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David Alan Gilbert" Cc: "Michael S . Tsirkin" , Marcel Apfelbaum , Markus Armbruster , Marcelo Tosatti , qemu-devel@nongnu.org, kvm@vger.kernel.org, Marc Morcos Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::649; envelope-from=3v087aQoKCpwI6N8IKN8KOCKKCHA.8KIMAIQ-9ARAHJKJCJQ.KNC@flex--marcmorcos.bounces.google.com; helo=mail-pl1-x649.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 11 Dec 2025 22:58:02 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1765511926251158500 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" - Fix 3 thread races detected by tsan - Change apicbase to 64 bit variable to reflect what it holds Signed-off-by: Marc Morcos --- hw/i386/kvm/apic.c | 12 ++++++++---- hw/intc/apic_common.c | 24 ++++++++++++++---------- include/hw/i386/apic_internal.h | 2 +- monitor/monitor.c | 8 +++++++- monitor/qmp.c | 2 ++ target/i386/kvm/kvm.c | 3 +++ util/thread-pool.c | 24 +++++++++++------------- 7 files changed, 46 insertions(+), 29 deletions(-) diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 82355f0463..b9b03c529f 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -34,9 +34,10 @@ static inline uint32_t kvm_apic_get_reg(struct kvm_lapic= _state *kapic, static void kvm_put_apic_state(APICCommonState *s, struct kvm_lapic_state = *kapic) { int i; + uint64_t apicbase =3D qatomic_read__nocheck(&s->apicbase); =20 memset(kapic, 0, sizeof(*kapic)); - if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { + if (kvm_has_x2apic_api() && apicbase & MSR_IA32_APICBASE_EXTD) { kvm_apic_set_reg(kapic, 0x2, s->initial_apic_id); } else { kvm_apic_set_reg(kapic, 0x2, s->id << 24); @@ -63,8 +64,9 @@ static void kvm_put_apic_state(APICCommonState *s, struct= kvm_lapic_state *kapic void kvm_get_apic_state(APICCommonState *s, struct kvm_lapic_state *kapic) { int i, v; + uint64_t apicbase =3D qatomic_read__nocheck(&s->apicbase); =20 - if (kvm_has_x2apic_api() && s->apicbase & MSR_IA32_APICBASE_EXTD) { + if (kvm_has_x2apic_api() && apicbase & MSR_IA32_APICBASE_EXTD) { assert(kvm_apic_get_reg(kapic, 0x2) =3D=3D s->initial_apic_id); } else { s->id =3D kvm_apic_get_reg(kapic, 0x2) >> 24; @@ -97,7 +99,7 @@ void kvm_get_apic_state(APICCommonState *s, struct kvm_la= pic_state *kapic) =20 static int kvm_apic_set_base(APICCommonState *s, uint64_t val) { - s->apicbase =3D val; + qatomic_set__nocheck(&s->apicbase, val); return 0; } =20 @@ -140,12 +142,14 @@ static void kvm_apic_put(CPUState *cs, run_on_cpu_dat= a data) APICCommonState *s =3D data.host_ptr; struct kvm_lapic_state kapic; int ret; + uint64_t apicbase; =20 if (is_tdx_vm()) { return; } =20 - kvm_put_apicbase(s->cpu, s->apicbase); + apicbase =3D qatomic_read__nocheck(&s->apicbase); + kvm_put_apicbase(s->cpu, apicbase); kvm_put_apic_state(s, &kapic); =20 ret =3D kvm_vcpu_ioctl(CPU(s->cpu), KVM_SET_LAPIC, &kapic); diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index ec9e978b0b..9e42189d8a 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -19,6 +19,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/atomic.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" @@ -52,8 +53,9 @@ int cpu_set_apic_base(APICCommonState *s, uint64_t val) uint64_t cpu_get_apic_base(APICCommonState *s) { if (s) { - trace_cpu_get_apic_base((uint64_t)s->apicbase); - return s->apicbase; + uint64_t apicbase =3D qatomic_read__nocheck(&s->apicbase); + trace_cpu_get_apic_base(apicbase); + return apicbase; } else { trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); return MSR_IA32_APICBASE_BSP; @@ -66,7 +68,7 @@ bool cpu_is_apic_enabled(APICCommonState *s) return false; } =20 - return s->apicbase & MSR_IA32_APICBASE_ENABLE; + return qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_ENABLE; } =20 void cpu_set_apic_tpr(APICCommonState *s, uint8_t val) @@ -223,9 +225,9 @@ void apic_designate_bsp(APICCommonState *s, bool bsp) } =20 if (bsp) { - s->apicbase |=3D MSR_IA32_APICBASE_BSP; + qatomic_fetch_or(&s->apicbase, MSR_IA32_APICBASE_BSP); } else { - s->apicbase &=3D ~MSR_IA32_APICBASE_BSP; + qatomic_fetch_and(&s->apicbase, ~MSR_IA32_APICBASE_BSP); } } =20 @@ -233,10 +235,11 @@ static void apic_reset_common(DeviceState *dev) { APICCommonState *s =3D APIC_COMMON(dev); APICCommonClass *info =3D APIC_COMMON_GET_CLASS(s); - uint32_t bsp; + uint64_t bsp; =20 - bsp =3D s->apicbase & MSR_IA32_APICBASE_BSP; - s->apicbase =3D APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE; + bsp =3D qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_BSP; + qatomic_set__nocheck(&s->apicbase, + APIC_DEFAULT_ADDRESS | bsp | MSR_IA32_APICBASE_ENABLE); s->id =3D s->initial_apic_id; =20 kvm_reset_irq_delivered(); @@ -363,7 +366,7 @@ static const VMStateDescription vmstate_apic_common =3D= { .post_load =3D apic_dispatch_post_load, .priority =3D MIG_PRI_APIC, .fields =3D (const VMStateField[]) { - VMSTATE_UINT32(apicbase, APICCommonState), + VMSTATE_UINT64(apicbase, APICCommonState), VMSTATE_UINT8(id, APICCommonState), VMSTATE_UINT8(arb_id, APICCommonState), VMSTATE_UINT8(tpr, APICCommonState), @@ -405,7 +408,8 @@ static void apic_common_get_id(Object *obj, Visitor *v,= const char *name, APICCommonState *s =3D APIC_COMMON(obj); uint32_t value; =20 - value =3D s->apicbase & MSR_IA32_APICBASE_EXTD ? s->initial_apic_id : = s->id; + value =3D qatomic_read__nocheck(&s->apicbase) & MSR_IA32_APICBASE_EXTD= ? + s->initial_apic_id : s->id; visit_type_uint32(v, name, &value, errp); } =20 diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_interna= l.h index 4a62fdceb4..32ce2c821e 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -158,7 +158,7 @@ struct APICCommonState { =20 MemoryRegion io_memory; X86CPU *cpu; - uint32_t apicbase; + uint64_t apicbase; /* All accesses to apicbase must use qatomic helper= s. */ uint8_t id; /* legacy APIC ID */ uint32_t initial_apic_id; uint8_t version; diff --git a/monitor/monitor.c b/monitor/monitor.c index c5a5d30877..f3bc4f0202 100644 --- a/monitor/monitor.c +++ b/monitor/monitor.c @@ -338,15 +338,21 @@ static void monitor_qapi_event_emit(QAPIEvent event, = QDict *qdict) { Monitor *mon; MonitorQMP *qmp_mon; + bool send; =20 trace_monitor_protocol_event_emit(event, qdict); QTAILQ_FOREACH(mon, &mon_list, entry) { + qemu_mutex_lock(&mon->mon_lock); if (!monitor_is_qmp(mon)) { + qemu_mutex_unlock(&mon->mon_lock); continue; } =20 qmp_mon =3D container_of(mon, MonitorQMP, common); - if (qmp_mon->commands !=3D &qmp_cap_negotiation_commands) { + send =3D qmp_mon->commands !=3D &qmp_cap_negotiation_commands; + qemu_mutex_unlock(&mon->mon_lock); + + if (send) { qmp_send_response(qmp_mon, qdict); } } diff --git a/monitor/qmp.c b/monitor/qmp.c index cb99a12d94..73c2fb8cbf 100644 --- a/monitor/qmp.c +++ b/monitor/qmp.c @@ -462,9 +462,11 @@ static void monitor_qmp_event(void *opaque, QEMUChrEve= nt event) =20 switch (event) { case CHR_EVENT_OPENED: + qemu_mutex_lock(&mon->common.mon_lock); mon->commands =3D &qmp_cap_negotiation_commands; monitor_qmp_caps_reset(mon); data =3D qmp_greeting(mon); + qemu_mutex_unlock(&mon->common.mon_lock); qmp_send_response(mon, data); qobject_unref(data); break; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 60c7981138..76bdef2c78 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5474,7 +5474,10 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run = *run) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; int ret; + bool nmi_pending =3D false; + bool smi_pending =3D false; =20 + bql_lock(); /* Inject NMI */ if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { diff --git a/util/thread-pool.c b/util/thread-pool.c index d2ead6b728..af49d4dfd9 100644 --- a/util/thread-pool.c +++ b/util/thread-pool.c @@ -18,6 +18,7 @@ #include "qemu/defer-call.h" #include "qemu/queue.h" #include "qemu/thread.h" +#include "qemu/atomic.h" #include "qemu/coroutine.h" #include "trace.h" #include "block/thread-pool.h" @@ -39,9 +40,9 @@ struct ThreadPoolElementAio { ThreadPoolFunc *func; void *arg; =20 - /* Moving state out of THREAD_QUEUED is protected by lock. After - * that, only the worker thread can write to it. Reads and writes - * of state and ret are ordered with memory barriers. + /* + * All access to state must be atomic, + * Use acquire/release ordering if relevant */ enum ThreadState state; int ret; @@ -105,15 +106,14 @@ static void *worker_thread(void *opaque) =20 req =3D QTAILQ_FIRST(&pool->request_list); QTAILQ_REMOVE(&pool->request_list, req, reqs); - req->state =3D THREAD_ACTIVE; + qatomic_set(&req->state, THREAD_ACTIVE); qemu_mutex_unlock(&pool->lock); =20 ret =3D req->func(req->arg); =20 req->ret =3D ret; - /* Write ret before state. */ - smp_wmb(); - req->state =3D THREAD_DONE; + /* _release to write ret before state. */ + qatomic_store_release(&req->state, THREAD_DONE); =20 qemu_bh_schedule(pool->completion_bh); qemu_mutex_lock(&pool->lock); @@ -180,7 +180,8 @@ static void thread_pool_completion_bh(void *opaque) =20 restart: QLIST_FOREACH_SAFE(elem, &pool->head, all, next) { - if (elem->state !=3D THREAD_DONE) { + /* _acquire to read state before ret. */ + if (qatomic_load_acquire(&elem->state) !=3D THREAD_DONE) { continue; } =20 @@ -189,9 +190,6 @@ restart: QLIST_REMOVE(elem, all); =20 if (elem->common.cb) { - /* Read state before ret. */ - smp_rmb(); - /* Schedule ourselves in case elem->common.cb() calls aio_poll= () to * wait for another request that completed at the same time. */ @@ -223,11 +221,11 @@ static void thread_pool_cancel(BlockAIOCB *acb) trace_thread_pool_cancel_aio(elem, elem->common.opaque); =20 QEMU_LOCK_GUARD(&pool->lock); - if (elem->state =3D=3D THREAD_QUEUED) { + if (qatomic_read(&elem->state) =3D=3D THREAD_QUEUED) { QTAILQ_REMOVE(&pool->request_list, elem, reqs); qemu_bh_schedule(pool->completion_bh); =20 - elem->state =3D THREAD_DONE; + qatomic_set(&elem->state, THREAD_DONE); elem->ret =3D -ECANCELED; } =20 --=20 2.52.0.239.gd5f0c6e74e-goog