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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Dec 2025 13:39:17.4976 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9550a51-8e53-4d69-9217-08de37f18416 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A672E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6021 Received-SPF: softfail client-ip=2a01:111:f403:c105::1; envelope-from=skolothumtho@nvidia.com; helo=CH1PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1765374078602158500 Install an event handler on the CMDQV vEVENTQ fd to read and propagate host received CMDQV errors to the guest. The handler runs in QEMU=E2=80=99s main loop, using a non-blocking fd regis= tered via qemu_set_fd_handler(). Signed-off-by: Shameer Kolothum --- hw/arm/tegra241-cmdqv.c | 80 +++++++++++++++++++++++++++++++++++++++++ hw/arm/tegra241-cmdqv.h | 2 ++ hw/arm/trace-events | 3 ++ 3 files changed, 85 insertions(+) diff --git a/hw/arm/tegra241-cmdqv.c b/hw/arm/tegra241-cmdqv.c index 812b027923..5b8a7bdff2 100644 --- a/hw/arm/tegra241-cmdqv.c +++ b/hw/arm/tegra241-cmdqv.c @@ -8,9 +8,12 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qemu/log.h" +#include "trace.h" =20 #include "hw/arm/smmuv3.h" +#include "hw/irq.h" #include "smmuv3-accel.h" #include "tegra241-cmdqv.h" =20 @@ -137,6 +140,79 @@ static uint64_t tegra241_cmdqv_read_vcmdq(Tegra241CMDQ= V *cmdqv, hwaddr offset, } } =20 +static void tegra241_cmdqv_event_read(void *opaque) +{ + Tegra241CMDQV *cmdqv =3D opaque; + struct { + struct iommufd_vevent_header hdr; + struct iommu_vevent_tegra241_cmdqv vevent; + } buf; + ssize_t readsz =3D sizeof(buf); + uint32_t last_seq =3D cmdqv->last_event_seq; + ssize_t bytes; + + bytes =3D read(cmdqv->veventq->veventq_fd, &buf, readsz); + if (bytes <=3D 0) { + if (errno =3D=3D EAGAIN || errno =3D=3D EINTR) { + return; + } + error_report("Tegra241 CMDQV: vEVENTQ: read failed (%s)", + strerror(errno)); + return; + } + + if (bytes < readsz) { + error_report("Tegra241 CMDQV: vEVENTQ: incomplete read (%zd/%zd by= tes)", + bytes, readsz); + return; + } + + if (buf.hdr.flags & IOMMU_VEVENTQ_FLAG_LOST_EVENTS) { + error_report("Tegra241 CMDQV: vEVENTQ has lost events"); + return; + } + + /* Check sequence in hdr for lost events if any */ + if (cmdqv->event_start) { + uint32_t expected =3D (last_seq =3D=3D INT_MAX) ? 0 : last_seq + 1; + + if (buf.hdr.sequence !=3D expected) { + uint32_t delta; + + if (buf.hdr.sequence >=3D last_seq) { + delta =3D buf.hdr.sequence - last_seq; + } else { + /* Handle wraparound from INT_MAX */ + delta =3D (INT_MAX - last_seq) + buf.hdr.sequence + 1; + } + error_report("Tegra241 CMDQV: vEVENTQ: detected lost %u event(= s)", + delta - 1); + } + } + + if (buf.vevent.lvcmdq_err_map[0] || buf.vevent.lvcmdq_err_map[1]) { + cmdqv->vintf_cmdq_err_map[0] =3D + buf.vevent.lvcmdq_err_map[0] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[1] =3D + (buf.vevent.lvcmdq_err_map[0] >> 32) & 0xffffffff; + cmdqv->vintf_cmdq_err_map[2] =3D + buf.vevent.lvcmdq_err_map[1] & 0xffffffff; + cmdqv->vintf_cmdq_err_map[3] =3D + (buf.vevent.lvcmdq_err_map[1] >> 32) & 0xffffffff; + for (int i =3D 0; i < 4; i++) { + cmdqv->cmdq_err_map[i] =3D cmdqv->vintf_cmdq_err_map[i]; + } + cmdqv->vi_err_map[0] |=3D 0x1; + qemu_irq_pulse(cmdqv->irq); + trace_tegra241_cmdqv_err_map( + cmdqv->vintf_cmdq_err_map[3], cmdqv->vintf_cmdq_err_map[2], + cmdqv->vintf_cmdq_err_map[1], cmdqv->vintf_cmdq_err_map[0]); + } + + cmdqv->last_event_seq =3D buf.hdr.sequence; + cmdqv->event_start =3D true; +} + static void tegra241_cmdqv_free_veventq(Tegra241CMDQV *cmdqv) { SMMUv3State *smmu =3D cmdqv->smmu; @@ -179,6 +255,10 @@ static bool tegra241_cmdqv_alloc_veventq(Tegra241CMDQV= *cmdqv, Error **errp) veventq->veventq_fd =3D veventq_fd; veventq->viommu =3D viommu; cmdqv->veventq =3D veventq; + + /* Set up event handler for veventq fd */ + fcntl(veventq_fd, F_SETFL, O_NONBLOCK); + qemu_set_fd_handler(veventq_fd, tegra241_cmdqv_event_read, NULL, cmdqv= ); return true; } =20 diff --git a/hw/arm/tegra241-cmdqv.h b/hw/arm/tegra241-cmdqv.h index ba7f2a0b1b..97eaef8a72 100644 --- a/hw/arm/tegra241-cmdqv.h +++ b/hw/arm/tegra241-cmdqv.h @@ -25,6 +25,8 @@ typedef struct Tegra241CMDQV { void *vcmdq_page0; IOMMUFDHWqueue *vcmdq[128]; IOMMUFDVeventq *veventq; + uint32_t last_event_seq; + bool event_start; =20 /* Register Cache */ uint32_t config; diff --git a/hw/arm/trace-events b/hw/arm/trace-events index 3457536fb0..76bda0efef 100644 --- a/hw/arm/trace-events +++ b/hw/arm/trace-events @@ -72,6 +72,9 @@ smmuv3_accel_unset_iommu_device(int devfn, uint32_t devid= ) "devfn=3D0x%x (idev dev smmuv3_accel_translate_ste(uint32_t vsid, uint32_t hwpt_id, uint64_t ste_1= , uint64_t ste_0) "vSID=3D0x%x hwpt_id=3D0x%x ste=3D%"PRIx64":%"PRIx64 smmuv3_accel_install_ste(uint32_t vsid, const char * type, uint32_t hwpt_i= d) "vSID=3D0x%x ste type=3D%s hwpt_id=3D0x%x" =20 +# tegra241-cmdqv +tegra241_cmdqv_err_map(uint32_t map3, uint32_t map2, uint32_t map1, uint32= _t map0) "hw irq received. error (hex) maps: %04X:%04X:%04X:%04X" + # strongarm.c strongarm_uart_update_parameters(const char *label, int speed, char parity= , int data_bits, int stop_bits) "%s speed=3D%d parity=3D%c data=3D%d stop= =3D%d" strongarm_ssp_read_underrun(void) "SSP rx underrun" --=20 2.43.0