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Tue, 09 Dec 2025 08:28:31 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Christian Stussak , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 1/4] Revert "target/arm: Re-use arm_is_psci_call() in HVF" Date: Tue, 9 Dec 2025 16:28:26 +0000 Message-ID: <20251209162829.1328559-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209162829.1328559-1-alex.bennee@linaro.org> References: <20251209162829.1328559-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1765297797173158500 This breaks a pure HVF (--disable-tcg) build because the fallback stub will always report false. This reverts commit 4695daacc068cd0aa9a91c0063c4f2a9ec9b7ba1. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Christian Stussak Message-ID: <20251209092459.1058313-2-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index de1e8fb8a05..70d34063df8 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1935,7 +1935,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) break; case EC_AA64_HVC: cpu_synchronize_state(cpu); - if (arm_is_psci_call(arm_cpu, EXCP_HVC)) { + if (arm_cpu->psci_conduit =3D=3D QEMU_PSCI_CONDUIT_HVC) { /* Do NOT advance $pc for HVC */ if (!hvf_handle_psci_call(cpu)) { trace_hvf_unknown_hvc(env->pc, env->xregs[0]); @@ -1949,7 +1949,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) break; case EC_AA64_SMC: cpu_synchronize_state(cpu); - if (arm_is_psci_call(arm_cpu, EXCP_SMC)) { + if (arm_cpu->psci_conduit =3D=3D QEMU_PSCI_CONDUIT_SMC) { /* Secure Monitor Call exception, we need to advance $pc */ advance_pc =3D true; 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Tue, 09 Dec 2025 08:28:31 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Christian Stussak , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 2/4] target/arm: ensure PSCI register updates are flushed Date: Tue, 9 Dec 2025 16:28:27 +0000 Message-ID: <20251209162829.1328559-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209162829.1328559-1-alex.bennee@linaro.org> References: <20251209162829.1328559-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1765297757454158500 When we handle a host call we report state back to the caller via registers. Set vcpu_dirty to indicate QEMU is currently the reference and hoist the flush_cpu_state() and make the call unconditional. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3228 Tested-by: Christian Stussak Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251209092459.1058313-3-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 70d34063df8..8e2940217a6 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1942,6 +1942,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) /* SMCCC 1.3 section 5.2 says every unknown SMCCC call ret= urns -1 */ env->xregs[0] =3D -1; } + cpu->vcpu_dirty =3D true; } else { trace_hvf_unknown_hvc(env->pc, env->xregs[0]); hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); @@ -1958,6 +1959,7 @@ static int hvf_handle_exception(CPUState *cpu, hv_vcp= u_exit_exception_t *excp) /* SMCCC 1.3 section 5.2 says every unknown SMCCC call ret= urns -1 */ env->xregs[0] =3D -1; } + cpu->vcpu_dirty =3D true; } else { trace_hvf_unknown_smc(env->xregs[0]); hvf_raise_exception(cpu, EXCP_UDEF, syn_uncategorized(), 1); @@ -1980,10 +1982,12 @@ static int hvf_handle_exception(CPUState *cpu, hv_v= cpu_exit_exception_t *excp) error_report("0x%llx: unhandled exception ec=3D0x%x", env->pc, ec); } =20 + /* flush any changed cpu state back to HVF */ + flush_cpu_state(cpu); + if (advance_pc) { uint64_t pc; =20 - flush_cpu_state(cpu); =20 r =3D hv_vcpu_get_reg(cpu->accel->fd, HV_REG_PC, &pc); assert_hvf_ok(r); --=20 2.47.3 From nobody Mon Feb 9 09:03:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1765297840; cv=none; d=zohomail.com; s=zohoarc; b=euzsvQCbNKW1w564vKWxh9C2sxEtQSoEGnjuMKDR10TBh5iz2CiBT2wq57B+275roU+92tAQs69UAAElIDv19boCT+sk9R/7NTA3qJCYtZjb90e8MIuMFwpty+prAf9uHpJtWs5rWsF89O79g7bB/Jhn8uCnQK36LAMW9DtATUI= ARC-Message-Signature: i=1; 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Tue, 09 Dec 2025 08:28:32 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alexander Graf , Mads Ynddal , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 3/4] target/arm: make HV_EXIT_REASON_CANCELED leave hvf_arch_vcpu_exec Date: Tue, 9 Dec 2025 16:28:28 +0000 Message-ID: <20251209162829.1328559-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209162829.1328559-1-alex.bennee@linaro.org> References: <20251209162829.1328559-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1765297843227158500 Without this we can spin tightly in the main HVF dispatch loop and never release the lock long enough. As a result the HMP never gets to run and shutting down the system deadlocks. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3228 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-ID: <20251209092459.1058313-4-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8e2940217a6..8288b605299 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -2020,6 +2020,7 @@ static int hvf_handle_vmexit(CPUState *cpu, hv_vcpu_e= xit_t *exit) break; case HV_EXIT_REASON_CANCELED: /* we got kicked, no exit to process */ + ret =3D -1; break; default: g_assert_not_reached(); --=20 2.47.3 From nobody Mon Feb 9 09:03:36 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1765297753; cv=none; d=zohomail.com; s=zohoarc; b=dGjfVBXjzNY6OE/tXCWWDYok/KPocthGrUxAbdTzls9FiZrdl9n7Y1VPD2qYjAnmxwMGW6uqmds0ryv/vbqfkuUL5TmloFRyYxPqd2rO3N2ennpC1z0/d1TC3DZ/sClUkGJ2z2x5ZqrFtVd1I0WS/uEdsK2gFxdF6SAamLgQhxI= ARC-Message-Signature: i=1; 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Tue, 09 Dec 2025 08:28:33 -0800 (PST) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Jessica Clarke , Richard Henderson , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [PULL 4/4] target/arm: handle unaligned PC during tlb probe Date: Tue, 9 Dec 2025 16:28:29 +0000 Message-ID: <20251209162829.1328559-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251209162829.1328559-1-alex.bennee@linaro.org> References: <20251209162829.1328559-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1765297757058158500 PC alignment faults have priority over instruction aborts and we have code to deal with this in the translation front-ends. However during tb_lookup we can see a potentially faulting probe which doesn't get a MemOp set. If the page isn't available this results in EC_INSNABORT (0x20) instead of EC_PCALIGNMENT (0x22). As there is no easy way to set the appropriate MemOp in the instruction fetch probe path lets just detect it in arm_cpu_tlb_fill_align() ahead of the main alignment check. We also teach arm_deliver_fault to deliver the right syndrome for MMU_INST_FETCH alignment issues. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3233 Tested-by: Jessica Clarke Reviewed-by: Richard Henderson Message-ID: <20251209092459.1058313-5-alex.bennee@linaro.org> Signed-off-by: Alex Benn=C3=A9e diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index f1983a5732e..5c689d3b69f 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -250,7 +250,11 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, fsr =3D compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); =20 if (access_type =3D=3D MMU_INST_FETCH) { - syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); + if (fi->type =3D=3D ARMFault_Alignment) { + syn =3D syn_pcalignment(); + } else { + syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); + } exc =3D EXCP_PREFETCH_ABORT; } else { bool gcs =3D regime_is_gcs(core_to_arm_mmu_idx(env, mmu_idx)); @@ -346,11 +350,18 @@ bool arm_cpu_tlb_fill_align(CPUState *cs, CPUTLBEntry= Full *out, vaddr address, } =20 /* - * Per R_XCHFJ, alignment fault not due to memory type has - * highest precedence. Otherwise, walk the page table and - * and collect the page description. + * PC alignment faults should be dealt with at translation time + * but we also need to catch them while being probed. + * + * Then per R_XCHFJ, alignment fault not due to memory type take + * precedence. Otherwise, walk the page table and and collect the + * page description. + * */ - if (address & ((1 << memop_alignment_bits(memop)) - 1)) { + if (access_type =3D=3D MMU_INST_FETCH && !cpu->env.thumb && + (address & 3)) { + fi->type =3D ARMFault_Alignment; + } else if (address & ((1 << memop_alignment_bits(memop)) - 1)) { fi->type =3D ARMFault_Alignment; } else if (!get_phys_addr(&cpu->env, address, access_type, memop, core_to_arm_mmu_idx(&cpu->env, mmu_idx), --=20 2.47.3