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Tue, 09 Dec 2025 08:01:31 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v2 2/4] hw/char: sifive_uart: Sync txwm interrupt pending status after TX FIFO enqueue Date: Wed, 10 Dec 2025 00:01:15 +0800 Message-ID: <20251209160117.1239596-3-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251209160117.1239596-1-frank.chang@sifive.com> References: <20251209160117.1239596-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1765296190471158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Currently, the txwm interrupt pending status is only updated when the asynchronous transmit handler runs. This can cause the txwm interrupt state to become unsynchronized between the SiFive UART and the interrupt controller. For example, when a txwm interrupt is raised, the corresponding APLIC pending bit is also set. However, if software later enqueues additional characters into the TX FIFO exceeding the transmit watermark, the APLIC pending bit may remain set because the txwm interrupt pending status is not updated at enqueue time. This issue has been observed on resource-constrained machines, where Linux reports spurious IRQ errors. In these cases, the asynchronous transmit handler is unable to drain the TX FIFO quickly enough to update the txwm pending status before software reads the ip register, which derives the txwm pending state directly from the actual number of characters in the TX FIFO. This commit fixes the issue by updating the txwm interrupt pending status immediately after enqueuing data into the TX FIFO, ensuring that the interrupt pending status between the SiFive UART and the interrupt controller remains synchronized. Signed-off-by: Frank Chang --- hw/char/sifive_uart.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 4a54dd52a1e..eff1766274e 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -124,12 +124,20 @@ static void sifive_uart_trigger_tx_fifo(SiFiveUARTSta= te *s) static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *b= uf, int size) { + uint32_t txcnt =3D SIFIVE_UART_GET_TXCNT(s->txctrl); + bool update_irq =3D false; + if (size > fifo8_num_free(&s->tx_fifo)) { size =3D fifo8_num_free(&s->tx_fifo); qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow.\n"); } =20 if (size > 0) { + if (fifo8_num_used(&s->tx_fifo) < txcnt && + (fifo8_num_used(&s->tx_fifo) + size) >=3D txcnt) { + update_irq =3D true; + } + fifo8_push_all(&s->tx_fifo, buf, size); } =20 @@ -137,6 +145,14 @@ static void sifive_uart_write_tx_fifo(SiFiveUARTState = *s, const uint8_t *buf, s->txfifo |=3D SIFIVE_UART_TXFIFO_FULL; } =20 + /* + * Update txwm interrupt pending status when the number of entries + * in the transmit FIFO crosses or reaches the watermark. + */ + if (update_irq) { + sifive_uart_update_irq(s); + } + sifive_uart_trigger_tx_fifo(s); } =20 --=20 2.43.0