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Tue, 09 Dec 2025 08:01:28 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Alistair Francis , Palmer Dabbelt , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , qemu-riscv@nongnu.org (open list:SiFive Machines), Frank Chang Subject: [PATCH v2 1/4] hw/char: sifive_uart: Implement txctrl.txen and rxctrl.rxen Date: Wed, 10 Dec 2025 00:01:14 +0800 Message-ID: <20251209160117.1239596-2-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251209160117.1239596-1-frank.chang@sifive.com> References: <20251209160117.1239596-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1765296184212158500 Content-Type: text/plain; charset="utf-8" From: Frank Chang Implement txctrl.txen and rxctrl.rxen as follows: * txctrl.txen The txen bit controls whether the Tx channel is active. When cleared, transmission of Tx FIFO contents is suppressed, and the txd pin is driven high. * rxctrl.rxen: The rxen bit controls whether the Rx channel is active. When cleared, the state of the rxd pin is ignored, and no characters will be enqueued into the Rx FIFO. Therefore, the Tx FIFO should not be dequeued when txctrl.txen is cleared, and the Rx FIFO should not be enqueued when rxctrl.rxen is cleared. Signed-off-by: Frank Chang --- hw/char/sifive_uart.c | 27 ++++++++++++++++++++------- include/hw/char/sifive_uart.h | 2 ++ 2 files changed, 22 insertions(+), 7 deletions(-) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index e7357d585a1..4a54dd52a1e 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -78,6 +78,11 @@ static gboolean sifive_uart_xmit(void *do_not_use, GIOCo= ndition cond, return G_SOURCE_REMOVE; } =20 + /* Don't pop the FIFO if transmit is disabled. */ + if (!SIFIVE_UART_TXEN(s->txctrl)) { + return G_SOURCE_REMOVE; + } + /* Don't pop the FIFO in case the write fails */ characters =3D fifo8_peek_bufptr(&s->tx_fifo, fifo8_num_used(&s->tx_fifo), &numptr); @@ -106,11 +111,19 @@ static gboolean sifive_uart_xmit(void *do_not_use, GI= OCondition cond, return G_SOURCE_REMOVE; } =20 -static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *b= uf, - int size) +static void sifive_uart_trigger_tx_fifo(SiFiveUARTState *s) { uint64_t current_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); =20 + if (!timer_pending(s->fifo_trigger_handle)) { + timer_mod(s->fifo_trigger_handle, current_time + + TX_INTERRUPT_TRIGGER_DELAY_NS); + } +} + +static void sifive_uart_write_tx_fifo(SiFiveUARTState *s, const uint8_t *b= uf, + int size) +{ if (size > fifo8_num_free(&s->tx_fifo)) { size =3D fifo8_num_free(&s->tx_fifo); qemu_log_mask(LOG_GUEST_ERROR, "sifive_uart: TX FIFO overflow.\n"); @@ -124,10 +137,7 @@ static void sifive_uart_write_tx_fifo(SiFiveUARTState = *s, const uint8_t *buf, s->txfifo |=3D SIFIVE_UART_TXFIFO_FULL; } =20 - if (!timer_pending(s->fifo_trigger_handle)) { - timer_mod(s->fifo_trigger_handle, current_time + - TX_INTERRUPT_TRIGGER_DELAY_NS); - } + sifive_uart_trigger_tx_fifo(s); } =20 static uint64_t @@ -184,6 +194,9 @@ sifive_uart_write(void *opaque, hwaddr addr, return; case SIFIVE_UART_TXCTRL: s->txctrl =3D val64; + if (SIFIVE_UART_TXEN(s->txctrl) && !fifo8_is_empty(&s->tx_fifo)) { + sifive_uart_trigger_tx_fifo(s); + } return; case SIFIVE_UART_RXCTRL: s->rxctrl =3D val64; @@ -231,7 +244,7 @@ static int sifive_uart_can_rx(void *opaque) { SiFiveUARTState *s =3D opaque; =20 - return s->rx_fifo_len < sizeof(s->rx_fifo); + return SIFIVE_UART_RXEN(s->rxctrl) && (s->rx_fifo_len < sizeof(s->rx_f= ifo)); } =20 static void sifive_uart_event(void *opaque, QEMUChrEvent event) diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h index 6486c3f4a5d..e216cacf693 100644 --- a/include/hw/char/sifive_uart.h +++ b/include/hw/char/sifive_uart.h @@ -51,6 +51,8 @@ enum { =20 #define SIFIVE_UART_TXFIFO_FULL 0x80000000 =20 +#define SIFIVE_UART_TXEN(txctrl) (txctrl & 0x1) +#define SIFIVE_UART_RXEN(rxctrl) (rxctrl & 0x1) #define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) #define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) =20 --=20 2.43.0