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Mon, 08 Dec 2025 16:01:48 -0800 (PST) Date: Tue, 09 Dec 2025 00:01:34 +0000 In-Reply-To: <20251209-aspeed-sgpio-v2-0-976e5f5790c2@google.com> Mime-Version: 1.0 References: <20251209-aspeed-sgpio-v2-0-976e5f5790c2@google.com> X-Mailer: b4 0.14.2 Message-ID: <20251209-aspeed-sgpio-v2-2-976e5f5790c2@google.com> Subject: [PATCH v2 2/6] hw/gpio/aspeed_sgpio: aspeed: Add QOM property accessors for SGPIO pins From: Yubin Zou To: qemu-devel@nongnu.org Cc: "=?utf-8?q?C=C3=A9dric_Le_Goater?=" , Peter Maydell , Steven Lee , Troy Lee , Jamin Lin , Andrew Jeffery , Joel Stanley , Fabiano Rosas , Laurent Vivier , Paolo Bonzini , Kane-Chen-AS , Nabih Estefan , qemu-arm@nongnu.org, Yubin Zou Content-Type: text/plain; charset="utf-8" Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::54a; envelope-from=37GY3aQYKCuchdKRWiPXXPUN.LXVZNVd-MNeNUWXWPWd.XaP@flex--yubinz.bounces.google.com; helo=mail-pg1-x54a.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, USER_IN_DEF_DKIM_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1765238541253158500 Content-Transfer-Encoding: quoted-printable This commit adds QOM property accessors for the Aspeed SGPIO pins. The `aspeed_sgpio_get_pin` and `aspeed_sgpio_set_pin` functions are implemented to get and set the level of individual SGPIO pins. These are then exposed as boolean properties on the SGPIO device object. Signed-off-by: Yubin Zou --- hw/gpio/aspeed_sgpio.c | 78 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 78 insertions(+) diff --git a/hw/gpio/aspeed_sgpio.c b/hw/gpio/aspeed_sgpio.c index 8676fa7ced134f1f62dc9e30b42c5fe6db3de268..efa7e574abe87e33e58ac88dba5= e3469c6702b83 100644 --- a/hw/gpio/aspeed_sgpio.c +++ b/hw/gpio/aspeed_sgpio.c @@ -91,6 +91,73 @@ static void aspeed_sgpio_2700_write(void *opaque, hwaddr= offset, uint64_t data, } } =20 +static bool aspeed_sgpio_get_pin_level(AspeedSGPIOState *s, int pin) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + return value & bit_mask; +} + +static void aspeed_sgpio_set_pin_level(AspeedSGPIOState *s, int pin, bool = level) +{ + uint32_t value =3D s->ctrl_regs[pin >> 1]; + bool is_input =3D !(pin % 2); + uint32_t bit_mask =3D 0; + + if (is_input) { + bit_mask =3D SGPIO_SERIAL_IN_VAL_MASK; + } else { + bit_mask =3D SGPIO_SERIAL_OUT_VAL_MASK; + } + + if (level) { + value |=3D bit_mask; + } else { + value &=3D ~bit_mask; + } + s->ctrl_regs[pin >> 1] =3D value; +} + +static void aspeed_sgpio_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level =3D true; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (sscanf(name, "sgpio%d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + level =3D aspeed_sgpio_get_pin_level(s, pin); + visit_type_bool(v, name, &level, errp); +} + +static void aspeed_sgpio_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + bool level; + int pin =3D 0xfff; + AspeedSGPIOState *s =3D ASPEED_SGPIO(obj); + + if (!visit_type_bool(v, name, &level, errp)) { + return; + } + if (sscanf(name, "sgpio%d", &pin) !=3D 1) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + aspeed_sgpio_set_pin_level(s, pin, level); +} + static const MemoryRegionOps aspeed_gpio_2700_ops =3D { .read =3D aspeed_sgpio_2700_read, .write =3D aspeed_sgpio_2700_write, @@ -114,6 +181,16 @@ static void aspeed_sgpio_realize(DeviceState *dev, Err= or **errp) sysbus_init_mmio(sbd, &s->iomem); } =20 +static void aspeed_sgpio_init(Object *obj) +{ + for (int i =3D 0; i < ASPEED_SGPIO_MAX_PIN_PAIR * 2; i++) { + char *name =3D g_strdup_printf("sgpio%d", i); + object_property_add(obj, name, "bool", aspeed_sgpio_get_pin, + aspeed_sgpio_set_pin, NULL, NULL); + g_free(name); + } +} + static void aspeed_sgpio_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -143,6 +220,7 @@ static const TypeInfo aspeed_sgpio_ast2700_info =3D { .name =3D TYPE_ASPEED_SGPIO "-ast2700", .parent =3D TYPE_ASPEED_SGPIO, .class_init =3D aspeed_sgpio_2700_class_init, + .instance_init =3D aspeed_sgpio_init, }; =20 static void aspeed_sgpio_register_types(void) --=20 2.52.0.223.gf5cc29aaa4-goog