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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1765211888; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=IoPMT69hU7hgy+EBlQGMx7ULsNeZWjI7C3qwtY9/v0g=; b=bW2HSu6+OvcLbo/PtCv1nTy2a4ekKG/dBsaD7Tcm5zUTB7vrHgNdF1Cq8FG15TC7dZzlMg zURx0ldbLPPnO1ZUgQOk1zROdTpvLyJwOmAbsmq+vBqan7qvN5ccT785ixVGCthhiYbwM5 Z8oK9H3NJbkwErS5alChFdHnzq7KvEI= X-MC-Unique: R3kM3kNlOH2eZWyggFSUYA-1 X-Mimecast-MFC-AGG-ID: R3kM3kNlOH2eZWyggFSUYA_1765211884 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, richard.henderson@linaro.org, cohuck@redhat.com, sebott@redhat.com Cc: maz@kernel.org Subject: [PATCH 1/3] scripts: introduce scripts/update-aarch64-sysreg-code.py Date: Mon, 8 Dec 2025 17:37:03 +0100 Message-ID: <20251208163751.611186-2-eric.auger@redhat.com> In-Reply-To: <20251208163751.611186-1-eric.auger@redhat.com> References: <20251208163751.611186-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Introduce a script that takes as input the Registers.json file delivered in the AARCHMRS Features Model downloadable from the Arm Developer A-Profile Architecture Exploration Tools page: https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloads and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc under the form of DEF(, , , , , ). We only care about IDregs with opcodes satisfying: op0 =3D 3, op1 within [0, 3], crn =3D 0, crm within [0, 7], op2 within [0, = 7] Signed-off-by: Eric Auger --- This was tested with https://developer.arm.com/-/cdn-downloads/permalink/Ex= ploration-Tools-OS-Machine-Readable-Data/AARCHMRS_BSD/AARCHMRS_OPENSOURCE_A= _profile_FAT-2025-09_ASL0.tar.gz Discussion about undesired generated regs can be found in https://lore.kernel.org/all/CAFEAcA9OXi4v+hdBMamQv85HYp2EqxOA5=3DnfsdZ5E3nf= 8RP_pw@mail.gmail.com/ --- scripts/update-aarch64-sysreg-code.py | 133 ++++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100755 scripts/update-aarch64-sysreg-code.py diff --git a/scripts/update-aarch64-sysreg-code.py b/scripts/update-aarch64= -sysreg-code.py new file mode 100755 index 0000000000..c7b31035d1 --- /dev/null +++ b/scripts/update-aarch64-sysreg-code.py @@ -0,0 +1,133 @@ +#!/usr/bin/env python3 + +# This script takes as input the Registers.json file delivered in +# the AARCHMRS Features Model downloadable from the Arm Developer +# A-Profile Architecture Exploration Tools page: +# https://developer.arm.com/Architectures/A-Profile%20Architecture#Downloa= ds +# and outputs the list of ID regs in target/arm/cpu-sysregs.h.inc +# under the form of DEF(, , , , , ) +# +# Copyright (C) 2025 Red Hat, Inc. +# +# Authors: Eric Auger +# +# SPDX-License-Identifier: GPL-2.0-or-later + + +import json +import os +import sys + +# returns the int value of a given @opcode for a reg @encoding +def get_opcode(encoding, opcode): + fvalue =3D encoding.get(opcode) + if fvalue: + value =3D fvalue.get('value') + if isinstance(value, str): + value =3D value.strip("'") + value =3D int(value,2) + return value + return -1 + +def extract_idregs_from_registers_json(filename): + """ + Load a Registers.json file and extract all ID registers, decode their + opcode and dump the information in target/arm/cpu-sysregs.h.inc + + Args: + filename (str): The path to the Registers.json + returns: + idregs: list of ID regs and their encoding + """ + if not os.path.exists(filename): + print(f"Error: {filename} could not be found!") + return {} + + try: + with open(filename, 'r') as f: + register_data =3D json.load(f) + + except json.JSONDecodeError: + print(f"Could not decode json from '{filename}'!") + return {} + except Exception as e: + print(f"Unexpected error while reading {filename}: {e}") + return {} + + registers =3D [r for r in register_data if isinstance(r, dict) and \ + r.get('_type') =3D=3D 'Register'] + + idregs =3D {} + + # Some regs have op code values like 000x, 001x. Anyway we don't need + # them. Besides some regs are undesired in the generated file such as + # CCSIDR_EL1 and CCSIDR2_EL1 which are arrays of regs. Also exclude + # VMPIDR_EL2 and VPIDR_EL2 which are outside of the IDreg scope we + # are interested in and are tricky to decode as their system accessor + # refer to MPIDR_EL1/MIDR_EL1 respectively + + skiplist =3D ['ALLINT', 'PM', 'S1_', 'S3_', 'SVCR', \ + 'CCSIDR_EL1', 'CCSIDR2_EL1', 'VMPIDR_EL2', 'VPIDR_EL2'] + + for register in registers: + reg_name =3D register.get('name') + + is_skipped =3D any(term in (reg_name or "").upper() for term in sk= iplist) + + if reg_name and not is_skipped: + accessors =3D register.get('accessors', []) + + for accessor in accessors: + type =3D accessor.get('_type') + if type in ['Accessors.SystemAccessor']: + encoding_list =3D accessor.get('encoding') + + if isinstance(encoding_list, list) and encoding_list a= nd \ + isinstance(encoding_list[0], dict): + encoding_wrapper =3D encoding_list[0] + encoding_source =3D encoding_wrapper.get('encoding= s', \ + encoding_wr= apper) + + if isinstance(encoding_source, dict): + op0 =3D get_opcode(encoding_source, 'op0') + op1 =3D get_opcode(encoding_source, 'op1') + op2 =3D get_opcode(encoding_source, 'op2') + crn =3D get_opcode(encoding_source, 'CRn') + crm =3D get_opcode(encoding_source, 'CRm') + encoding_str=3Df"{op0} {op1} {crn} {crm} {= op2}" + + # ID regs are assumed within this scope + if op0 =3D=3D 3 and (op1 =3D=3D 0 or op1 =3D=3D 1 or op1 = =3D=3D 3) and \ + crn =3D=3D 0 and (crm >=3D 0 and crm <=3D 7) and (op2 >= =3D 0 and op2 <=3D 7): + idregs[reg_name] =3D encoding_str + + return idregs + +if __name__ =3D=3D "__main__": + # Single arg expectedr: the path to the Registers.json file + if len(sys.argv) < 2: + print("Usage: scripts/update-aarch64-sysreg-code.py ") + sys.exit(1) + else: + json_file_path =3D sys.argv[1] + + extracted_registers =3D extract_idregs_from_registers_json(json_file_p= ath) + + if extracted_registers: + output_list =3D extracted_registers.items() + + # Sort by register name + sorted_output =3D sorted(output_list, key=3Dlambda item: item[0]) + + # format lines as DEF(, , , , , ) + final_output =3D "" + for reg_name, encoding in sorted_output: + reformatted_encoding =3D encoding.replace(" ", ", ") + final_output +=3D f"DEF({reg_name}, {reformatted_encoding})\n" + + with open("target/arm/cpu-sysregs.h.inc", 'w') as f: + f.write("/* SPDX-License-Identifier: BSD-3-Clause */\n\n") + f.write("/* This file is autogenerated by ") + f.write("scripts/update-aarch64-sysreg-code.py */\n\n") + f.write(final_output) + print(f"updated target/arm/cpu-sysregs.h.inc") --=20 2.52.0