From nobody Sun Dec 14 12:10:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1765000808; cv=none; d=zohomail.com; s=zohoarc; b=FlW3znmUT8DgbFEFDMvYokv0SCZfizRrwlCG7kJLYC7Mneo0iE55lS0+oIWsV265AFKmYRmBeG4jacGPQkwqpuO1RqcuSqn52BrGnDBqbt1/mF8OSsLWL/AJPARqg7ePEJaGfJQh0XXM/K0QA4EFQfDiYhcD8V/pcC82ZfVahrc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765000808; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9v9iWDgBCYpeHMTsm+20QdFqUeyuim+UMCMe+GTkr2c=; b=X5FcD+ADqWlWSW7jcUPdVg//1h7Wya/JbbTN9eNg0wyXxFdyQiVX9QHmcf1TdpRAEE1cFmChS7o3yzrUzczrnPEVIZnFsFoxkfeX7Vm3B0QOB3G7zhqLJlS1SLm++I7PO9YH4mAnLBaZfQuie9mAZqOEbHeA6bVOvuCxqlBj4c8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1765000808513382.9757222090309; Fri, 5 Dec 2025 22:00:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vRlJn-0004Hh-OJ; Sat, 06 Dec 2025 00:58:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vRlJc-0004EM-Hk; Sat, 06 Dec 2025 00:58:46 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vRlJZ-0005ZK-JD; Sat, 06 Dec 2025 00:58:43 -0500 Received: from pps.filterd (m0360083.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5B62kplU022887; Sat, 6 Dec 2025 05:58:40 GMT Received: from ppma11.dal12v.mail.ibm.com (db.9e.1632.ip4.static.sl-reverse.com [50.22.158.219]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 4avc0jgg5g-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 06 Dec 2025 05:58:39 +0000 (GMT) Received: from pps.filterd (ppma11.dal12v.mail.ibm.com [127.0.0.1]) by ppma11.dal12v.mail.ibm.com (8.18.1.2/8.18.1.2) with ESMTP id 5B6429aw029392; Sat, 6 Dec 2025 05:58:39 GMT Received: from smtprelay02.fra02v.mail.ibm.com ([9.218.2.226]) by ppma11.dal12v.mail.ibm.com (PPS) with ESMTPS id 4ardv20qbw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 06 Dec 2025 05:58:38 +0000 Received: from smtpav03.fra02v.mail.ibm.com (smtpav03.fra02v.mail.ibm.com [10.20.54.102]) by smtprelay02.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 5B65wZaF51708326 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 6 Dec 2025 05:58:35 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 423C820043; Sat, 6 Dec 2025 05:58:35 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id AFAF820040; Sat, 6 Dec 2025 05:58:32 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com (unknown [9.39.31.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 6 Dec 2025 05:58:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=9v9iWDgBCYpeHMTsm +20QdFqUeyuim+UMCMe+GTkr2c=; b=Q/R3IHacWyKr2yBqHEesKAO53ISZtwc/0 clL/1KuDCKLMHqK1NlnZ8lM1mlK7MzhatCA64yuXngtNH099vRb/odVbOtZY8gRN hhe6Q4QgfcadB0aVDi6pRqFvKZ/Tz41mqNLqiF9EIjAG1nXlHDMoOKBiQLD22A+p z41uhNioVhgsukxDbtkWKzmG6ZFzeAJGOh6semAosaXOBLG5+pMIUZHJIaUhvdYd CuleimTH6Am+7VdNTicRmLPQKr91ufArvuhsfJuYCDk30NeHtUgz2FGe/VcZ2IVz 9YuMRSAiS4VjZ0p+yFYTp4IQhlZv3fWaNX/tSnKcXq5Wq+u5EIzkg== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 7/9] pnv/mpipl: Write the preserved CPU and MDRT state Date: Sat, 6 Dec 2025 11:26:46 +0530 Message-ID: <20251206055648.1908734-8-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=Cf8FJbrl c=1 sm=1 tr=0 ts=6933c60f cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=9s9mwq7jZm2NEmiXaqsA:9 X-Proofpoint-ORIG-GUID: YIoDKON1DRc_NeoFEgNesiujKMh9xS1p X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAxNiBTYWx0ZWRfX6fxOOeltcReR cldKTfDD8JIvHK6kFoirP5DQBTCYRVK5A5IgFAdsLrAI4NgN3ASd9DwyGo8cHA8+XpbOY83QpIJ EIVpR2zEpybLiLkrgmb8nMUIx2v2hp7YA/Ju6jrdF/yM9EFqBYZ9yVyTqlFn37AcFUIFNwQKdHl qRfiNAOfHWObVrDO42UeBN0CxLjMVnsU/ZUNZrdqiDTgBor6hA+n3+rNk7iTCCVZZH1fMsRfPpP GDCFLMM7sQJNh/ltUfAt2naDWjK08gdfsM/Syr/HwLVztSLxs8DSnBK2b2nkRsgLyH79mSWcSdc OMzIaxCFxGx8Adro+/XY45esxUOkpJalQp+S3IWJCZDEMVAzt6UJGYljbrI7SL98Bg8TGm+mTzD /FIjSR8aA/L1GvnIUsZ0Mo01Y2s9sA== X-Proofpoint-GUID: YIoDKON1DRc_NeoFEgNesiujKMh9xS1p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_09,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060016 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000809297019200 Content-Type: text/plain; charset="utf-8" Logic for preserving the CPU registers and memory regions has been done in previous patches. Write those data at the relevant memory address, such as PROC_DUMP_AREA for CPU registers, and MDRT for preserved memory regions. Also export "mpipl-boot" device tree node, for kernel to know that it's a 'dump active' boot Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 31 ++++++++++++- hw/ppc/pnv_mpipl.c | 103 +++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 1 + 3 files changed, 134 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 643558f374e9..7c36f3a00e90 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -750,6 +750,7 @@ static void pnv_reset(MachineState *machine, ResetType = type) PnvMachineState *pnv =3D PNV_MACHINE(machine); IPMIBmc *bmc; void *fdt; + int node_offset; =20 qemu_devices_reset(type); =20 @@ -780,7 +781,35 @@ static void pnv_reset(MachineState *machine, ResetType= type) _FDT((fdt_pack(fdt))); } =20 - if (!pnv->mpipl_state.is_next_boot_mpipl) { + /* + * If it's a MPIPL boot, add the "mpipl-boot" property, and reset the + * boolean for MPIPL boot for next boot + */ + if (pnv->mpipl_state.is_next_boot_mpipl) { + void *fdt_copy =3D g_malloc0(FDT_MAX_SIZE); + + /* Write the preserved MDRT and CPU State Data */ + do_mpipl_write(pnv); + + /* Create a writable copy of the fdt */ + _FDT((fdt_open_into(fdt, fdt_copy, FDT_MAX_SIZE))); + + node_offset =3D fdt_path_offset(fdt_copy, "/ibm,opal/dump"); + _FDT((fdt_appendprop_u64(fdt_copy, node_offset, "mpipl-boot", 1))); + + /* Update the fdt, and free the original fdt */ + if (fdt !=3D machine->fdt) { + /* + * Only free the fdt if it's not machine->fdt, to prevent + * double free, since we already free machine->fdt later + */ + g_free(fdt); + } + fdt =3D fdt_copy; + + /* This boot is an MPIPL, reset the boolean for next boot */ + pnv->mpipl_state.is_next_boot_mpipl =3D false; + } else { /* * Set the "Thread Register State Entry Size", so that firmware can * allocate enough memory to capture CPU state in the event of a diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c index 8b41938c2e87..3c9755a6c440 100644 --- a/hw/ppc/pnv_mpipl.c +++ b/hw/ppc/pnv_mpipl.c @@ -19,6 +19,8 @@ (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF) #define MDDT_TABLE_RELOCATED \ (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF) +#define MDRT_TABLE_RELOCATED \ + (pnv->mpipl_state.skiboot_base + MDRT_TABLE_OFF) #define PROC_DUMP_RELOCATED \ (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF) =20 @@ -263,6 +265,100 @@ static void pnv_mpipl_preserve_cpu_state(PnvMachineSt= ate *pnv) } } =20 +static void pnv_mpipl_write_cpu_state(PnvMachineState *pnv) +{ + MpiplProcDumpArea *proc_area =3D &pnv->mpipl_state.proc_area; + MpiplPreservedCPUState *cpu_state =3D pnv->mpipl_state.cpu_states; + const uint32_t num_cpu_states =3D pnv->mpipl_state.num_cpu_states; + hwaddr next_regentries_hdr; + + if (be32_to_cpu(proc_area->alloc_size) < + (num_cpu_states * sizeof(MpiplPreservedCPUState))) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Size of buffer allocate by skiboot (%u bytes) is not" + "enough to save all CPUs registers needed (%ld bytes)", + be32_to_cpu(proc_area->alloc_size), + num_cpu_states * sizeof(MpiplPreservedCPUState)); + + return; + } + + proc_area->version =3D PROC_DUMP_AREA_VERSION_P9; + + /* + * This is the stride kernel/firmware should use to jump from a + * register entries header to next CPU's header + */ + proc_area->thread_size =3D cpu_to_be32(sizeof(MpiplPreservedCPUState)); + + /* Write the header and register entries for each CPU */ + next_regentries_hdr =3D be64_to_cpu(proc_area->alloc_addr) & (~HRMOR_B= IT); + for (int i =3D 0; i < num_cpu_states; ++i) { + cpu_physical_memory_write(next_regentries_hdr, &cpu_state->hdr, + sizeof(MpiplRegDataHdr)); + + cpu_physical_memory_write(next_regentries_hdr + sizeof(MpiplRegDat= aHdr), + &cpu_state->reg_entries, + NUM_REGS_PER_CPU * sizeof(MpiplRegEntry)); + + /* + * According to HDAT section: "15.3.1.5 Architected Register Data = content": + * + * The next register entries header will be at current header + + * "Thread Register State Entry size" + * + * Note: proc_area.thread_size =3D=3D sizeof(MpiplPreservedCPUStat= e) + */ + next_regentries_hdr +=3D sizeof(MpiplPreservedCPUState); + ++cpu_state; + } + + /* Point the destination address to the preserved memory region */ + proc_area->dest_addr =3D proc_area->alloc_addr; + proc_area->act_size =3D cpu_to_be32(num_cpu_states * + sizeof(MpiplPreservedCPUState)); + + cpu_physical_memory_write(PROC_DUMP_AREA_OFF, proc_area, + sizeof(MpiplProcDumpArea)); +} + +static void pnv_mpipl_write_mdrt(PnvMachineState *pnv) +{ + MpiplPreservedState *state =3D &pnv->mpipl_state; + AddressSpace *default_as =3D &address_space_memory; + MemTxResult io_result; + MemTxAttrs attrs; + + /* Mark the memory transactions as privileged memory access */ + attrs.user =3D 0; + attrs.memory =3D 1; + + /* + * Generally writes from platform during MPIPL don't go to a relocated + * skiboot address + * + * Though for MDRT we are doing so, as this is the address skiboot + * considers by default for MDRT + * + * MDRT/MDST/MDDT base addresses are actually meant to be shared by + * platform in SPIRA structures. + * + * Not implementing SPIRA as it increases complexity for no gains. + * Using the default address skiboot expects for MDRT, which is the + * relocated MDRT, hence writing to it + * + * Other tables like MDST/MDDT should not be written to relocated + * addresses, as skiboot will overwrite anything from SKIBOOT_BASE till + * SKIBOOT_BASE+SKIBOOT_SIZE (which is 0x30000000-0x31c00000 by defaul= t) + */ + io_result =3D address_space_write(default_as, MDRT_TABLE_RELOCATED, at= trs, + state->mdrt_table, + state->num_mdrt_entries * sizeof(MdrtTableEntry)); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "MPIPL: Failed to write MDRT table\= n"); + } +} + void do_mpipl_preserve(PnvMachineState *pnv) { pause_all_vcpus(); @@ -283,3 +379,10 @@ void do_mpipl_preserve(PnvMachineState *pnv) */ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } + +void do_mpipl_write(PnvMachineState *pnv) +{ + pnv_mpipl_write_mdrt(pnv); + pnv_mpipl_write_cpu_state(pnv); +} + diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 02baa0012460..a71e968c32e0 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -295,5 +295,6 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); =20 /* MPIPL helpers */ void do_mpipl_preserve(PnvMachineState *pnv); +void do_mpipl_write(PnvMachineState *pnv); =20 #endif /* PPC_PNV_H */ --=20 2.52.0