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Sat, 6 Dec 2025 05:58:19 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id CD40420040; Sat, 6 Dec 2025 05:58:16 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com (unknown [9.39.31.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 6 Dec 2025 05:58:16 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=WXAbInoT68uGejwRc twGK6rViOYGNcdONtCfPHF5hx8=; b=NU+Cl2wxXZHztCSm+sSkEWQHZBvzLVSyC PE/1VAts9F73moA7n3t0RcMYWME+X0Sz8aDtncL9DfRT8Kz3lpxkOoVwGJ8z07UQ fz1Vrvi42wxxTqmbcM3y5/SFOeBsZJOgPP0OvcTttndwpl9qnD+ODSJym0Y1fni2 xsA+SrVEPxSM+sd2jkh/xjSXSlFSElL/rr7bmB4fx1qXHK5mm26CieaqY3v8mShv OVzlKWgC+vcH/ZhFwAqUk8JdBUKjq7uOdbA6cmPcpgOpfnRhrIKsTPjn987i+6EI i3e9BNc3om2wcbrg/vZCFDohsT326wDo4LS9EtJy32DZp/HPMHsAQ== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 1/9] hw/ppc: Move SBE host doorbell function to top of file Date: Sat, 6 Dec 2025 11:26:40 +0530 Message-ID: <20251206055648.1908734-2-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAyMCBTYWx0ZWRfX1MVWpgbLN3q7 UAqlUM9bfdjkYoZgDD3nvbO9gLEMl5LU9NhRiudlj0WrOUi/h6CGejpKHIX4r95atOMD/JiMbZX kStnxJ/dPSN7mzpZVfAOgotkXwYix8GKlzsD/s/eSzbku9tLHhWYf9MATjVw2HEmhCc9DRglkl/ 8Ne2yKidPJdIML3wILpZB4mHsCp0i2f56+3QWybqMYVP4iERPaDFpYDHLOVQsesu/6kuurSGjch dhChRDCXgM2Le2mpxqzYDkjoZ2rlUSI98hxotuLc4RUfhuRmCkAFbBXM6cwt8GNt2PmJIIGQarA evyK6xWWkx/b9WxnxiFs+PtCN1zl3LRs3BYECJXqFUQzh/1QcIGi+SqmBM8MqVA2V6p3B11DB+k XDitNNvnBfPCx4VJbcBP8mMA3WvyxA== X-Authority-Analysis: v=2.4 cv=S/DUAYsP c=1 sm=1 tr=0 ts=6933c5ff cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=Cz7AoQ69vTHEakZR_RYA:9 X-Proofpoint-ORIG-GUID: 2OkVG0BBIofgT17B29lmCdQRqO9aClX_ X-Proofpoint-GUID: 2OkVG0BBIofgT17B29lmCdQRqO9aClX_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-06_01,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 clxscore=1015 impostorscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 bulkscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000763019019200 Content-Type: text/plain; charset="utf-8" Moved 'pnv_sbe_set_host_doorbell' as-it-is to above 'pnv_sbe_power9_xscom_ctrl_write'. This is done since in a future patch, S0 interrupt implementation uses 'pnv_sbe_set_host_doorbell', hence the host doorbell function needs to be declared/defined before 'pnv_sbe_power9_xscom_ctrl_write' where we implement the S0 interrupt. No functional change. Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index 34dc013d47bb..b9b28c5deaef 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -80,6 +80,15 @@ #define SBE_CONTROL_REG_S0 PPC_BIT(14) #define SBE_CONTROL_REG_S1 PPC_BIT(15) =20 +static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val) +{ + val &=3D SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */ + sbe->host_doorbell =3D val; + + trace_pnv_sbe_reg_set_host_doorbell(val); + qemu_set_irq(sbe->psi_irq, !!val); +} + struct sbe_msg { uint64_t reg[4]; }; @@ -125,15 +134,6 @@ static const MemoryRegionOps pnv_sbe_power9_xscom_ctrl= _ops =3D { .endianness =3D DEVICE_BIG_ENDIAN, }; =20 -static void pnv_sbe_set_host_doorbell(PnvSBE *sbe, uint64_t val) -{ - val &=3D SBE_HOST_RESPONSE_MASK; /* Is this right? What does HW do? */ - sbe->host_doorbell =3D val; - - trace_pnv_sbe_reg_set_host_doorbell(val); - qemu_set_irq(sbe->psi_irq, !!val); -} - /* SBE Target Type */ #define SBE_TARGET_TYPE_PROC 0x00 #define SBE_TARGET_TYPE_EX 0x01 --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1765000786; cv=none; d=zohomail.com; s=zohoarc; b=Gg7EkdMLX1JNcXarvzxi9Ocp75xK53E1pv40Jv97rKGJVoutn2ohDAqhZiuFQCasxb3wEPvqfQ5wxzugMLjIDiDCgvSvKuVzNMNptpvuB5zyvO/4Wghn0eGQxMaH/3J5z1Xp3W5YPxKjb5/ZCFP2K4JA1eBRAOWeq988A6gg8dk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765000786; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Sat, 6 Dec 2025 05:58:21 GMT Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8BF9520043; Sat, 6 Dec 2025 05:58:21 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 89A4C20040; Sat, 6 Dec 2025 05:58:19 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com (unknown [9.39.31.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 6 Dec 2025 05:58:19 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=ROy75RqasHOPQn/yH ra7gT4mwXrRJKa5wKQA5F3mCLQ=; b=CAsYvkP1Do3D7WdEhGIhRpLMzIUBWZvkX RQTcMqHtAd0oNpzcmM7mfx5MvGLazEsvH0Zxb3wqJWiDRgG3CiEbJiIIKuBt3X4o fgNJQkMy9T2f6r7U5qu3ZzJrpstQqPZOqSPUHd+D+98l8kRHyrJg25rtMQeNbfAm nETj7L/aNCVI4uyPCugiZHTzWz+XD86Bp7hEhrVuxtlGPmKOZCTXVUq+mThZFkuU xv1fAAOISu3yHs8GrOalN3DRs8e7XobCZEF4AlY/RRvBiYdQtYVZNNJLQmBRwSic PpcqYNtfXMYB51p+7Cqnj7UTC3vyQT5bChi6H+JnIccjlAY2Rzq9g== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 2/9] hw/ppc: Implement S0 SBE interrupt as cpu_pause then host reset Date: Sat, 6 Dec 2025 11:26:41 +0530 Message-ID: <20251206055648.1908734-3-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=Cf8FJbrl c=1 sm=1 tr=0 ts=6933c602 cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=atcXKtye3xvqEmVJAE4A:9 X-Proofpoint-ORIG-GUID: uDVTGdwLNzsEH_zgtH0g23nIvYVmpYmS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAxNiBTYWx0ZWRfX3S/LmDZpcTjs RFr+I2nu0HC9ngcO7WN81adXFyCn+T54wbOF+/GFs21bme78Nm8zLNoZKm/+jh+hbh5JD/1EVh6 U8Rw4YG6bAGfo5SSypOVsasd0zzjQ9GtU90sXcmrdJFf4y5/vofY2GHOMTCM3CclLvfkr6vKg3b gJ5L83c3RT7x4McAZ70FQLnco+c2V3lgRWxElIMkMfX06ByB1X2Ug/1w/1p60oH/kysxR8i+gOH Gu5Teilu2Gnu0/7F/j1X7PonrAjVlpDBIGT7sv4WSLamPeM8sXIaezua/TCk96z6hPQ6Wvjj49a gKkbG4uRHy1fPHLWGCEAr9Z/GIKgFY6CQnM5Ovex67mvJVhVy9qA27rwxDEytoS0XovGpcjgKNx IcC9PplS941ojALb5UCj4/3c5rGr/w== X-Proofpoint-GUID: uDVTGdwLNzsEH_zgtH0g23nIvYVmpYmS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_09,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060016 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000789166019200 Content-Type: text/plain; charset="utf-8" During MPIPL (aka fadump), OPAL triggers the S0 SBE interrupt to trigger MPIPL. Currently S0 interrupt is unimplemented in QEMU. Implement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the SBE's implementation of S0 seems to be basically "stop all clocks" and then "host reset". pause_vcpus is done in a later patch when register preserving support is added See 'stopClocksS0' in SBE source code for more information. Also log both S0 and S1 interrupts. Signed-off-by: Aditya Gupta --- hw/ppc/meson.build | 1 + hw/ppc/pnv_mpipl.c | 26 ++++++++++++++++++++++++++ hw/ppc/pnv_sbe.c | 29 +++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 6 ++++++ include/hw/ppc/pnv_mpipl.h | 19 +++++++++++++++++++ 5 files changed, 81 insertions(+) create mode 100644 hw/ppc/pnv_mpipl.c create mode 100644 include/hw/ppc/pnv_mpipl.h diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index f7dac87a2a48..c61fba4ec8f2 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -56,6 +56,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_pnor.c', 'pnv_nest_pervasive.c', 'pnv_n1_chiplet.c', + 'pnv_mpipl.c', )) # PowerPC 4xx boards ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c new file mode 100644 index 000000000000..d8c9b7a428b7 --- /dev/null +++ b/hw/ppc/pnv_mpipl.c @@ -0,0 +1,26 @@ +/* + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/runstate.h" +#include "hw/ppc/pnv.h" +#include "hw/ppc/pnv_mpipl.h" + +void do_mpipl_preserve(PnvMachineState *pnv) +{ + /* Mark next boot as Memory-preserving boot */ + pnv->mpipl_state.is_next_boot_mpipl =3D true; + + /* + * Do a guest reset. + * Next reset will see 'is_next_boot_mpipl' as true, and trigger MPIPL + * + * Requirement: + * GUEST_RESET is expected to NOT clear the memory, as is the case when + * this is merged + */ + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); +} diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index b9b28c5deaef..d004b7d5c225 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -21,11 +21,14 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" +#include "system/cpus.h" +#include "system/runstate.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_sbe.h" +#include "hw/ppc/pnv_mpipl.h" #include "trace.h" =20 /* @@ -113,11 +116,37 @@ static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *= opaque, hwaddr addr, static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvSBE *sbe =3D opaque; uint32_t offset =3D addr >> 3; =20 trace_pnv_sbe_xscom_ctrl_write(addr, val); =20 switch (offset) { + case SBE_CONTROL_REG_RW: + switch (val) { + case SBE_CONTROL_REG_S0: + qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n"); + + pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_R= ESPONSE_MASK); + + /* Preserve memory regions and CPU state, if MPIPL is register= ed */ + do_mpipl_preserve(pnv); + + /* + * Control may not come back here as 'do_mpipl_preserve' trigg= ers + * a guest reboot + */ + break; + case SBE_CONTROL_REG_S1: + qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n"); + break; + default: + qemu_log_mask(LOG_UNIMP, + "SBE: CONTROL_REG_RW: Unknown value: Ox%." + HWADDR_PRIx "\n", val); + } + break; default: qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%" HWADDR_PRIx "\n", addr >> 3); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index cbdddfc73cd4..02baa0012460 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -25,6 +25,7 @@ #include "hw/sysbus.h" #include "hw/ipmi/ipmi.h" #include "hw/ppc/pnv_pnor.h" +#include "hw/ppc/pnv_mpipl.h" =20 #define TYPE_PNV_CHIP "pnv-chip" =20 @@ -111,6 +112,8 @@ struct PnvMachineState { =20 bool big_core; bool lpar_per_core; + + MpiplPreservedState mpipl_state; }; =20 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id); @@ -290,4 +293,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); =20 #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip) =20 +/* MPIPL helpers */ +void do_mpipl_preserve(PnvMachineState *pnv); + #endif /* PPC_PNV_H */ diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h new file mode 100644 index 000000000000..c544984dc76d --- /dev/null +++ b/include/hw/ppc/pnv_mpipl.h @@ -0,0 +1,19 @@ +/* + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef PNV_MPIPL_H +#define PNV_MPIPL_H + +#include "qemu/osdep.h" + +typedef struct MpiplPreservedState MpiplPreservedState; + +/* Preserved state to be saved in PnvMachineState */ +struct MpiplPreservedState { + bool is_next_boot_mpipl; +}; + +#endif --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Sat, 6 Dec 2025 05:58:24 +0000 (GMT) Received: from smtpav03.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1D3752004B; Sat, 6 Dec 2025 05:58:22 +0000 (GMT) Received: from li-3c92a0cc-27cf-11b2-a85c-b804d9ca68fa.ibm.com (unknown [9.39.31.93]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTP; Sat, 6 Dec 2025 05:58:21 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=6cPgRN+TlNQStUUWI 2YeGjGMdaMcQjty9cbw/P60u3w=; b=k8xoFIIeWpQxqKRCMRRAvPo0L3PQwo4us Rq91T5Yby6RPk4QMJPy/FoCzoAOM3Nj37B9qEQRTiS2FyvqyN/0Tt+NZPKTI1aUO LJuKiK05GvlVSS4NgGUc0Cx0IOMj3tY8uy91hIC7XfDsF63CfdNBB0G+PUuJKC0x WTY7ktSD9JA/1F5/ov9fyFWETgLLSCaZqC1YBkB2IwoA80dRurwjq49o4Et5fKib wJQ06EsSGuNMQq9P5rHAUHdp8fb+UE05OCdZKE1hry0dMQmsAo58S70JpGV6LhT6 1BQK6WP5GL9ErXnTenrB+TNy9SB8b4a4JRM+5wNRTF6iyWfVeJLmg== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 3/9] hw/ppc: Handle stash command in PowerNV SBE Date: Sat, 6 Dec 2025 11:26:42 +0530 Message-ID: <20251206055648.1908734-4-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAyMCBTYWx0ZWRfX3/q4s0svO7Qa AlhUDbwq/CwcyIqZKzW90thKq5yjSM3lhnv/v24VCklbFDl0wT1ud7iB8HZ2wucKRB4V4aJEs18 +ClNgPuRHwNbitJg8OjUEBwo4OfttGKR6XBgzYF/bqRWSz+6RV5xjSQUmriX7PGS9g1V9Z3LQz0 rtfgYNZpKUKTjWNc5fIF0qYQSX7CzLtQW1cw/FytJ5MMiFbkc0vFP8JbgjaVAr6VGquMUQNzhcm 78tTEQygvZDIG5ztMTwvIf+dKL2Vit9jzzh5PrkePstFhPUQeE/uq5Pgn3sJzVr6EiV3wWsLU8g +RP63zYZtiuXN68IqRROarG9cJxofMXpjbS1aNO8eDrS169MU1KT2feCgRuyL9yxmvOb16VlxTr fDJzHH8/94Jx3g3/jPown0uRwyVR+Q== X-Proofpoint-GUID: eO8qQ9pLJfrJoyDDQt-6533rLv6DEJHL X-Proofpoint-ORIG-GUID: eO8qQ9pLJfrJoyDDQt-6533rLv6DEJHL X-Authority-Analysis: v=2.4 cv=O/U0fR9W c=1 sm=1 tr=0 ts=6933c605 cx=c_pps a=3Bg1Hr4SwmMryq2xdFQyZA==:117 a=3Bg1Hr4SwmMryq2xdFQyZA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=pGLkceISAAAA:8 a=rjUXpLR2p4wDE8UIozkA:9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-06_01,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 phishscore=0 suspectscore=0 adultscore=0 spamscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060020 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000763207019200 Content-Type: text/plain; charset="utf-8" Earlier since the SBE_CMD_STASH_MPIPL_CONFIG command was not handled, so skiboot used to not get any response from SBE: [ 106.350742821,3] SBE: Message timeout [chip id =3D 0], cmd =3D d7, s= ubcmd =3D 7 [ 106.352067746,3] SBE: Failed to send stash MPIPL config [chip id =3D= 0x0, rc =3D 254] Fix this by handling the command in PowerNV SBE, and sending a response so skiboot knows SBE has handled the STASH command The stashed skiboot base is later used to access the relocated MDST/MDDT tables when MPIPL is implemented. The purpose of stashing relocated base address is explained in following skiboot commit: author Vasant Hegde Fri Jul 12 16:47:5= 1 2019 +0530 committer Oliver O'Halloran Thu Aug 15 17:53:39 2019= +1000 SBE: Send OPAL relocated base address to SBE OPAL relocates itself during boot. During memory preserving IPL hostb= oot needs to access relocated OPAL base address to get MDST, MDDT tables. Hence= send relocated base address to SBE via 'stash MPIPL config' chip-op. Durin= g next IPL SBE will send stashed data to hostboot... so that hostboot can ac= cess these data. Signed-off-by: Aditya Gupta --- hw/ppc/pnv_sbe.c | 27 +++++++++++++++++++++++++++ include/hw/ppc/pnv_mpipl.h | 3 +++ 2 files changed, 30 insertions(+) diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c index d004b7d5c225..af888126e758 100644 --- a/hw/ppc/pnv_sbe.c +++ b/hw/ppc/pnv_sbe.c @@ -233,6 +233,7 @@ static void sbe_timer(void *opaque) =20 static void do_sbe_msg(PnvSBE *sbe) { + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); struct sbe_msg msg; uint16_t cmd, ctrl_flags, seq_id; int i; @@ -265,6 +266,32 @@ static void do_sbe_msg(PnvSBE *sbe) timer_del(sbe->timer); } break; + case SBE_CMD_STASH_MPIPL_CONFIG: + /* key =3D sbe->mbox[1] */ + switch (sbe->mbox[1]) { + case SBE_STASH_KEY_SKIBOOT_BASE: + pnv->mpipl_state.skiboot_base =3D sbe->mbox[2]; + qemu_log_mask(LOG_UNIMP, + "Stashing skiboot base: 0x%" HWADDR_PRIx "\n", + pnv->mpipl_state.skiboot_base); + + /* + * Set the response register. + * + * Currently setting the same sequence number in + * response as we got in the request. + */ + sbe->mbox[4] =3D sbe->mbox[0]; /* sequence number */ + pnv_sbe_set_host_doorbell(sbe, + sbe->host_doorbell | SBE_HOST_RESPONSE_WAITING); + + break; + default: + qemu_log_mask(LOG_UNIMP, + "SBE: CMD_STASH_MPIPL_CONFIG: Unimplemented key: 0x" TARGE= T_FMT_lx "\n", + sbe->mbox[1]); + } + break; default: qemu_log_mask(LOG_UNIMP, "SBE Unimplemented command: 0x%x\n", cmd); } diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h index c544984dc76d..60d6ede48209 100644 --- a/include/hw/ppc/pnv_mpipl.h +++ b/include/hw/ppc/pnv_mpipl.h @@ -8,11 +8,14 @@ #define PNV_MPIPL_H =20 #include "qemu/osdep.h" +#include "exec/hwaddr.h" =20 typedef struct MpiplPreservedState MpiplPreservedState; =20 /* Preserved state to be saved in PnvMachineState */ struct MpiplPreservedState { + /* skiboot_base will be valid only after OPAL sends relocated base to = SBE */ + hwaddr skiboot_base; bool is_next_boot_mpipl; }; =20 --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000807221019200 Content-Type: text/plain; charset="utf-8" Implement copying of memory region, as mentioned by MDST and MDDT tables. Copy the memory regions from source to destination in chunks of 32MB Note, qemu can fail preserving a particular entry due to any reason, such as: * region length mis-matching in MDST & MDDT * failed copy due to access/decode/etc memory issues HDAT doesn't specify any field in MDRT to notify host about such errors. Though HDAT section "15.3.1.3 Memory Dump Results Table (MDRT)" says: The Memory Dump Results Table is a list of the memory ranges that have been included in the dump Based on above statement, it looks like MDRT should include only those regions which are successfully captured in the dump, hence, regions which qemu fails to dump, just get skipped, and will not have a corresponding entry in MDRT Signed-off-by: Aditya Gupta --- hw/ppc/pnv_mpipl.c | 157 +++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_mpipl.h | 83 ++++++++++++++++++++ 2 files changed, 240 insertions(+) diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c index d8c9b7a428b7..a4f7113a44fd 100644 --- a/hw/ppc/pnv_mpipl.c +++ b/hw/ppc/pnv_mpipl.c @@ -5,12 +5,169 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "system/address-spaces.h" #include "system/runstate.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_mpipl.h" +#include + +#define MDST_TABLE_RELOCATED \ + (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF) +#define MDDT_TABLE_RELOCATED \ + (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF) + +/* + * Preserve the memory regions as pointed by MDST table + * + * During this, the memory region pointed by entries in MDST, are 'copied' + * as it is to the memory region pointed by corresponding entry in MDDT + * + * Notes: All reads should consider data coming from skiboot as bigendian, + * and data written should also be in big-endian + */ +static bool pnv_mpipl_preserve_mem(PnvMachineState *pnv) +{ + g_autofree MdstTableEntry *mdst =3D g_malloc(MDST_TABLE_SIZE); + g_autofree MddtTableEntry *mddt =3D g_malloc(MDDT_TABLE_SIZE); + g_autofree MdrtTableEntry *mdrt =3D g_malloc0(MDRT_TABLE_SIZE); + AddressSpace *default_as =3D &address_space_memory; + MemTxResult io_result; + MemTxAttrs attrs; + uint64_t src_addr, dest_addr; + uint32_t src_len; + uint64_t num_chunks; + int mdrt_idx =3D 0; + + /* Mark the memory transactions as privileged memory access */ + attrs.user =3D 0; + attrs.memory =3D 1; + + if (pnv->mpipl_state.mdrt_table) { + /* + * MDRT table allocated from some past crash, free the memory to + * prevent memory leak + */ + g_free(pnv->mpipl_state.mdrt_table); + pnv->mpipl_state.num_mdrt_entries =3D 0; + } + + io_result =3D address_space_read(default_as, MDST_TABLE_RELOCATED, att= rs, + mdst, MDST_TABLE_SIZE); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Failed to read MDST table at: 0x%lx\n", + MDST_TABLE_RELOCATED); + + return false; + } + + io_result =3D address_space_read(default_as, MDDT_TABLE_RELOCATED, att= rs, + mddt, MDDT_TABLE_SIZE); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Failed to read MDDT table at: 0x%lx\n", + MDDT_TABLE_RELOCATED); + + return false; + } + + /* Try to read all entries */ + for (int i =3D 0; i < MDST_MAX_ENTRIES; ++i) { + g_autofree uint8_t *copy_buffer =3D NULL; + bool is_copy_failed =3D false; + + /* Considering entry with address and size as 0, as end of table */ + if ((mdst[i].addr =3D=3D 0) && (mdst[i].size =3D=3D 0)) { + break; + } + + if (mdst[i].size !=3D mddt[i].size) { + qemu_log_mask(LOG_TRACE, + "Warning: Invalid entry, size mismatch in MDST & MDDT\= n"); + continue; + } + + if (mdst[i].data_region !=3D mddt[i].data_region) { + qemu_log_mask(LOG_TRACE, + "Warning: Invalid entry, region mismatch in MDST & MDD= T\n"); + continue; + } + + src_addr =3D be64_to_cpu(mdst[i].addr) & ~HRMOR_BIT; + dest_addr =3D be64_to_cpu(mddt[i].addr) & ~HRMOR_BIT; + src_len =3D be32_to_cpu(mddt[i].size); + +#define COPY_CHUNK_SIZE ((size_t)(32 * MiB)) + is_copy_failed =3D false; + copy_buffer =3D g_try_malloc(COPY_CHUNK_SIZE); + if (copy_buffer =3D=3D NULL) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Failed allocating memory (size: %zu) for copying" + " reserved memory regions\n", COPY_CHUNK_SIZE); + } + + num_chunks =3D ceil((src_len * 1.0f) / COPY_CHUNK_SIZE); + for (uint64_t chunk_id =3D 0; chunk_id < num_chunks; ++chunk_id) { + /* Take minimum of bytes left to copy, and chunk size */ + uint64_t copy_len =3D MIN( + src_len - (chunk_id * COPY_CHUNK_SIZE), + COPY_CHUNK_SIZE + ); + + /* Copy the source region to destination */ + io_result =3D address_space_read(default_as, src_addr, attrs, + copy_buffer, copy_len); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Failed to read region at: 0x%lx\n", src_addr); + is_copy_failed =3D true; + break; + } + + io_result =3D address_space_write(default_as, dest_addr, attrs, + copy_buffer, copy_len); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Failed to write region at: 0x%lx\n", dest_addr= ); + is_copy_failed =3D true; + break; + } + + src_addr +=3D COPY_CHUNK_SIZE; + dest_addr +=3D COPY_CHUNK_SIZE; + } +#undef COPY_CHUNK_SIZE + + if (is_copy_failed) { + /* + * HDAT doesn't specify an error code in MDRT for failed copy, + * and doesn't specify how this is to be handled + * Hence just skip adding an entry in MDRT, as done for size + * mismatch or other inconsistency between MDST/MDDT + */ + continue; + } + + /* Populate entry in MDRT table if preserving successful */ + mdrt[mdrt_idx].src_addr =3D cpu_to_be64(src_addr); + mdrt[mdrt_idx].dest_addr =3D cpu_to_be64(dest_addr); + mdrt[mdrt_idx].size =3D cpu_to_be32(src_len); + mdrt[mdrt_idx].data_region =3D mdst[i].data_region; + ++mdrt_idx; + } + + pnv->mpipl_state.mdrt_table =3D g_steal_pointer(&mdrt); + pnv->mpipl_state.num_mdrt_entries =3D mdrt_idx; + + return true; +} =20 void do_mpipl_preserve(PnvMachineState *pnv) { + pnv_mpipl_preserve_mem(pnv); + /* Mark next boot as Memory-preserving boot */ pnv->mpipl_state.is_next_boot_mpipl =3D true; =20 diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h index 60d6ede48209..ec173ba8268e 100644 --- a/include/hw/ppc/pnv_mpipl.h +++ b/include/hw/ppc/pnv_mpipl.h @@ -10,13 +10,96 @@ #include "qemu/osdep.h" #include "exec/hwaddr.h" =20 +#include + +typedef struct MdstTableEntry MdstTableEntry; +typedef struct MdrtTableEntry MdrtTableEntry; typedef struct MpiplPreservedState MpiplPreservedState; =20 +/* Following offsets are copied from skiboot source code */ +/* Use 768 bytes for SPIRAH */ +#define SPIRAH_OFF 0x00010000 +#define SPIRAH_SIZE 0x300 + +/* Use 256 bytes for processor dump area */ +#define PROC_DUMP_AREA_OFF (SPIRAH_OFF + SPIRAH_SIZE) +#define PROC_DUMP_AREA_SIZE 0x100 + +#define PROCIN_OFF (PROC_DUMP_AREA_OFF + PROC_DUMP_AREA_SIZE) +#define PROCIN_SIZE 0x800 + +/* Offsets of MDST and MDDT tables from skiboot base */ +#define MDST_TABLE_OFF (PROCIN_OFF + PROCIN_SIZE) +#define MDST_TABLE_SIZE 0x400 + +#define MDDT_TABLE_OFF (MDST_TABLE_OFF + MDST_TABLE_SIZE) +#define MDDT_TABLE_SIZE 0x400 +/* + * Offset of the dump result table MDRT. Hostboot will write to this + * memory after moving memory content from source to destination memory. + */ +#define MDRT_TABLE_OFF 0x01c00000 +#define MDRT_TABLE_SIZE 0x00008000 + +/* HRMOR_BIT copied from skiboot */ +#define HRMOR_BIT (1ul << 63) + +#define __packed __attribute__((packed)) + +/* + * Memory Dump Source Table (MDST) + * + * Format of this table is same as Memory Dump Source Table defined in HDAT + */ +struct MdstTableEntry { + uint64_t addr; + uint8_t data_region; + uint8_t dump_type; + uint16_t reserved; + uint32_t size; +} __packed; + +/* Memory dump destination table (MDDT) has same structure as MDST */ +typedef MdstTableEntry MddtTableEntry; + +/* + * Memory dump result table (MDRT) + * + * List of the memory ranges that have been included in the dump. This tab= le is + * filled by hostboot and passed to OPAL on second boot. OPAL/payload will= use + * this table to extract the dump. + * + * Note: This structure differs from HDAT, but matches the structure + * skiboot uses + */ +struct MdrtTableEntry { + uint64_t src_addr; + uint64_t dest_addr; + uint8_t data_region; + uint8_t dump_type; /* unused */ + uint16_t reserved; /* unused */ + uint32_t size; + uint64_t padding; /* unused */ +} __packed; + +/* Maximum length of mdst/mddt/mdrt tables */ +#define MDST_MAX_ENTRIES (MDST_TABLE_SIZE / sizeof(MdstTableEntry)) +#define MDDT_MAX_ENTRIES (MDDT_TABLE_SIZE / sizeof(MddtTableEntry)) +#define MDRT_MAX_ENTRIES (MDRT_TABLE_SIZE / sizeof(MdrtTableEntry)) + +static_assert(MDST_MAX_ENTRIES =3D=3D MDDT_MAX_ENTRIES, + "Maximum entries in MDDT must match MDST"); +static_assert(MDRT_MAX_ENTRIES >=3D MDST_MAX_ENTRIES, + "MDRT should support atleast having number of entries as in MDST"); + /* Preserved state to be saved in PnvMachineState */ struct MpiplPreservedState { /* skiboot_base will be valid only after OPAL sends relocated base to = SBE */ hwaddr skiboot_base; bool is_next_boot_mpipl; + + MdrtTableEntry *mdrt_table; + uint32_t num_mdrt_entries; }; =20 #endif --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1765000765; cv=none; d=zohomail.com; s=zohoarc; b=VqzOTZkFiixb/Tw4kjGN82e9eFtqqlTvbTndhTGzeYXuWM36e5JU6c7eRfsu6YN5fsHQ4hOd5yHnfoTo/2bwt42rBSWNY9033K4iESweXrEYRiRX6aNgGYoJQmKn/tbJRrZzRkHrpV5WyR8ZdKJzqvP+vWSHND7Q09p5+SxZdY0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765000765; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000766921019200 Content-Type: text/plain; charset="utf-8" Kernel expects the platform to provide CPU registers after pausing execution of the CPUs. Currently only exporting the registers, used by Linux, for generating the /proc/vmcore Signed-off-by: Aditya Gupta --- hw/ppc/pnv_mpipl.c | 102 +++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv_mpipl.h | 62 ++++++++++++++++++++++ 2 files changed, 164 insertions(+) diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c index a4f7113a44fd..8b41938c2e87 100644 --- a/hw/ppc/pnv_mpipl.c +++ b/hw/ppc/pnv_mpipl.c @@ -8,6 +8,8 @@ #include "qemu/log.h" #include "qemu/units.h" #include "system/address-spaces.h" +#include "system/cpus.h" +#include "system/hw_accel.h" #include "system/runstate.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_mpipl.h" @@ -17,6 +19,8 @@ (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF) #define MDDT_TABLE_RELOCATED \ (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF) +#define PROC_DUMP_RELOCATED \ + (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF) =20 /* * Preserve the memory regions as pointed by MDST table @@ -164,9 +168,107 @@ static bool pnv_mpipl_preserve_mem(PnvMachineState *p= nv) return true; } =20 +static void do_store_cpu_regs(CPUState *cpu, MpiplPreservedCPUState *state) +{ + CPUPPCState *env =3D cpu_env(cpu); + MpiplRegDataHdr *regs_hdr =3D &state->hdr; + MpiplRegEntry *reg_entries =3D state->reg_entries; + MpiplRegEntry *curr_reg_entry; + uint32_t num_saved_regs =3D 0; + + cpu_synchronize_state(cpu); + + regs_hdr->pir =3D cpu_to_be32(env->spr[SPR_PIR]); + + /* QEMU CPUs are not in Power Saving Mode */ + regs_hdr->core_state =3D 0xff; + + regs_hdr->off_regentries =3D 0; + regs_hdr->num_regentries =3D cpu_to_be32(NUM_REGS_PER_CPU); + + regs_hdr->alloc_size =3D cpu_to_be32(sizeof(MpiplRegEntry)); + regs_hdr->act_size =3D cpu_to_be32(sizeof(MpiplRegEntry)); + +#define REG_TYPE_GPR 0x1 +#define REG_TYPE_SPR 0x2 +#define REG_TYPE_TIMA 0x3 + +/* + * ID numbers used by f/w while populating certain registers + * + * Copied these defines from the linux kernel + */ +#define REG_ID_NIP 0x7D0 +#define REG_ID_MSR 0x7D1 +#define REG_ID_CCR 0x7D2 + + curr_reg_entry =3D reg_entries; + +#define REG_ENTRY(type, num, val) \ + do { \ + curr_reg_entry->reg_type =3D cpu_to_be32(type); \ + curr_reg_entry->reg_num =3D cpu_to_be32(num); \ + curr_reg_entry->reg_val =3D cpu_to_be64(val); \ + ++curr_reg_entry; \ + ++num_saved_regs; \ + } while (0) + + /* Save the GPRs */ + for (int gpr_id =3D 0; gpr_id < 32; ++gpr_id) { + REG_ENTRY(REG_TYPE_GPR, gpr_id, env->gpr[gpr_id]); + } + + REG_ENTRY(REG_TYPE_SPR, REG_ID_NIP, env->nip); + REG_ENTRY(REG_TYPE_SPR, REG_ID_MSR, env->msr); + + /* + * Ensure the number of registers saved match the number of + * registers per cpu + * + * This will help catch an error if in future a new register entry + * is added/removed while not modifying NUM_PER_CPU_REGS + */ + assert(num_saved_regs =3D=3D NUM_REGS_PER_CPU); +} + +static void pnv_mpipl_preserve_cpu_state(PnvMachineState *pnv) +{ + MachineState *machine =3D MACHINE(pnv); + uint32_t num_cpus =3D machine->smp.cpus; + MpiplPreservedCPUState *state; + CPUState *cpu; + + if (pnv->mpipl_state.cpu_states) { + /* + * CPU States might have been allocated from some past crash, free= the + * memory to preven memory leak + */ + g_free(pnv->mpipl_state.cpu_states); + pnv->mpipl_state.num_cpu_states =3D 0; + } + + pnv->mpipl_state.cpu_states =3D g_malloc_n(num_cpus, + sizeof(MpiplPreservedCPUState)); + pnv->mpipl_state.num_cpu_states =3D num_cpus; + + state =3D pnv->mpipl_state.cpu_states; + + /* Preserve the Processor Dump Area */ + cpu_physical_memory_read(PROC_DUMP_RELOCATED, &pnv->mpipl_state.proc_a= rea, + sizeof(MpiplProcDumpArea)); + + CPU_FOREACH(cpu) { + do_store_cpu_regs(cpu, state); + ++state; + } +} + void do_mpipl_preserve(PnvMachineState *pnv) { + pause_all_vcpus(); + pnv_mpipl_preserve_mem(pnv); + pnv_mpipl_preserve_cpu_state(pnv); =20 /* Mark next boot as Memory-preserving boot */ pnv->mpipl_state.is_next_boot_mpipl =3D true; diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h index ec173ba8268e..d85970bba039 100644 --- a/include/hw/ppc/pnv_mpipl.h +++ b/include/hw/ppc/pnv_mpipl.h @@ -16,6 +16,12 @@ typedef struct MdstTableEntry MdstTableEntry; typedef struct MdrtTableEntry MdrtTableEntry; typedef struct MpiplPreservedState MpiplPreservedState; =20 +typedef struct MpiplRegDataHdr MpiplRegDataHdr; +typedef struct MpiplRegEntry MpiplRegEntry; +typedef struct MpiplProcDumpArea MpiplProcDumpArea; +typedef struct MpiplPreservedState MpiplPreservedState; +typedef struct MpiplPreservedCPUState MpiplPreservedCPUState; + /* Following offsets are copied from skiboot source code */ /* Use 768 bytes for SPIRAH */ #define SPIRAH_OFF 0x00010000 @@ -46,6 +52,8 @@ typedef struct MpiplPreservedState MpiplPreservedState; =20 #define __packed __attribute__((packed)) =20 +#define NUM_REGS_PER_CPU 34 /*(32 GPRs, NIP, MSR)*/ + /* * Memory Dump Source Table (MDST) * @@ -92,6 +100,55 @@ static_assert(MDST_MAX_ENTRIES =3D=3D MDDT_MAX_ENTRIES, static_assert(MDRT_MAX_ENTRIES >=3D MDST_MAX_ENTRIES, "MDRT should support atleast having number of entries as in MDST"); =20 +/* + * Processor Dump Area + * + * This contains the information needed for having processor + * state captured during a platform dump. + * + * As mentioned in HDAT, following the P9 specific format + */ +struct MpiplProcDumpArea { + uint32_t thread_size; /* Size of each thread register entry */ +#define PROC_DUMP_AREA_VERSION_P9 0x1 /* P9 format */ + uint8_t version; + uint8_t reserved[11]; + uint64_t alloc_addr; /* Destination memory to place register data = */ + uint32_t reserved2; + uint32_t alloc_size; /* Allocated size */ + uint64_t dest_addr; /* Destination address */ + uint32_t reserved3; + uint32_t act_size; /* Actual data size */ +} __packed; + +/* + * "Architected Register Data" in the HDAT spec + * + * Acts as a header to the register entries for a particular thread + */ +struct MpiplRegDataHdr { + uint32_t pir; /* PIR of thread */ + uint8_t core_state; /* Stop state of the overall core */ + uint8_t reserved[3]; + uint32_t off_regentries; /* Offset to Register Entries Array */ + uint32_t num_regentries; /* Number of Register Entries in Array */ + uint32_t alloc_size; /* Allocated size for each Register Entry */ + uint32_t act_size; /* Actual size for each Register Entry */ +} __packed; + +struct MpiplRegEntry { + uint32_t reg_type; + uint32_t reg_num; + uint64_t reg_val; +} __packed; + +struct MpiplPreservedCPUState { + MpiplRegDataHdr hdr; + + /* Length of 'reg_entries' is hdr.num_regentries */ + MpiplRegEntry reg_entries[NUM_REGS_PER_CPU]; +}; + /* Preserved state to be saved in PnvMachineState */ struct MpiplPreservedState { /* skiboot_base will be valid only after OPAL sends relocated base to = SBE */ @@ -100,6 +157,11 @@ struct MpiplPreservedState { =20 MdrtTableEntry *mdrt_table; uint32_t num_mdrt_entries; + + MpiplProcDumpArea proc_area; + + MpiplPreservedCPUState *cpu_states; + uint32_t num_cpu_states; }; =20 #endif --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1765000793; cv=none; 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Sat, 6 Dec 2025 05:58:29 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=wLctdVdz23RHi6EBM uEsjZPOv8PROCGZwAcs6GsBiBo=; b=mKH4fFSalPD38/9byyedRWhLRBVjCv178 n49sV+8q52a4sr3os87ijBAQPKAEVtBfxtMoeW24bo3/P8BnZNW7uhr47A27eZy/ e+jMEW5Z4qEDVyOIeJEqRFq0TvWMniL9dLni0RbFu5OWyrbUMhMYf8Tt+yb7YUeq NJKI5CnftjzvXXFrhiQDdEM8XnjmoPd7Q8EkUxHtOOoWBsp5KGWIBeb9oWUE95Cb rZ8HJ73EtCEpmiRg6BQBCvo9u//mffQ/lsIU5uZmeh9SKPYzj8HPvZnCpaC2D8wS ysMOTIVbkUPSV/gxPlqKR4pJxSx51GhivHXJ31zrCV4fU3qqG9/Hg== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 6/9] pnv/mpipl: Set thread entry size to be allocated by firmware Date: Sat, 6 Dec 2025 11:26:45 +0530 Message-ID: <20251206055648.1908734-7-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: CLoV9n_qqLOzfu_IE6BxJJz5uglsFKyr X-Proofpoint-ORIG-GUID: CLoV9n_qqLOzfu_IE6BxJJz5uglsFKyr X-Authority-Analysis: v=2.4 cv=AdS83nXG c=1 sm=1 tr=0 ts=6933c60c cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=x2nWBmqi6rLqIJY0GGYA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAwMCBTYWx0ZWRfX6lNZa20VrzXu xmoysbwgM0QU59qi0XzSgtZC+P3LxIgqKtqNzGh0tnE3i3wATuQmkHZXdz8T1O6/lllYMRD2RQW Sx5CmQoypVsv3JnKHt9KCSqLMbRIQ8PrvLngZAX8lbZrZXQyxT0DzOSfngtGDr7WPXTUbWtGcOG 5+hOK5mzBesaT7jJxbLYZOu9u0gtykeq3n1s7yY+x6mzTEKSSTKtmHP2ggHweCmq/C2vZzl1ZVQ PPNb5DHTxpBk+Gvw6FajolMc5tqcg2gt4nhqZTi0xKOeHSau1PsGpATYCfzjVbDqS/9zphkhvFS MAMppQnfOM7muGRbx3HPmDSdsLxzJINezY4Wjixj2MLvEwU9+Hu+FuSkLxkS01dl6PdBFhVJtod 3RfOPpR0SoudxUhkpetcSmx0jvc3lA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-06_01,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060000 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000794972019200 Content-Type: text/plain; charset="utf-8" Set the "Thread Register State Entry Size" that is required by firmware (OPAL), to know size of memory to allocate to capture CPU state, in the event of a crash Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 895132da91bd..643558f374e9 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -780,6 +780,30 @@ static void pnv_reset(MachineState *machine, ResetType= type) _FDT((fdt_pack(fdt))); } =20 + if (!pnv->mpipl_state.is_next_boot_mpipl) { + /* + * Set the "Thread Register State Entry Size", so that firmware can + * allocate enough memory to capture CPU state in the event of a + * crash + */ + + MpiplProcDumpArea proc_area; + + proc_area.version =3D PROC_DUMP_AREA_VERSION_P9; + proc_area.thread_size =3D cpu_to_be32(sizeof(MpiplPreservedCPUStat= e)); + + /* These are to be allocated & assigned by the firmware */ + proc_area.alloc_addr =3D 0; + proc_area.alloc_size =3D 0; + + /* These get assigned after crash, when QEMU preserves the registe= rs */ + proc_area.dest_addr =3D 0; + proc_area.act_size =3D 0; + + cpu_physical_memory_write(PROC_DUMP_AREA_OFF, &proc_area, + sizeof(proc_area)); + } + cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); =20 /* Update machine->fdt with latest fdt */ --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 6 Dec 2025 05:58:32 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=9v9iWDgBCYpeHMTsm +20QdFqUeyuim+UMCMe+GTkr2c=; b=Q/R3IHacWyKr2yBqHEesKAO53ISZtwc/0 clL/1KuDCKLMHqK1NlnZ8lM1mlK7MzhatCA64yuXngtNH099vRb/odVbOtZY8gRN hhe6Q4QgfcadB0aVDi6pRqFvKZ/Tz41mqNLqiF9EIjAG1nXlHDMoOKBiQLD22A+p z41uhNioVhgsukxDbtkWKzmG6ZFzeAJGOh6semAosaXOBLG5+pMIUZHJIaUhvdYd CuleimTH6Am+7VdNTicRmLPQKr91ufArvuhsfJuYCDk30NeHtUgz2FGe/VcZ2IVz 9YuMRSAiS4VjZ0p+yFYTp4IQhlZv3fWaNX/tSnKcXq5Wq+u5EIzkg== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 7/9] pnv/mpipl: Write the preserved CPU and MDRT state Date: Sat, 6 Dec 2025 11:26:46 +0530 Message-ID: <20251206055648.1908734-8-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Authority-Analysis: v=2.4 cv=Cf8FJbrl c=1 sm=1 tr=0 ts=6933c60f cx=c_pps a=aDMHemPKRhS1OARIsFnwRA==:117 a=aDMHemPKRhS1OARIsFnwRA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=9s9mwq7jZm2NEmiXaqsA:9 X-Proofpoint-ORIG-GUID: YIoDKON1DRc_NeoFEgNesiujKMh9xS1p X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAxNiBTYWx0ZWRfX6fxOOeltcReR cldKTfDD8JIvHK6kFoirP5DQBTCYRVK5A5IgFAdsLrAI4NgN3ASd9DwyGo8cHA8+XpbOY83QpIJ EIVpR2zEpybLiLkrgmb8nMUIx2v2hp7YA/Ju6jrdF/yM9EFqBYZ9yVyTqlFn37AcFUIFNwQKdHl qRfiNAOfHWObVrDO42UeBN0CxLjMVnsU/ZUNZrdqiDTgBor6hA+n3+rNk7iTCCVZZH1fMsRfPpP GDCFLMM7sQJNh/ltUfAt2naDWjK08gdfsM/Syr/HwLVztSLxs8DSnBK2b2nkRsgLyH79mSWcSdc OMzIaxCFxGx8Adro+/XY45esxUOkpJalQp+S3IWJCZDEMVAzt6UJGYljbrI7SL98Bg8TGm+mTzD /FIjSR8aA/L1GvnIUsZ0Mo01Y2s9sA== X-Proofpoint-GUID: YIoDKON1DRc_NeoFEgNesiujKMh9xS1p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-05_09,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060016 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=adityag@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000809297019200 Content-Type: text/plain; charset="utf-8" Logic for preserving the CPU registers and memory regions has been done in previous patches. Write those data at the relevant memory address, such as PROC_DUMP_AREA for CPU registers, and MDRT for preserved memory regions. Also export "mpipl-boot" device tree node, for kernel to know that it's a 'dump active' boot Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 31 ++++++++++++- hw/ppc/pnv_mpipl.c | 103 +++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/pnv.h | 1 + 3 files changed, 134 insertions(+), 1 deletion(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 643558f374e9..7c36f3a00e90 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -750,6 +750,7 @@ static void pnv_reset(MachineState *machine, ResetType = type) PnvMachineState *pnv =3D PNV_MACHINE(machine); IPMIBmc *bmc; void *fdt; + int node_offset; =20 qemu_devices_reset(type); =20 @@ -780,7 +781,35 @@ static void pnv_reset(MachineState *machine, ResetType= type) _FDT((fdt_pack(fdt))); } =20 - if (!pnv->mpipl_state.is_next_boot_mpipl) { + /* + * If it's a MPIPL boot, add the "mpipl-boot" property, and reset the + * boolean for MPIPL boot for next boot + */ + if (pnv->mpipl_state.is_next_boot_mpipl) { + void *fdt_copy =3D g_malloc0(FDT_MAX_SIZE); + + /* Write the preserved MDRT and CPU State Data */ + do_mpipl_write(pnv); + + /* Create a writable copy of the fdt */ + _FDT((fdt_open_into(fdt, fdt_copy, FDT_MAX_SIZE))); + + node_offset =3D fdt_path_offset(fdt_copy, "/ibm,opal/dump"); + _FDT((fdt_appendprop_u64(fdt_copy, node_offset, "mpipl-boot", 1))); + + /* Update the fdt, and free the original fdt */ + if (fdt !=3D machine->fdt) { + /* + * Only free the fdt if it's not machine->fdt, to prevent + * double free, since we already free machine->fdt later + */ + g_free(fdt); + } + fdt =3D fdt_copy; + + /* This boot is an MPIPL, reset the boolean for next boot */ + pnv->mpipl_state.is_next_boot_mpipl =3D false; + } else { /* * Set the "Thread Register State Entry Size", so that firmware can * allocate enough memory to capture CPU state in the event of a diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c index 8b41938c2e87..3c9755a6c440 100644 --- a/hw/ppc/pnv_mpipl.c +++ b/hw/ppc/pnv_mpipl.c @@ -19,6 +19,8 @@ (pnv->mpipl_state.skiboot_base + MDST_TABLE_OFF) #define MDDT_TABLE_RELOCATED \ (pnv->mpipl_state.skiboot_base + MDDT_TABLE_OFF) +#define MDRT_TABLE_RELOCATED \ + (pnv->mpipl_state.skiboot_base + MDRT_TABLE_OFF) #define PROC_DUMP_RELOCATED \ (pnv->mpipl_state.skiboot_base + PROC_DUMP_AREA_OFF) =20 @@ -263,6 +265,100 @@ static void pnv_mpipl_preserve_cpu_state(PnvMachineSt= ate *pnv) } } =20 +static void pnv_mpipl_write_cpu_state(PnvMachineState *pnv) +{ + MpiplProcDumpArea *proc_area =3D &pnv->mpipl_state.proc_area; + MpiplPreservedCPUState *cpu_state =3D pnv->mpipl_state.cpu_states; + const uint32_t num_cpu_states =3D pnv->mpipl_state.num_cpu_states; + hwaddr next_regentries_hdr; + + if (be32_to_cpu(proc_area->alloc_size) < + (num_cpu_states * sizeof(MpiplPreservedCPUState))) { + qemu_log_mask(LOG_GUEST_ERROR, + "MPIPL: Size of buffer allocate by skiboot (%u bytes) is not" + "enough to save all CPUs registers needed (%ld bytes)", + be32_to_cpu(proc_area->alloc_size), + num_cpu_states * sizeof(MpiplPreservedCPUState)); + + return; + } + + proc_area->version =3D PROC_DUMP_AREA_VERSION_P9; + + /* + * This is the stride kernel/firmware should use to jump from a + * register entries header to next CPU's header + */ + proc_area->thread_size =3D cpu_to_be32(sizeof(MpiplPreservedCPUState)); + + /* Write the header and register entries for each CPU */ + next_regentries_hdr =3D be64_to_cpu(proc_area->alloc_addr) & (~HRMOR_B= IT); + for (int i =3D 0; i < num_cpu_states; ++i) { + cpu_physical_memory_write(next_regentries_hdr, &cpu_state->hdr, + sizeof(MpiplRegDataHdr)); + + cpu_physical_memory_write(next_regentries_hdr + sizeof(MpiplRegDat= aHdr), + &cpu_state->reg_entries, + NUM_REGS_PER_CPU * sizeof(MpiplRegEntry)); + + /* + * According to HDAT section: "15.3.1.5 Architected Register Data = content": + * + * The next register entries header will be at current header + + * "Thread Register State Entry size" + * + * Note: proc_area.thread_size =3D=3D sizeof(MpiplPreservedCPUStat= e) + */ + next_regentries_hdr +=3D sizeof(MpiplPreservedCPUState); + ++cpu_state; + } + + /* Point the destination address to the preserved memory region */ + proc_area->dest_addr =3D proc_area->alloc_addr; + proc_area->act_size =3D cpu_to_be32(num_cpu_states * + sizeof(MpiplPreservedCPUState)); + + cpu_physical_memory_write(PROC_DUMP_AREA_OFF, proc_area, + sizeof(MpiplProcDumpArea)); +} + +static void pnv_mpipl_write_mdrt(PnvMachineState *pnv) +{ + MpiplPreservedState *state =3D &pnv->mpipl_state; + AddressSpace *default_as =3D &address_space_memory; + MemTxResult io_result; + MemTxAttrs attrs; + + /* Mark the memory transactions as privileged memory access */ + attrs.user =3D 0; + attrs.memory =3D 1; + + /* + * Generally writes from platform during MPIPL don't go to a relocated + * skiboot address + * + * Though for MDRT we are doing so, as this is the address skiboot + * considers by default for MDRT + * + * MDRT/MDST/MDDT base addresses are actually meant to be shared by + * platform in SPIRA structures. + * + * Not implementing SPIRA as it increases complexity for no gains. + * Using the default address skiboot expects for MDRT, which is the + * relocated MDRT, hence writing to it + * + * Other tables like MDST/MDDT should not be written to relocated + * addresses, as skiboot will overwrite anything from SKIBOOT_BASE till + * SKIBOOT_BASE+SKIBOOT_SIZE (which is 0x30000000-0x31c00000 by defaul= t) + */ + io_result =3D address_space_write(default_as, MDRT_TABLE_RELOCATED, at= trs, + state->mdrt_table, + state->num_mdrt_entries * sizeof(MdrtTableEntry)); + if (io_result !=3D MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "MPIPL: Failed to write MDRT table\= n"); + } +} + void do_mpipl_preserve(PnvMachineState *pnv) { pause_all_vcpus(); @@ -283,3 +379,10 @@ void do_mpipl_preserve(PnvMachineState *pnv) */ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } + +void do_mpipl_write(PnvMachineState *pnv) +{ + pnv_mpipl_write_mdrt(pnv); + pnv_mpipl_write_cpu_state(pnv); +} + diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 02baa0012460..a71e968c32e0 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -295,5 +295,6 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor); =20 /* MPIPL helpers */ void do_mpipl_preserve(PnvMachineState *pnv); +void do_mpipl_write(PnvMachineState *pnv); =20 #endif /* PPC_PNV_H */ --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Sat, 6 Dec 2025 05:58:35 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=pp1; bh=VueZTIY2Ugd2O6URX Xd0/Ttdg8i3mKIQCFXlU+Qcp7o=; b=SwN51I5OhEnP4wI4weu5Qatx37rY4BD4H t79r1USju2BSe1B/PCWJNDoFOOeMPZfuoPHbZ+S/KFifWA483abRlmBFz9cDQ3g0 T7yNjhC0QALToAsv2iB6geksjMnJuTXr1OOcNe+KabXm8RWeWL+Hvv3Q/WWiwlzl Hmk+YOnCN2HHKGkrIkNjcIIzRrdp75ffvo0NM9Tsd96cHwAscCMf9xRjVoryAR9V m5V7ApaWpWt4yJA/Rmr8S9uI+xy317ypi4qAf39MJJy0h92gDptSNb+nwjAzLDgl /I2EHfHDJbPuGDEmdOnU6bzBf8gjQiavvJedyn+L68EUmRS/jIRDg== From: Aditya Gupta To: Cc: , Hari Bathini , Sourabh Jain , Harsh Prateek Bora Subject: [PATCH v2 8/9] pnv/mpipl: Enable MPIPL support Date: Sat, 6 Dec 2025 11:26:47 +0530 Message-ID: <20251206055648.1908734-9-adityag@linux.ibm.com> X-Mailer: git-send-email 2.52.0 In-Reply-To: <20251206055648.1908734-1-adityag@linux.ibm.com> References: <20251206055648.1908734-1-adityag@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: fS367mCaadfYQEJ24MXdMU1qVTeK7CCK X-Proofpoint-ORIG-GUID: fS367mCaadfYQEJ24MXdMU1qVTeK7CCK X-Authority-Analysis: v=2.4 cv=AdS83nXG c=1 sm=1 tr=0 ts=6933c612 cx=c_pps a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17 a=wP3pNCr1ah4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=VnNF1IyMAAAA:8 a=dCvegdiEg4V6ml2xVIcA:9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjA2MDAwMCBTYWx0ZWRfX8XfLabzYTbf3 ZwlKkYdLpT9OpDkAzwM9cCyb04ermOBeY4kH9oidyz6x3tsfA7IBTnQUPLFSERTXS2Ncq6fiycP TNRK3DUM5dwq+0uX/JCvwUIWmR4gyM7wBiLnZTbYQ51Ch7tgrFOgRgTcewxMxVl+je/SLvyqN0W jQiEjUhJv3hd8jhnVZQIJoot9+rA/YfDFw+GsuqlNDaiir77nZrwy0vznGqA/wQd3CGOeVqPqpz Fw93/8WteXIznFSFK72nlqKqz81yBFLAwl+ESlutzbLU66g8tCRTvEH0h/24ipYvSYs5XlJSuxd WqbZ7gUK+5sHYwxEl3n0xrJ3h4853JlEAWX8lw4Albk4Xedfh427+JZXY8kl6VfPYDd0ThUY+K0 2Orbj2YYISpsylK0f3iNxhC1qUQncg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-06_01,2025-12-04_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 spamscore=0 phishscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510240000 definitions=main-2512060000 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000794995019200 Content-Type: text/plain; charset="utf-8" With all MPIPL support in place, export a "dump" node in device tree, signifying that PowerNV QEMU platform supports MPIPL Signed-off-by: Aditya Gupta --- hw/ppc/pnv.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 7c36f3a00e90..8a62b0ee1074 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -54,6 +54,7 @@ #include "hw/ppc/pnv_chip.h" #include "hw/ppc/pnv_xscom.h" #include "hw/ppc/pnv_pnor.h" +#include "hw/ppc/pnv_mpipl.h" =20 #include "hw/isa/isa.h" #include "hw/char/serial-isa.h" @@ -671,6 +672,39 @@ static void pnv_dt_power_mgt(PnvMachineState *pnv, voi= d *fdt) _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)= ); } =20 +static void pnv_dt_mpipl_dump(PnvMachineState *pnv, void *fdt) +{ + int off; + + /* + * Add "dump" node so kernel knows MPIPL (aka fadump) is supported + * + * Note: This is only needed to be done since we are passing device tr= ee to + * opal + * + * In case HDAT is supported in future, then opal can add these nodes = by + * itself based on system attribute having MPIPL_SUPPORTED bit set + */ + off =3D fdt_add_subnode(fdt, 0, "ibm,opal"); + if (off =3D=3D -FDT_ERR_EXISTS) { + off =3D fdt_path_offset(fdt, "/ibm,opal"); + } + + _FDT(off); + off =3D fdt_add_subnode(fdt, off, "dump"); + _FDT(off); + _FDT((fdt_setprop_string(fdt, off, "compatible", "ibm,opal-dump"))); + + /* Add kernel and initrd as fw-load-area */ + uint64_t fw_load_area[4] =3D { + cpu_to_be64(KERNEL_LOAD_ADDR), cpu_to_be64(KERNEL_MAX_SIZE), + cpu_to_be64(INITRD_LOAD_ADDR), cpu_to_be64(INITRD_MAX_SIZE) + }; + + _FDT((fdt_setprop(fdt, off, "fw-load-area", + fw_load_area, sizeof(fw_load_area)))); +} + static void *pnv_dt_create(MachineState *machine) { PnvMachineClass *pmc =3D PNV_MACHINE_GET_CLASS(machine); @@ -733,6 +767,9 @@ static void *pnv_dt_create(MachineState *machine) pmc->dt_power_mgt(pnv, fdt); } =20 + /* Advertise support for MPIPL */ + pnv_dt_mpipl_dump(pnv, fdt); + return fdt; } =20 --=20 2.52.0 From nobody Sun Dec 14 06:34:44 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=linux.ibm.com ARC-Seal: i=1; a=rsa-sha256; t=1765000810; cv=none; d=zohomail.com; s=zohoarc; b=McSBiUpmVig3lBKXv/m2lumIwE+YhQOSjWpOCIUNGajUQHzXj1YYRrX7XvU2OqAw28P8PshWjSAJHGTeItGLqbVkjaY4fyjmBVAk2dv0eXP+iLjPRiTkVncPllXn838Mp5OfWU2ecalF4RYz67YTROXImW30Z/meOmtqtAlYh1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1765000810; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.158.5; envelope-from=adityag@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1765000811188019200 Content-Type: text/plain; charset="utf-8" With MPIPL support implemented, enable fadump's functional test for PowerNV Also, current functional test for powernv uses op-build's Linux 5.10 image, which doesn't support adding "fadump=3Don" in argument due to this: Kernel is locked down from Kernel configuration; see man kernel_lockdow= n.7 Hence, instead of op-build's image, use the newer fedora vmlinuz as used in FADump PSeries functional test Also due to "bash#" string not showing up, rely on sh: no job control to check if testcase has reached till shell Signed-off-by: Aditya Gupta --- tests/functional/ppc64/test_fadump.py | 35 ++++++++++----------------- 1 file changed, 13 insertions(+), 22 deletions(-) diff --git a/tests/functional/ppc64/test_fadump.py b/tests/functional/ppc64= /test_fadump.py index 2d6b8017e8f0..e3238ceadfe6 100755 --- a/tests/functional/ppc64/test_fadump.py +++ b/tests/functional/ppc64/test_fadump.py @@ -14,6 +14,7 @@ class QEMUFadump(LinuxKernelTest): =20 1. test_fadump_pseries: PSeries 2. test_fadump_pseries_kvm: PSeries + KVM + 3. test_fadump_powernv: PowerNV """ =20 timeout =3D 90 @@ -24,11 +25,6 @@ class QEMUFadump(LinuxKernelTest): msg_registered_failed =3D '' msg_dump_active =3D '' =20 - ASSET_EPAPR_KERNEL =3D Asset( - ('https://github.com/open-power/op-build/releases/download/v2.7/' - 'zImage.epapr'), - '0ab237df661727e5392cee97460e8674057a883c5f74381a128fa772588d45cd') - ASSET_VMLINUZ_KERNEL =3D Asset( ('https://archives.fedoraproject.org/pub/archive/fedora-secondary/' 'releases/39/Everything/ppc64le/os/ppc/ppc64/vmlinuz'), @@ -64,16 +60,14 @@ def do_test_fadump(self, is_kvm=3DFalse, is_powernv=3DF= alse): # SLOF takes upto >20s in startup time, use VOF self.set_machine("pseries") self.vm.add_args("-machine", "x-vof=3Don") - self.vm.add_args("-m", "6G") + + self.vm.add_args("-m", "6G") =20 self.vm.set_console() =20 kernel_path =3D None =20 - if is_powernv: - kernel_path =3D self.ASSET_EPAPR_KERNEL.fetch() - else: - kernel_path =3D self.ASSET_VMLINUZ_KERNEL.fetch() + kernel_path =3D self.ASSET_VMLINUZ_KERNEL.fetch() =20 initrd_path =3D self.ASSET_FEDORA_INITRD.fetch() =20 @@ -104,16 +98,14 @@ def do_test_fadump(self, is_kvm=3DFalse, is_powernv=3D= False): timeout=3D20 ) =20 - # Ensure fadump is registered successfully, if registration - # succeeds, we get a log from rtas fadump: - # - # rtas fadump: Registration is successful! - self.wait_for_console_pattern( - "rtas fadump: Registration is successful!" - ) + # Ensure fadump is registered successfully + if not is_powernv: + self.wait_for_console_pattern( + "rtas fadump: Registration is successful!" + ) =20 # Wait for the shell - self.wait_for_console_pattern("#") + self.wait_for_console_pattern("sh: no job control") =20 # Mount /proc since not available in the initrd used exec_command(self, command=3D"mount -t proc proc /proc") @@ -137,7 +129,7 @@ def do_test_fadump(self, is_kvm=3DFalse, is_powernv=3DF= alse): # that qemu didn't pass the 'ibm,kernel-dump' device tree node wait_for_console_pattern( test=3Dself, - success_message=3D"rtas fadump: Firmware-assisted dump is acti= ve", + success_message=3D"fadump: Firmware-assisted dump is active", failure_message=3D"fadump: Reserved " ) =20 @@ -150,7 +142,7 @@ def do_test_fadump(self, is_kvm=3DFalse, is_powernv=3DF= alse): self.wait_for_console_pattern("preserving crash data") =20 # Wait for prompt - self.wait_for_console_pattern("sh-5.2#") + self.wait_for_console_pattern("Run /bin/sh as init process") =20 # Mount /proc since not available in the initrd used exec_command_and_wait_for_pattern(self, @@ -168,9 +160,8 @@ def do_test_fadump(self, is_kvm=3DFalse, is_powernv=3DF= alse): def test_fadump_pseries(self): return self.do_test_fadump(is_kvm=3DFalse, is_powernv=3DFalse) =20 - @skip("PowerNV Fadump not supported yet") def test_fadump_powernv(self): - return + return self.do_test_fadump(is_kvm=3DFalse, is_powernv=3DTrue) =20 def test_fadump_pseries_kvm(self): """ --=20 2.52.0