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Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/15] hw/timer: Make PERIPHCLK divider configurable Date: Thu, 4 Dec 2025 10:34:49 +0100 Message-ID: <20251204093502.50582-3-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841090518019201 From: YannickV The A9 global timer and ARM MP timer use PERIPHCLK as their clock source. The frequency of PERIPHCLK is derived by dividing the main clock (CLK) by a configurable divider (must be at least 2). Previously, the PERIPHCLK divider was not configurable, which could lead to unexspected behavior if the application exspected a different PERIPHCLK rate. The property periphclk-divider specifies by which value the main clock is divided to generate PERIPHCLK. This allows flexible configuration of the timer clocks to match application requirements. Information can be found in the Zynq 7000 Soc Technical Reference Manual under Timers. https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: YannickV Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/a9gtimer.c | 19 ++++++++++++++++++- hw/timer/arm_mptimer.c | 19 ++++++++++++++++++- include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index ad9abcb4bb..8b4c6d7e6a 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -27,6 +27,7 @@ #include "hw/timer/a9gtimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/log.h" @@ -62,9 +63,17 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerStat= e *s) =20 static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The a9 global timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to a9 + * gtimer ticks can be calculated like this: + */ uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, R_CONTROL_PRESCALER_LEN) + 1; - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * s->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz); } =20 @@ -312,6 +321,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error = **errp) sysbus_init_mmio(sbd, &s->iomem); s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync= , s); =20 + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >=3D 2", + s->periphclk_divider); + return; + } + for (i =3D 0; i < s->num_cpu; i++) { A9GTimerPerCPU *gtb =3D &s->per_cpu[i]; =20 @@ -378,6 +393,8 @@ static const Property a9_gtimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", A9GTimerState, + periphclk_divider, 10), }; =20 static void a9_gtimer_class_init(ObjectClass *klass, const void *data) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 342ca1276a..cf434ca2f4 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -27,6 +27,7 @@ #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -61,8 +62,16 @@ static inline void timerblock_update_irq(TimerBlock *tb) /* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The arm mp timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to arm mp + * timer ticks can be calculated like this: + */ uint64_t prescale =3D (((control >> 8) & 0xff) + 1); - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * tb->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz); } =20 @@ -273,6 +282,12 @@ static void arm_mptimer_realize(DeviceState *dev, Erro= r **errp) for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; tb->freq_hz =3D s->freq_hz; + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >= =3D 2", + s->periphclk_divider); + return; + } + tb->periphclk_divider =3D s->periphclk_divider; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, @@ -309,6 +324,8 @@ static const Property arm_mptimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", ARMMPTimerState, + periphclk_divider, 10), }; =20 static void arm_mptimer_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 3b63d14927..ff9baf1c77 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -77,6 +77,7 @@ struct A9GTimerState { MemoryRegion iomem; /* static props */ uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; =20 QEMUTimer *timer; diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index da43a3d351..061934e4b5 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -32,6 +32,7 @@ typedef struct { uint32_t status; struct ptimer_state *timer; uint64_t freq_hz; + uint64_t periphclk_divider; qemu_irq irq; MemoryRegion iomem; } TimerBlock; @@ -45,6 +46,7 @@ struct ARMMPTimerState { /*< public >*/ =20 uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; --=20 2.47.3