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Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 13/15] hw/arm/xilinx_zynq: Add flash-type property Date: Thu, 4 Dec 2025 10:35:00 +0100 Message-ID: <20251204093502.50582-14-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840987772019200 Content-Type: text/plain; charset="utf-8" From: YannickV Read flash-type value as machine property and set the flash type accordingly. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 25 ++++++++++++++++++++----- include/hw/arm/xilinx_zynq.h | 1 + 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 4d095ab6f3..db4fac17c8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -120,7 +120,8 @@ static void gem_init(uint32_t base, qemu_irq irq) } =20 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi, int unit0) + bool is_qspi, int unit0, + const char *flash_type) { int unit =3D unit0; DeviceState *dev; @@ -152,7 +153,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_a= ddr, qemu_irq irq, =20 for (j =3D 0; j < num_ss; ++j) { DriveInfo *dinfo =3D drive_get(IF_MTD, 0, unit++); - flash_dev =3D qdev_new("n25q128"); + flash_dev =3D qdev_new(flash_type); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -190,6 +191,14 @@ static void zynq_set_boot_mode(Object *obj, const char= *str, m->boot_mode =3D mode; } =20 +static void zynq_set_flash_type(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m =3D ZYNQ_MACHINE(obj); + g_free(m->flash_type); + m->flash_type =3D g_strdup(str); +} + static void ddr_ctrl_init(uint32_t base) { DeviceState *dev; @@ -283,9 +292,12 @@ static void zynq_init(MachineState *machine) pic[n] =3D qdev_get_gpio_in(dev, n); } =20 - n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0); - n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n); - n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n); + n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0, + zynq_machine->flash_type); + n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n, + zynq_machine->flash_type); + n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n, + zynq_machine->flash_type); =20 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]= ); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]= ); @@ -473,6 +485,9 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) "Supported boot modes:" " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); + + prop =3D object_class_property_add_str(oc, "flash-type", NULL, zynq_se= t_flash_type); + object_property_set_default_str(prop, "n25q128"); } =20 static const TypeInfo zynq_machine_type =3D { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index ec80441e7c..7379fe3988 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -31,6 +31,7 @@ struct ZynqMachineState { Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; uint8_t boot_mode; + char *flash_type; }; =20 #endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3