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Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 09/15] hw/misc/zynq_slcr: Add logic for DCI configuration Date: Thu, 4 Dec 2025 10:34:56 +0100 Message-ID: <20251204093502.50582-10-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841118792019200 Content-Type: text/plain; charset="utf-8" From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Cali= bration The DCI control register and status register have been added. As soon as the ENABLE and RESET bit are set, the RESET bit has also been toggled to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status register is set. If these bits change the DONE bit is reset. Note that the option bits are not taken into consideration. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 010387beec..d8702da4ce 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -180,6 +180,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) =20 REG32(DDRIOB, 0xb40) +REG32(DDRIOB_DCI_CTRL, 0xb70) + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) +REG32(DDRIOB_DCI_STATUS, 0xb74) + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) #define DDRIOB_LENGTH 14 =20 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 @@ -193,6 +199,8 @@ struct ZynqSLCRState { =20 MemoryRegion iomem; =20 + bool ddriob_dci_ctrl_reset_toggled; + uint32_t regs[ZYNQ_SLCR_NUM_REGS]; =20 Clock *ps_clk; @@ -331,6 +339,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) =20 DB_PRINT("RESET\n"); =20 + s->ddriob_dci_ctrl_reset_toggled =3D false; + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_DDRIOB + 4] =3D s->regs[R_DDRIOB + 5] =3D s->regs[R_DDRIOB += 6] =3D 0x00000e00; s->regs[R_DDRIOB + 12] =3D 0x00000021; + + s->regs[R_DDRIOB_DCI_CTRL] =3D 0x00000020; } =20 static void zynq_slcr_reset_hold(Object *obj, ResetType type) @@ -554,6 +566,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, (int)offset, (unsigned)val & 0xFFFF); } return; + + case R_DDRIOB_DCI_CTRL: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)= ) { + + s->ddriob_dci_ctrl_reset_toggled =3D true; + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); + } + + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && + s->ddriob_dci_ctrl_reset_toggled) { + + s->regs[R_DDRIOB_DCI_STATUS] |=3D R_DDRIOB_DCI_STATUS_DONE_MAS= K; + } else { + s->regs[R_DDRIOB_DCI_STATUS] &=3D ~R_DDRIOB_DCI_STATUS_DONE_MA= SK; + } + break; } =20 if (s->regs[R_LOCKSTA]) { --=20 2.47.3