From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764840986; cv=none; d=zohomail.com; s=zohoarc; b=WXiy3xLcUe/ziKtYpWlqV/iCC1b99NXGvoZhGofWRi+pHz+7s2pBe45HtLUvOyJKnQGJHS4LieVlcXlzhRueu4uDneVpLtc5VG4vY+g18aEDKGaKv5KnPV3dpvvrbx85aWF7NrO2I3kjKCcHLvPgNKgTNHdNd3Q3D3XlBXSsYuw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764840986; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dD9uX6PaBNvNuAFjXV9Q7DahJDHptOizy7QDhFL8Gts=; b=cFt3waBK+f97pw4ICH1f056JuryLL4F9yTqthnv7rSRCykpKX/uUapcggnRlM7fMz7DAjrWwMhwlecf0+LOO+hn+lcWuAoAhdlthceP07z9PLORlJ+xh2z06Ibne7NoFmCmz/NwbXp34P3NAA32ryxiJ02nCjXgqa0Ry+8ThnZE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764840986238861.873044002396; Thu, 4 Dec 2025 01:36:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kI-0001ER-Hr; Thu, 04 Dec 2025 04:35:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5jz-00018A-VD for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:13 -0500 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5jv-0003N7-Jc for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:10 -0500 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-64180bd67b7so922417a12.0 for ; Thu, 04 Dec 2025 01:35:06 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840905; x=1765445705; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dD9uX6PaBNvNuAFjXV9Q7DahJDHptOizy7QDhFL8Gts=; b=Xaj+3bi2z29SWcHuBTqFEQKqLOo/QxCneReO0J7OGZNvlBuqggpvhOmre3qm3Bjfzs 0xyvmkMW29FEsom/hBKNUet9I6uhklVdiIMofCmy+ueEVlyGuoAGphNgNQqNQ9Nqdq01 CPMi64lj7EvqkIt68kPD5iq5ZzSV3nvkn6GSIz1bYyPya8V0eM9y6O75vknao/QRxxPf YerpzgAG9ff/FMGs5feOUP7wVlp3RhWN+BhwIdVuq8sMdq8cI4XZ6KquokkeVkbmim4e ZoqhBmyhmG71TzE52yOCANzUbHJXp1YODDBn0FBo6hFVK+2YpxfCLUAjJ3m2YVe/Y/Rr h64w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840905; x=1765445705; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=dD9uX6PaBNvNuAFjXV9Q7DahJDHptOizy7QDhFL8Gts=; b=Evh0uXrNcQI7V7sALLxbPMSrVGWR7f7bgQv8hb+2DaYzBQB6ML+7xxAxHxBPIbLzqg T4M1xt7k2nreecJ6G47D4XIxjZDGR5/fi/tezNBcdVVX76qGCrWahxq6nYui3siAXQlM tt0taFOmYXZhYam5fzIGZI+9QhulLJQmTwxzU93uWwrdku1P15f4X4Al0GB0wyRXDv6X DgIuCPUGwhpEf4iPVVPVP4S2F9iiMQuM2jsTY/3yAzegPwzvNkc2QpyazvNojKxNe9V7 o3hH8OdtCB+KAw6d/QUSP5MmfqQVEg3o5yHJg9HwI0gz9r+xfQmKQX++WyMZzBUF+Db9 Q3+w== X-Gm-Message-State: AOJu0Yydj9JJ5NISWVkjb1YMUVkBCMcque/UKhs1mkyc/BLz1EbQoq1p mAvUWYNI/hmhrEGZR+qolQh3v0r8R4fL1Min3Nei4hbAKwFExvV3EE8uXRji01/0 X-Gm-Gg: ASbGnctSl1beYwyPI+0OoxrURvwKvSTSjL3zJs2a+0LLaiItV3HXFCgPZRwdonDPBU1 6zJTojXJg84x8vlfGlgk7ZK3Tqyn3MWp18rJpNQBWY9GLa4xZjoz39phnxQ6GoeZW1DZr6Fuu+a Yd8U1OplORO9GgYBMCaKNqIeJkwp8fXyP4pzr39Xy/BqubLzJGZQmupNd086Az9mgWGtq9JoqJp bFuYPXR2m6EOniSw+cePQ/1mYsQBzhGHnLY4D0GXZZ26J16Y6g1Yiggv64ZSLsOHPaXTASC7whc BqS3UACoSAz+59x5w8MxQIUO4l2WbUdw8EjCAtKVO5DBzCiDs9fv39ztM3jQ3t9MhTNI8zOjR9Z mNifGBemLUhOyUwQUwzCEk2iKAyWJpEQC6zK+IunuRpvrnAJASJhbyyjAuMZL4U8nL13+iij/20 nVN2e/FfVoufKk0NMN+CrhYmuqsccMm6A= X-Google-Smtp-Source: AGHT+IE6d/SHN2OcrtrFj1TBqwCEjZQSDjJXv7k71DKG6n9hi6fDLIvewnwQZsYMCA7/FWlifx46kQ== X-Received: by 2002:a05:6402:2807:b0:647:5c27:5440 with SMTP id 4fb4d7f45d1cf-6479c49c55cmr4840711a12.24.1764840904695; Thu, 04 Dec 2025 01:35:04 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 01/15] hw/timer: Make frequency configurable Date: Thu, 4 Dec 2025 10:34:48 +0100 Message-ID: <20251204093502.50582-2-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::531; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840987816019200 Content-Type: text/plain; charset="utf-8" From: YannickV The a9 global timer and arm mp timers rely on the PERIPHCLK as their clock source. The current implementation does not take that into account. That causes problems for applications assuming other frequencies than 1 GHz. We can now configure frequencies for the a9 global timer and arm mp timer. By allowing these values to be set according to the application's needs, we ensure that the timers behave consistently with the expected system configuration. The SoC configures the device correctly. Information can be found in the Zynq 7000 SoC Technical Reference Manual under Timers. https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: YannickV --- hw/timer/a9gtimer.c | 9 ++++++--- hw/timer/arm_mptimer.c | 15 +++++++++++---- include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 4 files changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 690140f5a6..ad9abcb4bb 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -63,9 +63,9 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerState= *s) static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, - R_CONTROL_PRESCALER_LEN); - - return (prescale + 1) * 10; + R_CONTROL_PRESCALER_LEN) + 1; + uint64_t scaled_prescaler =3D prescale * 10; + return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz); } =20 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s) @@ -374,6 +374,9 @@ static const VMStateDescription vmstate_a9_gtimer =3D { }; =20 static const Property a9_gtimer_properties[] =3D { + /* Default clock-frequency is 1GHz (NANOSECONDS_PER_SECOND) */ + DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz, + NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), }; =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 7cc5915e9e..342ca1276a 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -59,9 +59,11 @@ static inline void timerblock_update_irq(TimerBlock *tb) } =20 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ -static inline uint32_t timerblock_scale(uint32_t control) +static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { - return (((control >> 8) & 0xff) + 1) * 10; + uint64_t prescale =3D (((control >> 8) & 0xff) + 1); + uint64_t scaled_prescaler =3D prescale * 10; + return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz); } =20 /* Must be called within a ptimer transaction block */ @@ -155,7 +157,7 @@ static void timerblock_write(void *opaque, hwaddr addr, ptimer_stop(tb->timer); } if ((control & 0xff00) !=3D (value & 0xff00)) { - ptimer_set_period(tb->timer, timerblock_scale(value)); + ptimer_set_period(tb->timer, timerblock_scale(tb, value)); } if (value & 1) { uint64_t count =3D ptimer_get_count(tb->timer); @@ -222,7 +224,8 @@ static void timerblock_reset(TimerBlock *tb) ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); - ptimer_set_period(tb->timer, timerblock_scale(0)); + ptimer_set_period(tb->timer, + timerblock_scale(tb, tb->control)); ptimer_transaction_commit(tb->timer); } } @@ -269,6 +272,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; + tb->freq_hz =3D s->freq_hz; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, @@ -301,6 +305,9 @@ static const VMStateDescription vmstate_arm_mptimer =3D= { }; =20 static const Property arm_mptimer_properties[] =3D { + /* Default clock-frequency is 1GHz (NANOSECONDS_PER_SECOND) */ + DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz, + NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), }; =20 diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 6ae9122e4b..3b63d14927 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -76,6 +76,7 @@ struct A9GTimerState { =20 MemoryRegion iomem; /* static props */ + uint64_t freq_hz; uint32_t num_cpu; =20 QEMUTimer *timer; diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index 65a96e2a0d..da43a3d351 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -31,6 +31,7 @@ typedef struct { uint32_t control; uint32_t status; struct ptimer_state *timer; + uint64_t freq_hz; qemu_irq irq; MemoryRegion iomem; } TimerBlock; @@ -43,6 +44,7 @@ struct ARMMPTimerState { SysBusDevice parent_obj; /*< public >*/ =20 + uint64_t freq_hz; uint32_t num_cpu; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841088; cv=none; d=zohomail.com; s=zohoarc; b=XSyEZ/0R7yv5CITTvRkceRScCDpu7g83Kx4O3bHSKD7Fv/ZP5M0TlpPRZhPmPjN97iRGmL8kDO2s1du0W9PVCtJLjeyRYPwfFvM/vqg039awncmI7VnS7RmsDvS8YKksCFJLl4l3OOfar+NinOjHij5+zWc1IMP0dd6g8FApR7o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841088; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=V1FaMp/q/JL2kLXBh26/LCxuSePONdt3doBm4ttYakg=; b=LR/3rgcVeBz0cpFXoj/ZAfTuooLDkRtSrS3bNDH0o8INCwfJtdAGoac4ftLMIh02MLYUCZVATNBW3nJOzoTjz9acfQEW7xLk6RNN+zIh/jMh/lcqZPMkDLWzUsuDy3dx9y1KKhxDQZrMW5wBKAg4uq1sQ7sLkoRb1ACBcVv9QZw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841088713114.83296769714298; Thu, 4 Dec 2025 01:38:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kX-0001Tz-Br; Thu, 04 Dec 2025 04:35:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k1-00018L-Mc for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:14 -0500 Received: from mail-ed1-x535.google.com ([2a00:1450:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5jv-0003NM-Od for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:11 -0500 Received: by mail-ed1-x535.google.com with SMTP id 4fb4d7f45d1cf-64320b9bb4bso1447799a12.0 for ; Thu, 04 Dec 2025 01:35:07 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840906; x=1765445706; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=V1FaMp/q/JL2kLXBh26/LCxuSePONdt3doBm4ttYakg=; b=IHXPZ3s5hd6LCBUCu98YO8sQqjWixd6KGSXkXth/rfPFAFQ8dgz236XPSXlZ4iRQYW 7JGsaUTQFt7VZHoFqtKXKGji5xHju8h6Iea0zXvzKGTmrV5u4bvrSY5HxtgRhJZxFPVp hIISQORqunC5QsqjqhodaCcUg5yDgCZMrEVy+E9cE0UPy0RPKUKl4le+KlyNXLAuueum FrNLNZ/BaOm0J4ALP1kbraHQdgL//a+FvE7NlUfbV1GYS86mto6sNBRWohL6pyRb+x3D BqmjtcmelY+cq95KFvXR+/Z0XMgBwKrwl3/aJqJeCojDFIxUhdgIt78Cg3FbMkHDt4tx mJ7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840906; x=1765445706; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=V1FaMp/q/JL2kLXBh26/LCxuSePONdt3doBm4ttYakg=; b=I2quXzDOUa5ssZHMI4VQ6tvsDUa0vNwk9ja64gC7UI7gPMJ6soHlu+iDvBHSYvWonx T9Ss212Ira0bPUrsjbHrFCnBjRBNXmO0sy/otPvdoOyfYk8A5RNy+No1lOYNMphFNXBN Iw4R0U0d+IbD3NshTsP+NjK/AlKAwA5Z2pXkhbaQoW4R2k1Q7JmkZMDengOf3b8zLLKY 8jdo8Hq/VoAmXNnX4Ij/n7nrz4P8Bvef3676HaRsEqt1Rlj7TWS2gN9KQdPx0hO4csHg IiAnIc3P9p2F33hSTn93wIw/jwRsNUWvE38CzMo1Og2lI7oLhn4XlYdGg9WCDCrYrD2C edgw== X-Gm-Message-State: AOJu0Yx/IStQ7hGSUQgbh0UPo+G/jghjF5Rwe8M378y5yXcgZ04t/7ml gIEDianQT8saQrk4py8sVXc4VrMsK44QJQLrbSmtVa6Ht9MnW/cjj+8EiereempX X-Gm-Gg: ASbGncuE6n2WDUzLbA1jgSpVOZawsQxHJJj5x+wkb+k8qqvpzK2uguwZhZyVOSgdDMl pqBRhJxAFlO37SGNvlRJ0re55Q2F14AjihMhvMPiP9U8P8wwmKozZUVIX4rtkIv/nNd4jZxUDtD K3xOhWFtSw97tkb+pJDKO3wYunMlGiAvBPTYlcFwvOdAwivYX5UrqS3GRqZ/mxT07g++GxzriJf R9uQSoWKDLlLPzF4AV2UvDFnuf+dYpJKuVYuyY44+QBCOzl+3gsiSb3YLl6fWzWVnvm6rWqmTO2 BkF3JU5z18Ki0t0wxw2tAX9w577e4kXC+mC9wRKiJw1FJ00FETy3vebqNJum7pReI4daJmFhzOw GO1N/QePJDzpOhup5nKkVeU/UIArXX5zEWADSrIoO1LL+AYBllItwT3c+EO3Bs+gRYH+wO5tYIJ 9JmrMYJsIpuVNAzg8sok/HK2rgA1hjc5g= X-Google-Smtp-Source: AGHT+IHRq32vLnXfjGTJTaruhjX4XUltJvv6j2Llyb23pMh4NpXzOx2taZeR1UpEXgy2R+erxhlA6A== X-Received: by 2002:a05:6402:3192:b0:640:998e:4471 with SMTP id 4fb4d7f45d1cf-647a69f7bc2mr1759622a12.5.1764840905891; Thu, 04 Dec 2025 01:35:05 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 02/15] hw/timer: Make PERIPHCLK divider configurable Date: Thu, 4 Dec 2025 10:34:49 +0100 Message-ID: <20251204093502.50582-3-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841090518019201 From: YannickV The A9 global timer and ARM MP timer use PERIPHCLK as their clock source. The frequency of PERIPHCLK is derived by dividing the main clock (CLK) by a configurable divider (must be at least 2). Previously, the PERIPHCLK divider was not configurable, which could lead to unexspected behavior if the application exspected a different PERIPHCLK rate. The property periphclk-divider specifies by which value the main clock is divided to generate PERIPHCLK. This allows flexible configuration of the timer clocks to match application requirements. Information can be found in the Zynq 7000 Soc Technical Reference Manual under Timers. https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: YannickV Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/a9gtimer.c | 19 ++++++++++++++++++- hw/timer/arm_mptimer.c | 19 ++++++++++++++++++- include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index ad9abcb4bb..8b4c6d7e6a 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -27,6 +27,7 @@ #include "hw/timer/a9gtimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/log.h" @@ -62,9 +63,17 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerStat= e *s) =20 static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The a9 global timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to a9 + * gtimer ticks can be calculated like this: + */ uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, R_CONTROL_PRESCALER_LEN) + 1; - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * s->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz); } =20 @@ -312,6 +321,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error = **errp) sysbus_init_mmio(sbd, &s->iomem); s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync= , s); =20 + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >=3D 2", + s->periphclk_divider); + return; + } + for (i =3D 0; i < s->num_cpu; i++) { A9GTimerPerCPU *gtb =3D &s->per_cpu[i]; =20 @@ -378,6 +393,8 @@ static const Property a9_gtimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", A9GTimerState, + periphclk_divider, 10), }; =20 static void a9_gtimer_class_init(ObjectClass *klass, const void *data) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 342ca1276a..cf434ca2f4 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -27,6 +27,7 @@ #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -61,8 +62,16 @@ static inline void timerblock_update_irq(TimerBlock *tb) /* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The arm mp timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to arm mp + * timer ticks can be calculated like this: + */ uint64_t prescale =3D (((control >> 8) & 0xff) + 1); - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * tb->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz); } =20 @@ -273,6 +282,12 @@ static void arm_mptimer_realize(DeviceState *dev, Erro= r **errp) for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; tb->freq_hz =3D s->freq_hz; + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >= =3D 2", + s->periphclk_divider); + return; + } + tb->periphclk_divider =3D s->periphclk_divider; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, @@ -309,6 +324,8 @@ static const Property arm_mptimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", ARMMPTimerState, + periphclk_divider, 10), }; =20 static void arm_mptimer_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 3b63d14927..ff9baf1c77 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -77,6 +77,7 @@ struct A9GTimerState { MemoryRegion iomem; /* static props */ uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; =20 QEMUTimer *timer; diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index da43a3d351..061934e4b5 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -32,6 +32,7 @@ typedef struct { uint32_t status; struct ptimer_state *timer; uint64_t freq_hz; + uint64_t periphclk_divider; qemu_irq irq; MemoryRegion iomem; } TimerBlock; @@ -45,6 +46,7 @@ struct ARMMPTimerState { /*< public >*/ =20 uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841059; cv=none; d=zohomail.com; s=zohoarc; b=WKTiZtu6ClEBbX4RPK8q7CuSBpVdu3E6AdErNs3fFImcWP1nw8IibXwZB6CDJ7PTLEgAIq+nL8QIZyrpb1MIfu+Y8CBhjvhCvBiUkosWEsO/GvhtFjHhkbt/ZFAbPNs2YRIuCBeoyJjyvZZU9uQ+6ygW/HR8uipoAVUmWWKY4fU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841059; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=k2Eh0GOKOaei3jLJLhPOl4V4bK4+Eil0n0H9DTtEdt4=; b=UYscXVeD6qGx69k+wrRL82FFb1qz+NfXj+0LnitF7QZg1dwsuOGLlCuc2BjOFqhoqPK4DV6SqxCuJxoUnu7XsQy68psIsHYD9mdJ4bWbRwn2+RSTH7f56tC5CLI23lM/DtqbKhREFCUFr3VugX//oiNSepdJUKIGgVOx0Zm1Y44= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841058955645.474102630944; Thu, 4 Dec 2025 01:37:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5ka-0001Xe-7H; Thu, 04 Dec 2025 04:35:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k3-00019W-1c for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:15 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5jy-0003Nk-FW for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:12 -0500 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-647a44f6dcaso866083a12.3 for ; Thu, 04 Dec 2025 01:35:08 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840907; x=1765445707; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=k2Eh0GOKOaei3jLJLhPOl4V4bK4+Eil0n0H9DTtEdt4=; b=NoyaK38g7NijisNn5NaWqYhx83V7QFdCkCBGJf9Ar0IpZO1e6rBOMG9p46MoLbU9LR Spezd/D5Obmaa6RPiCbDREm81RTkLxHttp6pD/1EqGqBlW2o2HtroVzkiNBGndc6d22i DH2qK5iMZ9eShEcg2j6secaS79aAwmoSBHgsbXjBThSsGLsmUvdmeZCHu8/YjMibVh/X yXYO5tj5h5aD9AimU7+BeSpBOdPIQ5PhjclWtMwswZOG+WIk+HefYUFIag24MgtkDaCq DyZ5hU/ubC/UfVTbDQEep6F7I8dpcEDiBhkIb/BRAXoJoMbTofgEqVJbcur++jRhQGie ln3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840907; x=1765445707; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=k2Eh0GOKOaei3jLJLhPOl4V4bK4+Eil0n0H9DTtEdt4=; b=YiAMO8t55k56OMzg8PNSnTZOT6RhHmrvP6npVddWFNN4WSJhHMXiWqvtwyAcBiwEfw FgL8k5tsMBT+0OhxcTEvmuW1s8q7tjrTpBjK1AK6eiV45RjFNPQOWyatZPzbg5i9Vjf1 GWDZYEXxtoV0o5KACQOg7zP1g+eRzvMYWsrwH0aiOT/DeFGOppzArtPpS6aNud+MIh8S uHPdK4BQwhIpMlGGjbqLFdYrn8fuqxbkb+L8SGtxh17xUvfOLkpJlpS4fPBkzEyp3awn biLxk8AKgH2uwJhh+bETfOyx05bHH48cR8V2pYXYVapzE1r0OXBFZf6yIgANy1BUIGTw y7ww== X-Gm-Message-State: AOJu0YyUy0l3o27LtzZZjunfzJVXr3abqgHkzkBDpzCUWEq5qpoRX1hS N8pQdXW7ib78rOhHQ/bu51rS2qu9F/zeRURZ+u7+j2hCJggv4Qo+JJRUVJGjLOCV X-Gm-Gg: ASbGncsAYBeLXwLKZD9WgEn7NhhH+Fdggjk9V6aZu8QALO82hLoiIUuHksaHvzu4NhS +tw7SrmIUSe3RRW1F0Uxn0zYoubMRguU/KSs7/LUQKN/GHi12ZtRHtbJ/jkDcNYW+HNGrIXO80e GmubNbU4u7CzMEh0MAgByNdxWn7Hi3tBxcq1Z/T9EciB1h3IHImsfLZ6J5NkQeF9xRp7tdf5JLy gkyb9lBFopnAOqqnZK22l1xm7ZEUp+ercd71NKU+tbgjLYGJAUAvYELpO87xjC5O/q8ZAQjQJo0 7HTHiOJBPFjWFXl686MpOEUxLg89f+LyU5JN8e+mchr/L0iEP7UfUpCPnY1q+KeyinJtmpq7GCX ZbLqm3HHxISf6Ws6E5U3lvFATpjzgVpvrRvyg2ckIwD2YkjPwDw9ucK4COroSknHLI+4JbJZA5t D5x1OhP4+gYxdegMeeMYIVIqQTY/lsc/zss067dVSrlA== X-Google-Smtp-Source: AGHT+IF13y7SN0Xslm4FgKr1E+BJcTBCa78t0jTJJ/ykK0Utu/E8iv3jeeP98vM7SkBC4ef8CkFPvQ== X-Received: by 2002:a05:6402:2351:b0:645:c99e:5e50 with SMTP id 4fb4d7f45d1cf-6479c4e710emr5278854a12.16.1764840906809; Thu, 04 Dec 2025 01:35:06 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 03/15] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Date: Thu, 4 Dec 2025 10:34:50 +0100 Message-ID: <20251204093502.50582-4-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841060198019200 Content-Type: text/plain; charset="utf-8" From: YannickV A DMA transfer to destination address `0xffffffff` should trigger a bitstream load via the PCAP interface. Currently, this case is not intercepted, causing loaders to enter an infinite loop when polling the status register. This commit adds a check for `0xffffffff` as the destination address. If detected, the relevant status register bits (`DMA_DONE`, `DMA_P_DONE`, and `PCFG_DONE`) are set to indicate a successful bitstream load. If the address is different, the DMA transfer proceeds as usual. A successful load is indicated but nothing is actually done. Guests relying on FPGA functions are still known to fail. This feature is required for the integration of the Beckhoff CX7200 model. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 8141d46033..2430d70bf7 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -247,7 +247,14 @@ static uint64_t r_lock_pre_write(RegisterInfo *reg, ui= nt64_t val) static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); - + if ((s->regs[R_DMA_DST_ADDR]) =3D=3D 0xffffffff) { + DB_PRINT("bitstream loading detected\n"); + s->regs[R_INT_STS] |=3D R_INT_STS_DMA_DONE_MASK | + R_INT_STS_DMA_P_DONE_MASK | + R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); + return; + } s->dma_cmd_fifo[s->dma_cmd_fifo_num] =3D (XlnxZynqDevcfgDMACmd) { .src_addr =3D s->regs[R_DMA_SRC_ADDR] & ~0x3UL, .dest_addr =3D s->regs[R_DMA_DST_ADDR] & ~0x3UL, --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764840992; cv=none; d=zohomail.com; s=zohoarc; b=bmv1mM/R4h4W/+mlr83uC+sSWZRwD+b0TlAQ/EqRtfDBULqu2s9IYwjyPRXm9Zz1WXLSw9B3ocTFlBiiq0/Xno0ZlsodPa4V0USSGUUTMdwu1Mh/kEnqob0uh9LpN5I+mMqqW+3dgwtyrXOzUonNqzmJnNdrOFTG5YuU+BfF3iI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764840992; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7b25Fv33Xq/PZxsyLv+FhSwrtyaBUSUZvYVfFNhl+n0=; b=Rdd6haEShjrB2qgOrx/xeD4G6d0MQhyNsOAmjBUF+SktPi3Nfj+PeGsHV1nOpycxggThvfW1KbCA3BDvqYZUKF9rY3scPtmuQOvd1pop5B8vXaFdpmT21QbnBFqNEnWFtRdRJNIS3f9qG7H5s0qN1tXZRLcdoZcJAR6KM0BzriE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764840992891547.4093073609488; Thu, 4 Dec 2025 01:36:32 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kc-0001aF-50; Thu, 04 Dec 2025 04:35:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k3-00019Y-30 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:15 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5jz-0003O3-LQ for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:13 -0500 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-63c489f1e6cso1178666a12.1 for ; Thu, 04 Dec 2025 01:35:09 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840908; x=1765445708; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7b25Fv33Xq/PZxsyLv+FhSwrtyaBUSUZvYVfFNhl+n0=; b=hP41a3BCOtLWdNUUIAksi8xnHw3KR4KvKCBsxwqHxbrdFl1PQUK2YE8qtkQi0Toieo B/UpivEQoXwDSYhQVfOGEZK6gdwRCxwkxe6XiRdjYtIpv8iGijqzhANe2VSgVKu94Zg2 +nUsIkYmBjrTC65Aw5P6ynnp8yu39IC2uHJCWO3z+z37QAgmAiEmCFCgMDHrmt+kkT7T 68JnjMTOgJtbcS9TwHP6jl/F7KoQ50TeYr6pI0DKom9gXy52aKfC9yqoZlKmeGxmApHO JWUpOjL/zIeSmy+ekWiFipWJ3Z6GREjEhIG+EOorVZtu1x+lgDTAu3gvmdtagNU1Nz6Z +5vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840908; x=1765445708; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=7b25Fv33Xq/PZxsyLv+FhSwrtyaBUSUZvYVfFNhl+n0=; b=WdPk4iKZvCqjVJPeuuYNMwg4CAgnvPV4bEVvPjaa+H4x3/6SeJI679n4f5ayQHnzzW c5JFqJIGPJ/J+02AeyuRktMROVfg/SzGx0ljpaDAc78pU6TaAVsFpjr7wwTSXN/hoaap D9B3ddhVXGd2VLMjNSQoOoYuow6xKJWeYpl+5wLYSY2NEelIqtGiIYYYxNGG5RvYFzQ5 KIydv75OuDgqbmGFxGRQfGUKnmPLG0JyIYzh7ju/GZBL4eilzGNGfEA40XGRShpyn+VT XZzFmWrgASy7UhcxLEP8i0TS3nLS2/A4O5SFxCTnlZKbOqgU95FVoTJNxMOTRSczmB9B h5aw== X-Gm-Message-State: AOJu0Yyj/1H9aXFMhcetc5U68n07wjN78BFwwODy176WatabEcSvjkd+ Uq5KblldwigTtzztqi60QTiuaSHwsL6bv5TtGh08Vvb9/kN+wXr15LdVb0mz7vLr X-Gm-Gg: ASbGncu+LS47UJ7zz+p0kyLgOe7WPDYLNO0IpYW4uBlSHQ7LaAs8b7KZgz24CPwWEXH coLn9YhZlZmgzO5sFXf85yHp3gUYsCuJp5fiwBPDmjNfsFXgYfaBYiULNQLuCLf0qXaKRcmqey4 6Qxiwj4RbUiAEFx4gqUIjhpq+osz1izr4GM3FdvE0/FB+sIfpahEpAnVK30djEC95VUMq9wnHh8 3jjE+mtWybhm7XabUEkq0dswO0E3hhLhf6veKRWFIpyacT8l65SX/cnold8PaNjup78Hi25/c8j sJhWoUt01zFshDJGpDxtUPkLJtMHgFXoJENexN/YR1SEXZiXh8/Sgsn7p/D0AcGF1TMbaVgpaN9 2dZY7UVG8Bk/OpXUid3adyVrCjcf2YsFL2ULQYXGQ4gbDLYyy4BlHJrSSYiUmIMeP7sU+5JMU9y Gtp+kGc4h1eatquoXtmtDyG/nq3SMroN8kkaNUKsJS1Q== X-Google-Smtp-Source: AGHT+IGD3i0LrPdz5e0vL2bVXHvaVwO3UwaQb643ryzJqh4NN+/Ny4XDYuq6HOVcEOUUcRWhewotkw== X-Received: by 2002:a05:6402:35c2:b0:641:1cbe:a5bf with SMTP id 4fb4d7f45d1cf-647a6a418a3mr2209665a12.9.1764840908018; Thu, 04 Dec 2025 01:35:08 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 04/15] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Date: Thu, 4 Dec 2025 10:34:51 +0100 Message-ID: <20251204093502.50582-5-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840993748019200 Content-Type: text/plain; charset="utf-8" From: YannickV During the emulation startup, all registers are reset, which triggers the `r_unlock_post_write` function with a value of 0. This led to an unintended memory access disable, making the devcfg unusable. During startup, the memory space no longer gets locked. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 2430d70bf7..0c06daa6b9 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -221,7 +221,9 @@ static void r_unlock_post_write(RegisterInfo *reg, uint= 64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); const char *device_prefix =3D object_get_typename(OBJECT(s)); - + if (device_is_in_reset(DEVICE(s))) { + return; + } if (val =3D=3D R_UNLOCK_MAGIC) { DB_PRINT("successful unlock\n"); s->regs[R_CTRL] |=3D R_CTRL_PCAP_PR_MASK; --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841165; cv=none; d=zohomail.com; s=zohoarc; b=F2hBTuH5yFchqowJpxaXb2zO5nyYeEnqfiidZAX27zlyaBZuRwCTmat9QpP4WnD/tTc/UxVqAbmDnz8t4+IRqwRwh0ooxNWgaIM3fjcpLrZeDKIZfb/m9SUU1ux+42KcLCbDepn8E/AB0zqr5SCTD4bv1kkxL2NBHkQj2n/wpew= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841165; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=GYKOAMZxGQEu+IKZWOj4QK/Xu0CKwD6MX43mJOeXe6Q=; b=fdasqT3IPKhdvD88v6ZXIDhNC6ujW6Xre0yPPKrUh+7zm8I+KAFlwneawb3a0RQbsQh5mKs6QtYEUeh+seScU+51A6hJ5X11dwrNyxnNmPwbakczIlq1asViNgAxcZCBe/CsGz1buzmT7m7BOyjUXasDdZ24gIR/P2lET8p3fOs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17648411656111.1303437035376191; Thu, 4 Dec 2025 01:39:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5ke-0001ff-9e; Thu, 04 Dec 2025 04:35:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k3-00019d-6w for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:16 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k0-0003OW-LO for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:14 -0500 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-640d0ec9651so1234317a12.3 for ; Thu, 04 Dec 2025 01:35:10 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840909; x=1765445709; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GYKOAMZxGQEu+IKZWOj4QK/Xu0CKwD6MX43mJOeXe6Q=; b=h+b5+rxxZAK4N/oAANxPfbezh9Bjcv+EwWJYryW+GCWSWDxcjctEpGPTfSH/b44LKP vOJQI0n4NEOIymBa7QDMXTmmsLo1xq/6PwSDBtMj6znjrrgSLP1MdAPAQK4bwE6cVdB/ TR7ThkGlwCHEk1SKIz3AJ5zwQ1PVBwr/jYBEpNoT+49Sk5+P1oh1Z3DoT2XNaUnY2a/F vwX8/PWyMvG4f0gLG2XjtzdDmJ0NvXHvY6zwgRm4oadbhRO4hMa6yp8B5sjbzl6hrn4v bk6DA1ftNg6xg6/2i6RpwItypfq6U6vTFLtMMHFtaMjDke9x6eMgHTOC9/d4XinEh27I 6h6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840909; x=1765445709; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=GYKOAMZxGQEu+IKZWOj4QK/Xu0CKwD6MX43mJOeXe6Q=; b=cuBxmTg5MTsAFtDbJIKh26TyDyISZiZKwyI6VlNcg5ANVzbTqbIT7Rp2Bwb5BzkHKi V0v/Jak8wBsNQVkp+nbuXGm3HcNIOKdOYtpQbWayOaITM8JOUSKJEu5CzeyUBT5d/4F+ QYRycdtBlBfYxhS0Q7XKCQn3HId+/qo7lcRtYaCr0wa0Two6Ey1z+VvCUdoeYRHXCrBo Jtox1AiJkQccpNPMdBPqbzl1ZTY76uI9p3RV7mu0uFIaI97G3diE1ayENTBW7x58Gm5g WYEeaPQy36tKi/86SfDCE8TvkasCgn7jH6xlw3NzncCWs+QwPc405rAhZu86BaCPVTku SCGA== X-Gm-Message-State: AOJu0YxWzJ9Uy1Q4lMQJGy1UJ4wZ29mJcPnI9MCaOZ/714Gp3WA6idaq Y0E7IHcYa7e1Y6n7XtmdrK+dds0NbBuWilUMGzYo6Z9uohJzKG7DHzct5Q2Fv3ax X-Gm-Gg: ASbGncs41qMn3yB6QUOi79rimeSRHYeL8vOt1loek65WAMbJSQxCPi1ultrQ/gh47R/ Np4rgu3QZznPpbxgHWpoQewe4Z1p41Irl7bAmvy/E/RdS7tcWLuV5o0VZk3xdAmYE9nfaqbFaLd nzTAGOyUetXEa6Bjvbpb3GZ8J5iejm3eChEaT9GyWVw11cGyjeKGcW/0ExbFWhd+6MONQDEY54k 4yVyNEmT8JJ6KdP9wzofzOBQSx5LLPF1pBmxGfAzp9/VDVk22Jyra0huf8cAjq0Fli41ru02+jM AJtyct4/FGNjPFeFfMpIXw1OdS28sJGdlulRpSxhvIyrAhZzSSxZ+1LFitdUU2RWcTSMiOGovEO ee4FDS8AZM4PdJnL1JPSl8+v0UqQ83qjoHvy+eCCBhTg2lXq0U+/aCnUm/rmlGPqQDkZ9GM+fA9 OZEtcHGUjhGSy7cZxuGa9csoiE2FyxTZE= X-Google-Smtp-Source: AGHT+IHRWE58FcvoPJ8ZSmwaHY03rwwe2vOUSoLt2uGh886mo3Qht6opR13pKJXbn8T91+cGXeqOsw== X-Received: by 2002:a05:6402:51c9:b0:641:8644:f87f with SMTP id 4fb4d7f45d1cf-6479c4f7003mr4697998a12.17.1764840909049; Thu, 04 Dec 2025 01:35:09 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 05/15] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Date: Thu, 4 Dec 2025 10:34:52 +0100 Message-ID: <20251204093502.50582-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841167170019200 Content-Type: text/plain; charset="utf-8" From: YannickV All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Since we can assume that programming is always done, the `PCFG_DONE` flag is always set to 1, so it will not never be cleared. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 0c06daa6b9..72f7b1f170 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -188,6 +188,8 @@ static void r_ixr_post_write(RegisterInfo *reg, uint64_= t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); =20 + s->regs[R_INT_STS] |=3D R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); } =20 --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841053; cv=none; d=zohomail.com; s=zohoarc; b=Jn7bkzEakDvyIUePHyku/9zerJmZ0iKM9+9uvbmopFCQRxvjgClb2+hDzT4vWUZebY8VHuUR+4GNdf7Dxfb4PiiMikALAo4Mcw1k97B3Lsx4yNrSpq+H+kjcU3FuibakVa/AQ8ttTbQ9NHQ0VGctzWtrnZLgMZZLLN5dHfytNfo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841053; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/rkLVpmvYPi7YnLbLN1p5rsM99VpTuNA1PPyZs5DkRU=; b=LEkbj7dtrSI29asy9JNFweiUlbf0T2bGeXyJ8maFx1vq9PXi+mXkSUl0oC96h+Mgoz92xnrAtjgKTMkTcfYJ2jdXmMkuONpztsEnvHPiX3AsBpTeUkrxxsRB1LqibV3Zd3Ns3M2qyJ3lBsffP5JxOlPcISV3ZCY0rleLlE2vtAQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841053369234.3703135354849; Thu, 4 Dec 2025 01:37:33 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kX-0001U1-CO; Thu, 04 Dec 2025 04:35:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k5-0001Ad-TX for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:19 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k1-0003P3-F7 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:15 -0500 Received: by mail-ed1-x52d.google.com with SMTP id 4fb4d7f45d1cf-64149f78c0dso998724a12.3 for ; Thu, 04 Dec 2025 01:35:11 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840910; x=1765445710; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/rkLVpmvYPi7YnLbLN1p5rsM99VpTuNA1PPyZs5DkRU=; b=UN6Dm/wZRDPKUrD1zahI5XqekPFj//tKKCJxVq3J/XLSJjomgF2rOv/bZiQG+w+IuX D/HlxBYJ/9e9IG6/SXfiZFfcTPOOFC0Q9WfWMJtsKr+nj7oZO5gfbJb6VjJELqg0mz2W gVHbhUUnkarfidd5rNX0OPZfpUcBQ0hoGN5k5+8veJ2k2aKheq/SXKtIHCo6D11puyQ5 y+jqwq3p1MtmsKDhDniORaU9sQCK+AnnHeLR9O6ZPce5A41jpiFjslj6M1LUzQKbLwne qVlhiUrA/69h0aE/TyPqg5qY8PZlvYUCaqhFnQk+VYi4NzFReZdd0UY48iCmqw+G51Zp udgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840910; x=1765445710; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=/rkLVpmvYPi7YnLbLN1p5rsM99VpTuNA1PPyZs5DkRU=; b=JspGQmY+xn/tqgygaoJt6G/Ka/fqP3Nw355rgAz0GXdjrs9/MKgXgCjTE8KRp8rGME LCinFERHEd6TKQ0nZC1/ThgLg4STQZS/fpr/YppiTc2u3AnAJySgCwg1OvLACH/ghBmw K5TDQk6x02eI5cU94yvX1nnGkGojEYHgH/z9k4OinJQM3RFEz5XuBUn1hiH7KIdsW61w v1XeHcVqo8GBinfC7dbOSVdcX+4NNJD+p4hz+n1UnC0YtgiqlKmvYMVsFwDs4Ccwty7f L2Tm2l8UlidAcbYd6TUWM6SGuV03fT1VJyi0H4cvNacBz4eNvDuYdSLfsEqxXf/TvWnA 3/LA== X-Gm-Message-State: AOJu0YzuGsnPQt5Se7jtYkuJ3NGztLZXcaua9N1QF6VuhD4PC6rsZMXa HnIDmm8wBliQGIQPtUKNxrU8ELM1rd6CtJbiEKR2BeC8n7kh8cJgvYW3oGXKocyn X-Gm-Gg: ASbGncvetIGcg5L5A8JqqSrNdIyZnbZlKVtBRGNz9YVWTJ0gFa/sYau0k7u99ySoXbr PZ43wXGHT4w2BKtxDXIMZuv6gudzQAmpI5CKCq+0zry1QeJEeBDCtL37ugf076Pz9rSMWMgpo3d rcS5mj6et94uuMuSNRvzAejlXjf9w4f2GNayWt+RZw72hwPeAiTwjuTV3zw5IEWYj/fyJU3pCxd 77h3+QhZShXQ30ArcOV/aFaYNMl5QyPwel1zpIm5CZ/n7qn3JC38DEDPa6X44o6pcFTxQbu43Re 6nEr/5mk3NxV04w87drUE4xmSTBCCU7AtbNk1ooUbyhuNE2pO1h8f51wzlzC+/XrJ+0Lamy/l6m /VoPRZQE4JeGLtTbS9biJqNhUxmAZyXI8XMUTwPmEJvLkapxtdiPZ9sFDEpaCjXXga+gt88SMfW w5zOgD6Idy567n1hK7HvorJUtQg/HFTdE= X-Google-Smtp-Source: AGHT+IEE/Dy9/q68MhBnUXI6cgvGWwaGEuHePLY892vj5mY8uUnlEdVaoLq+lNffPoqtZa1yM8JiKw== X-Received: by 2002:a05:6402:4310:b0:640:f8a7:aa25 with SMTP id 4fb4d7f45d1cf-6479c4b220cmr5051039a12.30.1764840910139; Thu, 04 Dec 2025 01:35:10 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 06/15] hw/dma/zynq-devcfg: Simulate dummy PL reset Date: Thu, 4 Dec 2025 10:34:53 +0100 Message-ID: <20251204093502.50582-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841054169019200 Content-Type: text/plain; charset="utf-8" From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG_PROG_B. Indicating the reset was successful. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 72f7b1f170..722d68a568 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -49,6 +49,7 @@ =20 REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignor= ed */ + FIELD(CTRL, PCFG_PROG_B, 30, 1) FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlo= ck */ FIELD(CTRL, PCAP_MODE, 26, 1) FIELD(CTRL, MULTIBOOT_EN, 24, 1) @@ -116,6 +117,7 @@ REG32(STATUS, 0x14) FIELD(STATUS, PSS_GTS_USR_B, 11, 1) FIELD(STATUS, PSS_FST_CFG_B, 10, 1) FIELD(STATUS, PSS_CFG_RESET_B, 5, 1) + FIELD(STATUS, PCFG_INIT, 4, 1) =20 REG32(DMA_SRC_ADDR, 0x18) REG32(DMA_DST_ADDR, 0x1C) @@ -204,6 +206,13 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg, ui= nt64_t val) val |=3D lock_ctrl_map[i] & s->regs[R_CTRL]; } } + + if (FIELD_EX32(val, CTRL, PCFG_PROG_B)) { + s->regs[R_STATUS] |=3D R_STATUS_PCFG_INIT_MASK; + } else { + s->regs[R_STATUS] &=3D ~R_STATUS_PCFG_INIT_MASK; + } + return val; } =20 --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764840986; cv=none; d=zohomail.com; s=zohoarc; b=lgD2idKb23tF6MJfOgznb/e0hG2Od7t+IMaRbMjXc1uL2VhT1V7Ll3mT/Z0YuOINPYFljGR3MeDkEdqhikljR4HdnBp1x6IT6twVEX3V26Eiyve92JTQzKMOKtm5mGLYxqnabFIa40jJGXm+GPm3vuQ7tXRwXMI0W9Gb++mg8tE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764840986; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Pfg+3r5e3fkTMweJDY05x2D0nfBscf4bb3i1khlEcLs=; b=Ky6eMpZMRdLBvSV4JAyLVk3vL//Npei9warQabM/Jxt0xr16JpIxRkg+NZ480W3ONLpRseQcZ3E111VfpYPkKDBwpitraJieceBlu6NDjsMPIyxhKzv60Y/LD6zUiglCuhK1n4fnnYSqdvtcEo6AlKz8w06VgJXnHHnk/JOesbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764840986330558.952726688178; Thu, 4 Dec 2025 01:36:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kf-0001iC-CV; Thu, 04 Dec 2025 04:35:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k7-0001BV-4E for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:20 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k2-0003Pm-Tq for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:17 -0500 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-6408f9cb1dcso1037600a12.3 for ; Thu, 04 Dec 2025 01:35:12 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840911; x=1765445711; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Pfg+3r5e3fkTMweJDY05x2D0nfBscf4bb3i1khlEcLs=; b=IiIPr18pO97Co4agTe3ETohSwv4ifgFVfLPGhmwp7tPSaCmCm10k6OlNbmF3vf8c9F wPmQ47qbkgYXzUkqoR5I9vu8l2kAU8wBMo1Y2KJ7eEstisoRyZr2sfDjIvXFP3UvcCFj KXS3byBbWgqp0x3NjgBCDczcphvgjeiSRKS0lljXc4IpYB5Uv9lAQu4eqqfhr5APqTVv hROqK/GjnFZQdoRGqlfdE7ElBnMnzIHC2yIB/6IvOQwcoZ06MUOx/lvSuDAPY1Hgiyty rM5y5z8YVzCkPLI8HWef2YFuOD9fiCwxX1BG00T/XiAzooUT7iGVZdk3xiK795UyzH4D yvNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840911; x=1765445711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Pfg+3r5e3fkTMweJDY05x2D0nfBscf4bb3i1khlEcLs=; b=sBz2GbH8pIF9uwQjP4fkLhHaRjHu0lgcWd28yIiq0dOkYRYOiB0mCfUvcpiQyypeqV VFO9YRw5oa6yO6ZDXeGig/175UMsprqsyDun31SD7HkhgrI0OqcWzb2326yyeE8jJXfU 26VmuA/434/+BHbRJkipcJQAnok/lw/HT448hKaYCKp2W7YGCFXfuFJ8DswnHQpwEq82 Svap0yF5lqNwa+hGWHc1p1Lwe7yTO0MQuANcVs1FDZPYOBWuJc5vXV4C6xi/vBpPAapW kj1eSST3lUo9+roXivvSlVYPU3B6IgVRNtWSoQt/BNQ10aPD/apq9VoIVb/mWU0cuqyv mQFg== X-Gm-Message-State: AOJu0YwP+/KfFiMOFQm3QC9gjWYQuwNbpNUa3IbRCL9zE1aQjgZ9zOiV 4HlzYhD1FU84Fv2k3d5G1l2yFDx3ZiQhY/JDDGA4NVV1S+/65BZwMDxfLyk8IOfa X-Gm-Gg: ASbGncvrtFogpIkhdVFeLzbBD/Dq37sVfVoejYpAKQPe7CdiYL77aCk7wEbxrBZYMbW ZdrznyJ+Fk20F20RX26goAhh6vbGB/fwjVF5luOn7ug/pqEb/qXBmAHfmTBWe31AAilWEHJhsDB Pb8rlgLbRPS7IQ8tNYz1VoSnfKrf0SBYlcqX1RwyH0FzUZ4SVUc71a8YrRP1oNpMx5DBkdDzqw3 g894ZNyBl0rZi2jaeXpoymDd4/cDsNZ2oUyPeSwRoOkyr6oxuV5AJWAQf0G3KMk+ZhYPB4zclrf 0+fXwiue1bFYJmY0I1wu9McDubcazVPVYIUiIxSbxZYowfLbh6uorlQOrBqQr4kHWE78M7iapZa 2s4bobLR6wL32o5cMvpjBnhXtiswNrbGLN12FBebLTE60QAH8YtI5iiBn3kVqLboOZ6ubx6r45/ dPROLj2g87aXIvUmG+EOqncuwuuE/8O8w= X-Google-Smtp-Source: AGHT+IFRf3LHkGMTeKzqM0EWxnZp7Zf/lsrWcTpTYLwWOhltIN/yp45v4fnUPpsbHleX7Oc15Kf4CQ== X-Received: by 2002:a05:6402:26cc:b0:641:1f22:fc68 with SMTP id 4fb4d7f45d1cf-647abddcb97mr1856056a12.24.1764840911099; Thu, 04 Dec 2025 01:35:11 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 07/15] hw/dma/zynq-devcfg: Indicate power-up status of PL Date: Thu, 4 Dec 2025 10:34:54 +0100 Message-ID: <20251204093502.50582-8-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840987744019200 Content-Type: text/plain; charset="utf-8" From: YannickV It is assumed, that the programmable logic (PL) is always powered during emulation. Therefor the PCFG_POR_B bit in the MCTRL register is set. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 722d68a568..bd8057caa9 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -333,7 +333,8 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_i= nfo[] =3D { /* Silicon 3.0 for version field, the mysterious reserved bit 23 * and QEMU platform identifier. */ - .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU= _MASK, + .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | + R_MCTRL_PCFG_POR_B_MASK | R_MCTRL_QEMU_MASK, .ro =3D ~R_MCTRL_INT_PCAP_LPBK_MASK, .rsvd =3D 0x00f00303, }, --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841111; cv=none; d=zohomail.com; s=zohoarc; b=eHf3HbkXey7DJmeZNDuzDI119BEJwk871FjGUJLjs37gTqEbFWYg9fSAE3WupMVd9MJdtone1hAU0SfBmPJI1wBSf8fe/C3J5wo7N7hNBRSyh665Hs1NDn5mbHFFeeMVUNyx8r1OgTYzjL8HaVThNunqzseckSCcyk0TpQSdhBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841111; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=tuhKr8tcgT6+mlw34YZY+4u+6pYYVBP54SxXZIOuzm8=; b=LRAJp4PBVEITc7TaRKwNMK/h7ZxjXDv1Pmlc8Tuq542eCXktTDKEQyDGhA0546Bg+xLmRUra9odykOk+ECn/6hQfQjfxjx+IJqzXuwUcKebwGvuXaqaJtQ+0oTVFoitlW+6vQZHVEgSthK2bdvsQKTOKkAigqjeEKK0FGU7kAJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841111068234.44786459110594; Thu, 4 Dec 2025 01:38:31 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kd-0001eb-Pb; Thu, 04 Dec 2025 04:35:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k8-0001Be-AA for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:21 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k2-0003QF-Tp for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:19 -0500 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-6408f9cb1dcso1037638a12.3 for ; Thu, 04 Dec 2025 01:35:13 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840912; x=1765445712; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tuhKr8tcgT6+mlw34YZY+4u+6pYYVBP54SxXZIOuzm8=; b=Hv39Ad2p7GSIyRsL4JHoqTdPSvYlAv1SMfv+PC8ZVn8ymVjyjmUQLcejftAQc+vocf U+T+/qMd9c0QxI8yxhQFzLTwtRk4eChPf28rprgRDACmTYSu+KnWjq7+C4bRrqeqjcMg sn70Vpt3G+GSA5n81AfFo8Qg9xUz6TQT3414eArfr9kzhJC0nCcalANeVIdMu6RQ/XfW aALwAEQXb2j8sWv1puK+9o+4QJutPN41YV8N5B7gb5eFLLp6pcGlhSRp0ZraBOiyuzY2 0unHyqLSXGyXEZn2yI4z8WmnJ+l4Z75wkDsvoO83ALWW4eKaGESR8MtJYGAmv1PRPp1G O0Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840912; x=1765445712; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=tuhKr8tcgT6+mlw34YZY+4u+6pYYVBP54SxXZIOuzm8=; b=Kj/Ig9FhXkTYJeTIoPnF4K/d8g6OatmC9VGiC+8BfScfxkdTJfM9Pmwfpam/tClIJX MM9OXL0t8ELIC+cspw8N4T/Bl2E+QIityeXtxIb4fapdiFWFmBvpNMmRO42ErKrnHWWn sL4zdvo2RidVw5wss6Soofkjcu2fpozT9suFB4b5JxIVIuB/6ryvVSABBQctWmUE6n+z rfb46VSx4AI9vbvjMznNhmgzOFFYozC0HUek8DySkLM20MAyM0rusfwq2h9TFyShDrOI XO3d9DKheLndgFM5m0At4Gw3Srh4MhrcZ7vKjjJNJTA04oG4sXREIPQ1ORAAsjkUCHW8 oerg== X-Gm-Message-State: AOJu0Yxv3hxCYcxFR2MVilez5ieYNrn+YSypgxmuc2luiNgsX9+IzC+u 70lm9URpGp6MN43TVBU9ZRJnMfZrlpX4DDLfonllpoJoTkFWEFVBkUpp00UHiN5b X-Gm-Gg: ASbGnctCelfZPH7A7Ocj4+QWaJH8Dtuninhfd1eO0kbYSW8m/25YsCQUVaFeD5kk1VX d8+89+TXpTp3iWs+35L7G2s07WSaNrp72T57HviEcP6ccQF6M7yFVQJ4QkitW+TqBDA0V2pdEfk 2mo26ALGTYdpJpz8Z+Jt60A8ciJsu6AAh9Ss/EwZCLPmUL70fVY3eE8fj1kaLbRnDQ39JsLj5na C7Gwqb1enaSRimRWpSkYQpWSKTwdDTU8eq+6jbW7uc50BcnQp5tybPG7gdKGu0P0V9FkQTHh4Q6 1w+plz4pPhz4+QdhxvCNLXwrc4dVw+uWVKcH1G88tni3HIdP1LpNJmRxyFaIJTIBW4tJSUqzoZ0 POpSJ38zSOUoyAIaetdXtwYeFfqpop00BoMJl3c9OLoJ4NG8A1uP0aY2Km3Gr2uX54SNcVmOPvW UhtX3o3WvT6heVRHfPal9USqiUgcvW4D0= X-Google-Smtp-Source: AGHT+IGbTp52ffiAOuTZ0CkHGcZnt1fCqBP/SAx3+ujyxgBGQ3xLec06lqUfgfp8wzncQt7cu1Ue9Q== X-Received: by 2002:a05:6402:430a:b0:647:a636:76c with SMTP id 4fb4d7f45d1cf-647abdf82e3mr1739596a12.31.1764840912236; Thu, 04 Dec 2025 01:35:12 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 08/15] hw/misc: Add dummy ZYNQ DDR controller Date: Thu, 4 Dec 2025 10:34:55 +0100 Message-ID: <20251204093502.50582-9-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841112678019200 Content-Type: text/plain; charset="utf-8" From: YannickV A dummy DDR controller for ZYNQ has been added. While all registers are pre= sent, not all are functional. Read and write access is validated, and the user mo= de can be set. This provides a basic DDR controller initialization, preventing system hangs due to endless polling or similar issues. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 16 +- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/xlnx-zynq-ddrc.c | 413 +++++++++++++++++++++++++++++++ include/hw/misc/xlnx-zynq-ddrc.h | 148 +++++++++++ 5 files changed, 578 insertions(+), 3 deletions(-) create mode 100644 hw/misc/xlnx-zynq-ddrc.c create mode 100644 include/hw/misc/xlnx-zynq-ddrc.h diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index c82edd3bed..c03ed09a67 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -201,6 +201,17 @@ static void zynq_set_boot_mode(Object *obj, const char= *str, m->boot_mode =3D mode; } =20 +static void ddr_ctrl_init(uint32_t base) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("zynq.ddr-ctlr"); + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); @@ -312,6 +323,8 @@ static void zynq_init(MachineState *machine) sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69-GIC_INTERNAL], pic[70-GIC_INTERNAL], pic[71-GIC_INTERNA= L], NULL); =20 + ddr_ctrl_init(0xF8006000); + gem_init(0xE000B000, pic[54 - GIC_INTERNAL]); gem_init(0xE000C000, pic[77 - GIC_INTERNAL]); =20 @@ -393,9 +406,6 @@ static void zynq_init(MachineState *machine) /* System Watchdog Timer Registers */ create_unimplemented_device("zynq.swdt", 0xF8005000, 4 * KiB); =20 - /* DDR memory controller */ - create_unimplemented_device("zynq.ddrc", 0xF8006000, 4 * KiB); - /* AXI_HP Interface (AFI) */ create_unimplemented_device("zynq.axi_hp0", 0xF8008000, 0x28); create_unimplemented_device("zynq.axi_hp1", 0xF8009000, 0x28); diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fccd735c24..3de37c9e1d 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -240,4 +240,7 @@ config IOSB config XLNX_VERSAL_TRNG bool =20 +config XLNX_ZYNQ_DDRC + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b1d8d8e5d2..ffbcca9796 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -95,6 +95,7 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xlnx-zynq-ddrc.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= apu-ctrl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( diff --git a/hw/misc/xlnx-zynq-ddrc.c b/hw/misc/xlnx-zynq-ddrc.c new file mode 100644 index 0000000000..0403be8189 --- /dev/null +++ b/hw/misc/xlnx-zynq-ddrc.c @@ -0,0 +1,413 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/registerfields.h" +#include "system/block-backend.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/dma.h" +#include "hw/misc/xlnx-zynq-ddrc.h" +#include "migration/vmstate.h" + +#ifndef DDRCTRL_ERR_DEBUG +#define DDRCTRL_ERR_DEBUG 0 +#endif + +static void zynq_ddrctrl_post_write(RegisterInfo *reg, uint64_t val) +{ + DDRCTRLState *s =3D DDRCTRL(reg->opaque); + if (reg->access->addr =3D=3D A_DDRC_CTRL) { + if (val & 0x1) { + s->reg[R_MODE_STS_REG] |=3D + (R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK & 0x1); + } else { + s->reg[R_MODE_STS_REG] &=3D + ~R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK; + } + } +} + +static const RegisterAccessInfo xlnx_zynq_ddrc_regs_info[] =3D { + /* 0x00 - 0x3C: Basic DDRC control and config */ + { .name =3D "DDRC_CTRL", + .addr =3D A_DDRC_CTRL, + .reset =3D 0x00000200, + .post_write =3D zynq_ddrctrl_post_write }, + { .name =3D "TWO_RANK_CFG", + .addr =3D A_TWO_RANK_CFG, + .reset =3D 0x000C1076 }, + { .name =3D "HPR_REG", + .addr =3D A_HPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "LPR_REG", + .addr =3D A_LPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "WR_REG", + .addr =3D A_WR_REG, + .reset =3D 0x0007F80F }, + { .name =3D "DRAM_PARAM_REG0", + .addr =3D A_DRAM_PARAM_REG0, + .reset =3D 0x00041016 }, + { .name =3D "DRAM_PARAM_REG1", + .addr =3D A_DRAM_PARAM_REG1, + .reset =3D 0x351B48D9 }, + { .name =3D "DRAM_PARAM_REG2", + .addr =3D A_DRAM_PARAM_REG2, + .reset =3D 0x83015904 }, + { .name =3D "DRAM_PARAM_REG3", + .addr =3D A_DRAM_PARAM_REG3, + .reset =3D 0x250882D0 }, + { .name =3D "DRAM_PARAM_REG4", + .addr =3D A_DRAM_PARAM_REG4, + .reset =3D 0x0000003C }, + { .name =3D "DRAM_INIT_PARAM", + .addr =3D A_DRAM_INIT_PARAM, + .reset =3D 0x00002007 }, + { .name =3D "DRAM_EMR_REG", + .addr =3D A_DRAM_EMR_REG, + .reset =3D 0x00000008 }, + { .name =3D "DRAM_EMR_MR_REG", + .addr =3D A_DRAM_EMR_MR_REG, + .reset =3D 0x00000940 }, + { .name =3D "DRAM_BURST8_RDWR", + .addr =3D A_DRAM_BURST8_RDWR, + .reset =3D 0x00020034 }, + { .name =3D "DRAM_DISABLE_DQ", + .addr =3D A_DRAM_DISABLE_DQ }, + { .name =3D "DRAM_ADDR_MAP_BANK", + .addr =3D A_DRAM_ADDR_MAP_BANK, + .reset =3D 0x00000F77 }, + { .name =3D "DRAM_ADDR_MAP_COL", + .addr =3D A_DRAM_ADDR_MAP_COL, + .reset =3D 0xFFF00000 }, + { .name =3D "DRAM_ADDR_MAP_ROW", + .addr =3D A_DRAM_ADDR_MAP_ROW, + .reset =3D 0x0FF55555 }, + { .name =3D "DRAM_ODT_REG", + .addr =3D A_DRAM_ODT_REG, + .reset =3D 0x00000249 }, + + /* 0x4C - 0x5C: PHY and DLL */ + { .name =3D "PHY_DBG_REG", + .addr =3D A_PHY_DBG_REG }, + { .name =3D "PHY_CMD_TIMEOUT_RDDATA_CPT", + .addr =3D A_PHY_CMD_TIMEOUT_RDDATA_CPT, + .reset =3D 0x00010200 }, + { .name =3D "MODE_STS_REG", + .addr =3D A_MODE_STS_REG }, + { .name =3D "DLL_CALIB", + .addr =3D A_DLL_CALIB, + .reset =3D 0x00000101 }, + { .name =3D "ODT_DELAY_HOLD", + .addr =3D A_ODT_DELAY_HOLD, + .reset =3D 0x00000023 }, + + /* 0x60 - 0x7C: Control registers */ + { .name =3D "CTRL_REG1", + .addr =3D A_CTRL_REG1, + .reset =3D 0x0000003E }, + { .name =3D "CTRL_REG2", + .addr =3D A_CTRL_REG2, + .reset =3D 0x00020000 }, + { .name =3D "CTRL_REG3", + .addr =3D A_CTRL_REG3, + .reset =3D 0x00284027 }, + { .name =3D "CTRL_REG4", + .addr =3D A_CTRL_REG4, + .reset =3D 0x00001610 }, + { .name =3D "CTRL_REG5", + .addr =3D A_CTRL_REG5, + .reset =3D 0x00455111 }, + { .name =3D "CTRL_REG6", + .addr =3D A_CTRL_REG6, + .reset =3D 0x00032222 }, + + /* 0xA0 - 0xB4: Refresh, ZQ, powerdown, misc */ + { .name =3D "CHE_REFRESH_TIMER0", + .addr =3D A_CHE_REFRESH_TIMER0, + .reset =3D 0x00008000 }, + { .name =3D "CHE_T_ZQ", + .addr =3D A_CHE_T_ZQ, + .reset =3D 0x10300802 }, + { .name =3D "CHE_T_ZQ_SHORT_INTERVAL_REG", + .addr =3D A_CHE_T_ZQ_SHORT_INTERVAL_REG, + .reset =3D 0x0020003A }, + { .name =3D "DEEP_PWRDWN_REG", + .addr =3D A_DEEP_PWRDWN_REG }, + { .name =3D "REG_2C", + .addr =3D A_REG_2C }, + { .name =3D "REG_2D", + .addr =3D A_REG_2D, + .reset =3D 0x00000200 }, + + /* 0xB8 - 0xF8: ECC, DFI, etc. */ + { .name =3D "DFI_TIMING", + .addr =3D A_DFI_TIMING, + .reset =3D 0x00200067 }, + { .name =3D "CHE_ECC_CONTROL_REG_OFFSET", + .addr =3D A_CHE_ECC_CONTROL_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_ECC_STATS_REG_OFFSET", + .addr =3D A_CHE_ECC_STATS_REG_OFFSET }, + { .name =3D "ECC_SCRUB", + .addr =3D A_ECC_SCRUB, + .reset =3D 0x00000008 }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET }, + + /* 0x114 - 0x174: PHY config, ratios, DQS, WE */ + { .name =3D "PHY_RCVER_ENABLE", + .addr =3D A_PHY_RCVER_ENABLE }, + { .name =3D "PHY_CONFIG0", + .addr =3D A_PHY_CONFIG0, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG1", + .addr =3D A_PHY_CONFIG1, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG2", + .addr =3D A_PHY_CONFIG2, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG3", + .addr =3D A_PHY_CONFIG3, + .reset =3D 0x40000001 }, + { .name =3D "PHY_INIT_RATIO0", + .addr =3D A_PHY_INIT_RATIO0 }, + { .name =3D "PHY_INIT_RATIO1", + .addr =3D A_PHY_INIT_RATIO1 }, + { .name =3D "PHY_INIT_RATIO2", + .addr =3D A_PHY_INIT_RATIO2 }, + { .name =3D "PHY_INIT_RATIO3", + .addr =3D A_PHY_INIT_RATIO3 }, + { .name =3D "PHY_RD_DQS_CFG0", + .addr =3D A_PHY_RD_DQS_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG1", + .addr =3D A_PHY_RD_DQS_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG2", + .addr =3D A_PHY_RD_DQS_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG3", + .addr =3D A_PHY_RD_DQS_CFG3, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WR_DQS_CFG0", + .addr =3D A_PHY_WR_DQS_CFG0 }, + { .name =3D "PHY_WR_DQS_CFG1", + .addr =3D A_PHY_WR_DQS_CFG1 }, + { .name =3D "PHY_WR_DQS_CFG2", + .addr =3D A_PHY_WR_DQS_CFG2 }, + { .name =3D "PHY_WR_DQS_CFG3", + .addr =3D A_PHY_WR_DQS_CFG3 }, + { .name =3D "PHY_WE_CFG0", + .addr =3D A_PHY_WE_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG1", + .addr =3D A_PHY_WE_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG2", + .addr =3D A_PHY_WE_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG3", + .addr =3D A_PHY_WE_CFG3, + .reset =3D 0x00000040 }, + + /* 0x17C - 0x194: Write data slaves, misc */ + { .name =3D "WR_DATA_SLV0", + .addr =3D A_WR_DATA_SLV0, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV1", + .addr =3D A_WR_DATA_SLV1, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV2", + .addr =3D A_WR_DATA_SLV2, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV3", + .addr =3D A_WR_DATA_SLV3, + .reset =3D 0x00000080 }, + { .name =3D "REG_64", + .addr =3D A_REG_64, + .reset =3D 0x10020000 }, + { .name =3D "REG_65", + .addr =3D A_REG_65 }, + + /* 0x1A4 - 0x1C4: Misc registers */ + { .name =3D "REG69_6A0", + .addr =3D A_REG69_6A0 }, + { .name =3D "REG69_6A1", + .addr =3D A_REG69_6A1 }, + { .name =3D "REG6C_6D2", + .addr =3D A_REG6C_6D2 }, + { .name =3D "REG6C_6D3", + .addr =3D A_REG6C_6D3 }, + { .name =3D "REG6E_710", + .addr =3D A_REG6E_710 }, + { .name =3D "REG6E_711", + .addr =3D A_REG6E_711 }, + { .name =3D "REG6E_712", + .addr =3D A_REG6E_712 }, + { .name =3D "REG6E_713", + .addr =3D A_REG6E_713 }, + + /* 0x1CC - 0x1E8: DLL, PHY status */ + { .name =3D "PHY_DLL_STS0", + .addr =3D A_PHY_DLL_STS0 }, + { .name =3D "PHY_DLL_STS1", + .addr =3D A_PHY_DLL_STS1 }, + { .name =3D "PHY_DLL_STS2", + .addr =3D A_PHY_DLL_STS2 }, + { .name =3D "PHY_DLL_STS3", + .addr =3D A_PHY_DLL_STS3 }, + { .name =3D "DLL_LOCK_STS", + .addr =3D A_DLL_LOCK_STS }, + { .name =3D "PHY_CTRL_STS", + .addr =3D A_PHY_CTRL_STS }, + { .name =3D "PHY_CTRL_STS_REG2", + .addr =3D A_PHY_CTRL_STS_REG2 }, + + /* 0x200 - 0x2B4: AXI, LPDDR, misc */ + { .name =3D "AXI_ID", + .addr =3D A_AXI_ID }, + { .name =3D "PAGE_MASK", + .addr =3D A_PAGE_MASK }, + { .name =3D "AXI_PRIORITY_WR_PORT0", + .addr =3D A_AXI_PRIORITY_WR_PORT0, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT1", + .addr =3D A_AXI_PRIORITY_WR_PORT1, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT2", + .addr =3D A_AXI_PRIORITY_WR_PORT2, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT3", + .addr =3D A_AXI_PRIORITY_WR_PORT3, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_RD_PORT0", + .addr =3D A_AXI_PRIORITY_RD_PORT0, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT1", + .addr =3D A_AXI_PRIORITY_RD_PORT1, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT2", + .addr =3D A_AXI_PRIORITY_RD_PORT2, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT3", + .addr =3D A_AXI_PRIORITY_RD_PORT3, + .reset =3D 0x000003FF }, + { .name =3D "EXCL_ACCESS_CFG0", + .addr =3D A_EXCL_ACCESS_CFG0 }, + { .name =3D "EXCL_ACCESS_CFG1", + .addr =3D A_EXCL_ACCESS_CFG1 }, + { .name =3D "EXCL_ACCESS_CFG2", + .addr =3D A_EXCL_ACCESS_CFG2 }, + { .name =3D "EXCL_ACCESS_CFG3", + .addr =3D A_EXCL_ACCESS_CFG3 }, + { .name =3D "MODE_REG_READ", + .addr =3D A_MODE_REG_READ }, + { .name =3D "LPDDR_CTRL0", + .addr =3D A_LPDDR_CTRL0 }, + { .name =3D "LPDDR_CTRL1", + .addr =3D A_LPDDR_CTRL1 }, + { .name =3D "LPDDR_CTRL2", + .addr =3D A_LPDDR_CTRL2, + .reset =3D 0x003C0015 }, + { .name =3D "LPDDR_CTRL3", + .addr =3D A_LPDDR_CTRL3, + .reset =3D 0x00000601 }, +}; + +static void zynq_ddrctrl_reset(DeviceState *dev) +{ + DDRCTRLState *s =3D DDRCTRL(dev); + int i; + + for (i =3D 0; i < ZYNQ_DDRCTRL_NUM_REG; ++i) { + register_reset(&s->regs_info[i]); + } +} + +static const MemoryRegionOps ddrctrl_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const VMStateDescription vmstate_zynq_ddrctrl =3D { + .name =3D "zynq_ddrc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, DDRCTRLState, ZYNQ_DDRCTRL_NUM_REG), + VMSTATE_END_OF_LIST() + } +}; + +static void zynq_ddrctrl_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + DDRCTRLState *s =3D DDRCTRL(obj); + + s->reg_array =3D + register_init_block32(DEVICE(obj), xlnx_zynq_ddrc_regs_info, + ARRAY_SIZE(xlnx_zynq_ddrc_regs_info), + s->regs_info, s->reg, + &ddrctrl_ops, + DDRCTRL_ERR_DEBUG, + ZYNQ_DDRCTRL_MMIO_SIZE); + + sysbus_init_mmio(sbd, &s->reg_array->mem); +} + +static void zynq_ddrctrl_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, zynq_ddrctrl_reset); + dc->vmsd =3D &vmstate_zynq_ddrctrl; +} + +static const TypeInfo ddrctrl_info =3D { + .name =3D TYPE_DDRCTRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DDRCTRLState), + .instance_init =3D zynq_ddrctrl_init, + .class_init =3D zynq_ddrctrl_class_init, +}; + +static void ddrctrl_register_types(void) +{ + type_register_static(&ddrctrl_info); +} + +type_init(ddrctrl_register_types) diff --git a/include/hw/misc/xlnx-zynq-ddrc.h b/include/hw/misc/xlnx-zynq-d= drc.h new file mode 100644 index 0000000000..3d45a02176 --- /dev/null +++ b/include/hw/misc/xlnx-zynq-ddrc.h @@ -0,0 +1,148 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef XLNX_ZYNQ_DDRC_H +#define XLNX_ZYNQ_DDRC_H + +#include "hw/sysbus.h" +#include "hw/register.h" + +#define TYPE_DDRCTRL "zynq.ddr-ctlr" +#define DDRCTRL(obj) \ + OBJECT_CHECK(DDRCTRLState, (obj), TYPE_DDRCTRL) + +REG32(DDRC_CTRL, 0x00) +REG32(TWO_RANK_CFG, 0x04) +REG32(HPR_REG, 0x08) +REG32(LPR_REG, 0x0C) +REG32(WR_REG, 0x10) +REG32(DRAM_PARAM_REG0, 0x14) +REG32(DRAM_PARAM_REG1, 0x18) +REG32(DRAM_PARAM_REG2, 0x1C) +REG32(DRAM_PARAM_REG3, 0x20) +REG32(DRAM_PARAM_REG4, 0x24) +REG32(DRAM_INIT_PARAM, 0x28) +REG32(DRAM_EMR_REG, 0x2C) +REG32(DRAM_EMR_MR_REG, 0x30) +REG32(DRAM_BURST8_RDWR, 0x34) +REG32(DRAM_DISABLE_DQ, 0x38) +REG32(DRAM_ADDR_MAP_BANK, 0x3C) +REG32(DRAM_ADDR_MAP_COL, 0x40) +REG32(DRAM_ADDR_MAP_ROW, 0x44) +REG32(DRAM_ODT_REG, 0x48) +REG32(PHY_DBG_REG, 0x4C) +REG32(PHY_CMD_TIMEOUT_RDDATA_CPT, 0x50) +REG32(MODE_STS_REG, 0x54) + FIELD(MODE_STS_REG, DDR_REG_DBG_STALL, 3, 3) + FIELD(MODE_STS_REG, DDR_REG_OPERATING_MODE, 0, 2) +REG32(DLL_CALIB, 0x58) +REG32(ODT_DELAY_HOLD, 0x5C) +REG32(CTRL_REG1, 0x60) +REG32(CTRL_REG2, 0x64) +REG32(CTRL_REG3, 0x68) +REG32(CTRL_REG4, 0x6C) +REG32(CTRL_REG5, 0x78) +REG32(CTRL_REG6, 0x7C) +REG32(CHE_REFRESH_TIMER0, 0xA0) +REG32(CHE_T_ZQ, 0xA4) +REG32(CHE_T_ZQ_SHORT_INTERVAL_REG, 0xA8) +REG32(DEEP_PWRDWN_REG, 0xAC) +REG32(REG_2C, 0xB0) +REG32(REG_2D, 0xB4) +REG32(DFI_TIMING, 0xB8) +REG32(CHE_ECC_CONTROL_REG_OFFSET, 0xC4) +REG32(CHE_CORR_ECC_LOG_REG_OFFSET, 0xC8) +REG32(CHE_CORR_ECC_ADDR_REG_OFFSET, 0xCC) +REG32(CHE_CORR_ECC_DATA_31_0_REG_OFFSET, 0xD0) +REG32(CHE_CORR_ECC_DATA_63_32_REG_OFFSET, 0xD4) +REG32(CHE_CORR_ECC_DATA_71_64_REG_OFFSET, 0xD8) +REG32(CHE_UNCORR_ECC_LOG_REG_OFFSET, 0xDC) +REG32(CHE_UNCORR_ECC_ADDR_REG_OFFSET, 0xE0) +REG32(CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, 0xE4) +REG32(CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, 0xE8) +REG32(CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, 0xEC) +REG32(CHE_ECC_STATS_REG_OFFSET, 0xF0) +REG32(ECC_SCRUB, 0xF4) +REG32(CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, 0xF8) +REG32(CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, 0xFC) +REG32(PHY_RCVER_ENABLE, 0x114) +REG32(PHY_CONFIG0, 0x118) +REG32(PHY_CONFIG1, 0x11C) +REG32(PHY_CONFIG2, 0x120) +REG32(PHY_CONFIG3, 0x124) +REG32(PHY_INIT_RATIO0, 0x12C) +REG32(PHY_INIT_RATIO1, 0x130) +REG32(PHY_INIT_RATIO2, 0x134) +REG32(PHY_INIT_RATIO3, 0x138) +REG32(PHY_RD_DQS_CFG0, 0x140) +REG32(PHY_RD_DQS_CFG1, 0x144) +REG32(PHY_RD_DQS_CFG2, 0x148) +REG32(PHY_RD_DQS_CFG3, 0x14C) +REG32(PHY_WR_DQS_CFG0, 0x154) +REG32(PHY_WR_DQS_CFG1, 0x158) +REG32(PHY_WR_DQS_CFG2, 0x15C) +REG32(PHY_WR_DQS_CFG3, 0x160) +REG32(PHY_WE_CFG0, 0x168) +REG32(PHY_WE_CFG1, 0x16C) +REG32(PHY_WE_CFG2, 0x170) +REG32(PHY_WE_CFG3, 0x174) +REG32(WR_DATA_SLV0, 0x17C) +REG32(WR_DATA_SLV1, 0x180) +REG32(WR_DATA_SLV2, 0x184) +REG32(WR_DATA_SLV3, 0x188) +REG32(REG_64, 0x190) +REG32(REG_65, 0x194) +REG32(REG69_6A0, 0x1A4) +REG32(REG69_6A1, 0x1A8) +REG32(REG6C_6D2, 0x1B0) +REG32(REG6C_6D3, 0x1B4) +REG32(REG6E_710, 0x1B8) +REG32(REG6E_711, 0x1BC) +REG32(REG6E_712, 0x1C0) +REG32(REG6E_713, 0x1C4) +REG32(PHY_DLL_STS0, 0x1CC) +REG32(PHY_DLL_STS1, 0x1D0) +REG32(PHY_DLL_STS2, 0x1D4) +REG32(PHY_DLL_STS3, 0x1D8) +REG32(DLL_LOCK_STS, 0x1E0) +REG32(PHY_CTRL_STS, 0x1E4) +REG32(PHY_CTRL_STS_REG2, 0x1E8) +REG32(AXI_ID, 0x200) +REG32(PAGE_MASK, 0x204) +REG32(AXI_PRIORITY_WR_PORT0, 0x208) +REG32(AXI_PRIORITY_WR_PORT1, 0x20C) +REG32(AXI_PRIORITY_WR_PORT2, 0x210) +REG32(AXI_PRIORITY_WR_PORT3, 0x214) +REG32(AXI_PRIORITY_RD_PORT0, 0x218) +REG32(AXI_PRIORITY_RD_PORT1, 0x21C) +REG32(AXI_PRIORITY_RD_PORT2, 0x220) +REG32(AXI_PRIORITY_RD_PORT3, 0x224) +REG32(EXCL_ACCESS_CFG0, 0x294) +REG32(EXCL_ACCESS_CFG1, 0x298) +REG32(EXCL_ACCESS_CFG2, 0x29C) +REG32(EXCL_ACCESS_CFG3, 0x2A0) +REG32(MODE_REG_READ, 0x2A4) +REG32(LPDDR_CTRL0, 0x2A8) +REG32(LPDDR_CTRL1, 0x2AC) +REG32(LPDDR_CTRL2, 0x2B0) +REG32(LPDDR_CTRL3, 0x2B4) + + +#define ZYNQ_DDRCTRL_MMIO_SIZE 0x400 +#define ZYNQ_DDRCTRL_NUM_REG (ZYNQ_DDRCTRL_MMIO_SIZE / 4) + +typedef struct DDRCTRLState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + RegisterInfoArray *reg_array; + uint32_t reg[ZYNQ_DDRCTRL_NUM_REG]; + RegisterInfo regs_info[ZYNQ_DDRCTRL_NUM_REG]; +} DDRCTRLState; +#endif --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841118; cv=none; d=zohomail.com; s=zohoarc; b=iUZQTHdxscCXtHoNWMGyNBMOA4wpkWjnstTXCNgHn6Fx+JFkN56WTbqt3yrY3/IzKYgegdSGMunTgg01LY32XqjL6Gr2yYb9Zyc5UwvAv6NI8YVMQfVy6M5YbCD5o/tq2lPQM0Lx/KCqyfDf+JSJn80fqFsGU5Y9xT3l8gSq1ec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841118; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=A1i0haX05wPH7+qqw20aGMRGdV4gaXbDlVbiQ7m2y5A=; b=E4hb0xXcc+JXlFFZHLfS8UnDeVva56P5tZ6zB+ifucTdzdWUvLIFCo8wbRvng3fq8VUbxIEI7M23o3C3+kX79ycny9esNcVHwhhxghi6nGzVDUJ7YRI5ZPSL7FgZxh7JOkTDXmznPpMAkoTs2t7EHq96itk6W2s6whwZcodrSIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841118489975.988943340349; Thu, 4 Dec 2025 01:38:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kq-0001xa-68; Thu, 04 Dec 2025 04:36:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k7-0001BY-U3 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:21 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k4-0003Ql-TP for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:19 -0500 Received: by mail-ed1-x530.google.com with SMTP id 4fb4d7f45d1cf-64198771a9bso1183601a12.2 for ; Thu, 04 Dec 2025 01:35:15 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840914; x=1765445714; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A1i0haX05wPH7+qqw20aGMRGdV4gaXbDlVbiQ7m2y5A=; b=I0gWVUVWnUuZCNeH6WrgDfI7DxaQZMimO4jz0Igm2ZstLOEkUw+aJAxYjE6dbY6VH5 TVFZXvDTpyQZaCo99XVQeloR/+y/qOzZnQF9OoPrJS2B1dl9J/GzPGIW/OCKvnzQrjkf rKr05EdDB15GrGGDQm+QuAT2uXUvFfTEW7wifZrcph2penPM3+hG59rXTI/ecaFZCt8n K9/CmT7IKkyDxpi00YACQ/MZNhhuyjD0dpZtLxwPGflpuKnmBq4vxADwk/Zbgw7WpsNZ RlZjzd465jpPsR96FHWO6WtzR02I9zAuZea1hoAWrowc8rHBF8psYThymsxq77h/2JM0 6wXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840914; x=1765445714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=A1i0haX05wPH7+qqw20aGMRGdV4gaXbDlVbiQ7m2y5A=; b=Sy1qkaFgSfD/3UpveQf0Gu3Cdg9rmabFUA04HuhuvCd5T1IoMQ0Or65dr6Ng8TCqrQ kzlyj0ARpZUcnwFkePu7TK8E46CDxH76xMECVlGb3OL8NBaz8YXQfG+wA+LZhfk5tZNv Em2XvZ3tv4vjbFWgCa/V3sjJKMkPikY1SHYPf/9a2KAPCMCeTfnmYFRSRSSfc9LnpkgA 8MU+yl+4mVmL0flQ2sAVPMbgZHFrJdvR++sUw/9XMkDFp9j4ebU3Ziw3vF/wS0H/5dn2 x1h4z/hdRMtJGJ4Gjzxy3IH9rJc51DqSHRV8Jdr92l8DGfiNqZ/gQwhZi7VFAbd/EkEa B+Mg== X-Gm-Message-State: AOJu0YwVb8KryoClldkgLS/IXz6ppXtH+NnuENAhgaiMas1QKTCY4C9S /1+wfyA5iJQMKQj82Ix7y9TrcbKf1FD0ik2EqvKrPL6CZC1B4x5wdIKBeRqhFGhK X-Gm-Gg: ASbGncviwsYZdiYcOzUDvRcaRXIFD2A5macZePExU/LSncA0fWgJpXAuTmGDce5nLJh SSXGZ0S1f4FFAhi2RkisyE8GBoji7H/qp4DphUJAFNlEkFMUM53HoxTH9EO8V9LiXTwTkv4r0ex YMQZs5M/qKQHFTMgFEFN0TqxlFu0tvN4N83eVRuAr0YBw0R/hZY/I+aeHheYKmknION0kysvLqd MQ9gwyoiuV11sEjOafZAjNCxboqdXX/ZU+gmBatNeSNGoZ4OqfKXvZ2fMdBZ/nbk4UxIDJgDtrk VxMpDpTTt8xO2aBgHWjvK4gp3Zeqn0VMQ2QUqmsep9CHBm0gKdFZeYTO6YlyclGy9p2M92+mMtC rbhBSGE0KiYtL/EyYxz5VKPU/E0XBS2gtx1JLeLhx69mBIaQl551AN4WOwdTk6XDDeQspyjA/LZ lSwTSFClUNaoBlqbuN+dWC7wpq2KJ4guA= X-Google-Smtp-Source: AGHT+IG8rL9464dTajU1ktk2gMR4Mu/f5eNl7PPvNO2woc6gSwfllc8gw5M+wFEdHrnZIddyGLcKVg== X-Received: by 2002:a05:6402:4304:b0:645:d73e:6f60 with SMTP id 4fb4d7f45d1cf-6479c41df28mr5000957a12.12.1764840913759; Thu, 04 Dec 2025 01:35:13 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV , "Edgar E. Iglesias" Subject: [PATCH v5 09/15] hw/misc/zynq_slcr: Add logic for DCI configuration Date: Thu, 4 Dec 2025 10:34:56 +0100 Message-ID: <20251204093502.50582-10-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841118792019200 Content-Type: text/plain; charset="utf-8" From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Cali= bration The DCI control register and status register have been added. As soon as the ENABLE and RESET bit are set, the RESET bit has also been toggled to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status register is set. If these bits change the DONE bit is reset. Note that the option bits are not taken into consideration. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index 010387beec..d8702da4ce 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -180,6 +180,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) =20 REG32(DDRIOB, 0xb40) +REG32(DDRIOB_DCI_CTRL, 0xb70) + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) +REG32(DDRIOB_DCI_STATUS, 0xb74) + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) #define DDRIOB_LENGTH 14 =20 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 @@ -193,6 +199,8 @@ struct ZynqSLCRState { =20 MemoryRegion iomem; =20 + bool ddriob_dci_ctrl_reset_toggled; + uint32_t regs[ZYNQ_SLCR_NUM_REGS]; =20 Clock *ps_clk; @@ -331,6 +339,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) =20 DB_PRINT("RESET\n"); =20 + s->ddriob_dci_ctrl_reset_toggled =3D false; + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_DDRIOB + 4] =3D s->regs[R_DDRIOB + 5] =3D s->regs[R_DDRIOB += 6] =3D 0x00000e00; s->regs[R_DDRIOB + 12] =3D 0x00000021; + + s->regs[R_DDRIOB_DCI_CTRL] =3D 0x00000020; } =20 static void zynq_slcr_reset_hold(Object *obj, ResetType type) @@ -554,6 +566,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, (int)offset, (unsigned)val & 0xFFFF); } return; + + case R_DDRIOB_DCI_CTRL: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)= ) { + + s->ddriob_dci_ctrl_reset_toggled =3D true; + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); + } + + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && + s->ddriob_dci_ctrl_reset_toggled) { + + s->regs[R_DDRIOB_DCI_STATUS] |=3D R_DDRIOB_DCI_STATUS_DONE_MAS= K; + } else { + s->regs[R_DDRIOB_DCI_STATUS] &=3D ~R_DDRIOB_DCI_STATUS_DONE_MA= SK; + } + break; } =20 if (s->regs[R_LOCKSTA]) { --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841037; cv=none; d=zohomail.com; s=zohoarc; b=gd6HREjNEU4sifY44OuFxyrLpIp+RIQvRMmv7gQenzUKgZeA4paK7JIz9bGeaRoBdrR+vwrqeCFnNFwEodeyyrX0UP5NKfHIrkuhcDa9oUmBtMRhb1RcNiMslpCPPpcguH+am2cRL3oDNp2ql8tsWl0746UOm6gpO4u7GOhnmtk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841037; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=fjSjlmOdpjZQhrKRdJsmQ3aaRl/swzR9Pvv1RdsP+JY=; b=Zymf0+JAIJldB/fXOV0l8N1eWimkrMo+bDGxjBsCc9JIZi4oVIo+fIFsFLvgp9dIjXCMj9ahmRLIIkKuk0Q92Esyv0gSwgMt40a5g1PR5v/pDFROtl3inCyeOr2sIGU79/m1IshLm6vlG0rO+nICORSJuVG0Jd1WNFQMSmcTYRM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17648410374731019.8335060609191; Thu, 4 Dec 2025 01:37:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kn-0001pA-Jp; Thu, 04 Dec 2025 04:36:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5kB-0001E1-0f for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:25 -0500 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k6-0003Rp-QG for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:22 -0500 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-6419b7b4b80so984205a12.2 for ; Thu, 04 Dec 2025 01:35:16 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840915; x=1765445715; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fjSjlmOdpjZQhrKRdJsmQ3aaRl/swzR9Pvv1RdsP+JY=; b=Uu6Ky4Xj9W1zIsi2dTvJBe68HQNISbgyAOKb+Tmjp/sX9BQm97PZJBZ16U9sXzOWBf Y2Bho/6VxZV+K3aj7zYGLg1mf5659/mh10vi1b4DNVWsypyLYxh5TEK0BteNH+3Kfpoy V4ivPVR5uRFEppXeCvbBLHT07Lf3EdIyfmCDuyX4mIPzorRDwOHdzpPyAE6dH8zOtjXi pK2uwTJxvj9syk1FfQJjSLvIc4M8pUfV3j2il2d47Rl416LHDQrXKBvifuozburGxNlS pK4hmeDCbrYAu5ogG9CLSqCLgWuHQ5sFI2UXHrcmg+iTUlWud1yXpU4JvSL27APuwTLE ckAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840915; x=1765445715; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=fjSjlmOdpjZQhrKRdJsmQ3aaRl/swzR9Pvv1RdsP+JY=; b=R3Ad2D8qGB+vInys8ek7LwsQ7bHm9bg+0durwgd44jhK1DuTVWCC1pKpr8qqjWEX02 PaEuk9H2asMM951XrUTDKv+sCK4oz9z70mR4m411RM2VXmmOkCBMAxZMafAT1byG7kTq RA3of+BxN3RsU/unGgx8qCy6Y8aEKF3JFU28b/yt7eLhnRl9OLWDLEO/bESxZwINk9gX X1pJdPTECrB3dAMOhNQzWhK0cw23K7bqTbMkUG0b8GVHZ8tvZxYdPg5xjVOvGWb0t0gI wgpzQchl7ArA9uChJ5utbXHKzADaRRf9AvrWgUcsgAV3rbKKNsvONeWOhXwmRz/i0o0z 7Tog== X-Gm-Message-State: AOJu0YxbGfF2W9WNyIRsxlg6+so1S4nHyk9Ci+3X1Vkr25L1s+ddZ0HY EZsxRy6gnJGbwCyzHx2SWfZQ9QpvKjwgslr4WGeWSzEYSEwVM/tiKif372//m41G X-Gm-Gg: ASbGncuaQPX4rUBJepPdvk+WMAcq6lMSqAJSgw3vISIkBlszqa3ScwEFbDkYskAObJg uOngcORUPpBf44f6CpH1zEJX08f+ocYUB5sjfsvLQTtm4xCXfRTRfMN/okhfnM2Qvj5aYvB4J2b zFwNw2jmAb6FAwL1EnYVPIHRMLY6aH1E7F4oh65gPoi24eeKMPTBpKNH2Ym6EK2cd8Wy42Odoju pAbRQ4e81jDOoCdfYpYh7n1h0OHEmjHl/YQQcOJRX0yqIfwkr5tpXQl21mymJNO9jb6F/ke+6yq 1/aFRYszXf9U7nBMWqSH3LPiTK1sGMlKwtHmCadKS8TNmkE66Bed6ADDfZxEVB/B2Q3eWkTAu8t KUdLMojq75rdi5SC0ZMxZRvmgNgqSXPPe2uyw3eMSHk78AH/0Vi3Ylmm6nmcQNHw/CtQmeGJjOD SERSSf7rhLXIaqQPn8nlq6FF82PyoeckKRbtT/bb6G7g== X-Google-Smtp-Source: AGHT+IGoQJyRkPlY9BPYAyFhFIvgUp6OykwaUf+WoOAh36+lIu4EAB8HBlChei/6WYibtuaaZVUt1g== X-Received: by 2002:a05:6402:2106:b0:641:15d:6b97 with SMTP id 4fb4d7f45d1cf-6479c47206amr4257168a12.2.1764840914957; Thu, 04 Dec 2025 01:35:14 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 10/15] hw/misc: Add Beckhoff CCAT device Date: Thu, 4 Dec 2025 10:34:57 +0100 Message-ID: <20251204093502.50582-11-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841038211019200 Content-Type: text/plain; charset="utf-8" From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a power of two. If no EEPROM binary is handed over an empty EEPROM of size 4096 is initialized. This device is needed for the Beckhoff CX7200 board emulation. Signed-off-by: YannickV --- hw/misc/Kconfig | 3 + hw/misc/beckhoff_ccat.c | 339 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 343 insertions(+) create mode 100644 hw/misc/beckhoff_ccat.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 3de37c9e1d..1eb57b421f 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -243,4 +243,7 @@ config XLNX_VERSAL_TRNG config XLNX_ZYNQ_DDRC bool =20 +config BECKHOFF_CCAT + bool + source macio/Kconfig diff --git a/hw/misc/beckhoff_ccat.c b/hw/misc/beckhoff_ccat.c new file mode 100644 index 0000000000..afc7a9e338 --- /dev/null +++ b/hw/misc/beckhoff_ccat.c @@ -0,0 +1,339 @@ +/* + * Beckhoff Communication Controller Emulation + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/units.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "system/dma.h" +#include "qemu/error-report.h" +#include "block/block.h" +#include "block/block_int.h" +#include "block/qdict.h" +#include "hw/block/block.h" +#include "migration/vmstate.h" +#include "qemu/bswap.h" + +#ifndef CCAT_ERR_DEBUG +#define CCAT_ERR_DEBUG 0 +#endif + +#define TYPE_BECKHOFF_CCAT "beckhoff-ccat" +OBJECT_DECLARE_SIMPLE_TYPE(BeckhoffCcat, BECKHOFF_CCAT) + +#define MAX_NUM_SLOTS 32 +#define CCAT_FUNCTION_BLOCK_SIZE 16 + +#define CCAT_EEPROM_OFFSET 0x100 +#define CCAT_DMA_OFFSET 0x8000 + +#define CCAT_MEM_SIZE (64 * KiB) +#define CCAT_DMA_SIZE 0x800 +#define CCAT_EEPROM_SIZE 0x20 + +#define EEPROM_MEMORY_SIZE 0x1000 + +#define EEPROM_CMD_OFFSET (CCAT_EEPROM_OFFSET + 0x00) + #define EEPROM_CMD_WRITE_MASK 0x2 + #define EEPROM_CMD_READ_MASK 0x1 +#define EEPROM_ADR_OFFSET (CCAT_EEPROM_OFFSET + 0x04) +#define EEPROM_DATA_OFFSET (CCAT_EEPROM_OFFSET + 0x08) + +#define DMA_BUFFER_OFFSET (CCAT_DMA_OFFSET + 0x00) +#define DMA_DIRECTION_OFFSET (CCAT_DMA_OFFSET + 0x7c0) + #define DMA_DIRECTION_MASK 1 +#define DMA_TRANSFER_OFFSET (CCAT_DMA_OFFSET + 0x7c4) +#define DMA_HOST_ADR_OFFSET (CCAT_DMA_OFFSET + 0x7c8) +#define DMA_TRANSFER_LENGTH_OFFSET (CCAT_DMA_OFFSET + 0x7cc) + +/* + * The informationblock is always located at address 0x0. + * Address and size are therefor replaced by two identifiers. + * The Parameter give information about the maximal number of + * function slots and the creation date (in this case 01.01.2001) + */ +#define CCAT_ID_1 0x88a4 +#define CCAT_ID_2 0x54414343 +#define CCAT_INFO_BLOCK_PARAMS ((MAX_NUM_SLOTS << 0) | (0x1 << 8) | \ + (0x1 << 16) | (0x1 << 24)) + +#define CCAT_FUN_TYPE_ENTRY 0x0001 +#define CCAT_FUN_TYPE_EEPROM 0x0012 +#define CCAT_FUN_TYPE_DMA 0x0013 + +typedef struct BeckhoffCcat { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t mem[CCAT_MEM_SIZE]; + + BlockBackend *eeprom_blk; + uint8_t *eeprom_storage; + uint32_t eeprom_size; +} BeckhoffCcat; + +static void sync_eeprom(BeckhoffCcat *s) +{ + if (!s->eeprom_blk) { + return; + } + blk_pwrite(s->eeprom_blk, 0, s->eeprom_size, s->eeprom_storage, 0); +} + +static uint64_t beckhoff_ccat_eeprom_read(void *opaque, hwaddr addr, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_eeprom_write(void *opaque, hwaddr addr, uint64_t= val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + uint64_t eeprom_adr; + uint64_t buf; + uint32_t bytes_to_read; + + switch (addr) { + case EEPROM_CMD_OFFSET: + eeprom_adr =3D ldl_le_p(&s->mem[EEPROM_ADR_OFFSET]); + eeprom_adr =3D (eeprom_adr * 2) % s->eeprom_size; + if (val & EEPROM_CMD_READ_MASK) { + buf =3D 0; + bytes_to_read =3D 8; + if (eeprom_adr > s->eeprom_size - 8) { + bytes_to_read =3D s->eeprom_size - eeprom_adr; + } + buf =3D ldn_le_p(s->eeprom_storage + eeprom_adr, bytes_to_read= ); + stq_le_p(&s->mem[EEPROM_DATA_OFFSET], buf); + } else if (val & EEPROM_CMD_WRITE_MASK) { + buf =3D ldl_le_p(&s->mem[EEPROM_DATA_OFFSET]); + stw_le_p((uint16_t *)(s->eeprom_storage + eeprom_adr), buf); + sync_eeprom(s); + } + break; + default: + stn_le_p(&s->mem[addr], size, val); + } +} + +static uint64_t beckhoff_ccat_dma_read(void *opaque, hwaddr addr, unsigned= size) +{ + BeckhoffCcat *s =3D opaque; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + if (s->mem[DMA_TRANSFER_OFFSET] & 0x1) { + s->mem[DMA_TRANSFER_OFFSET] =3D 0; + } + break; + } + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_dma_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + dma_addr_t dmaAddr; + uint8_t len; + uint8_t *mem_buf; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + len =3D s->mem[DMA_TRANSFER_LENGTH_OFFSET]; + mem_buf =3D &s->mem[DMA_BUFFER_OFFSET]; + dmaAddr =3D ldl_le_p(&s->mem[DMA_HOST_ADR_OFFSET]); + if (s->mem[DMA_DIRECTION_OFFSET] & DMA_DIRECTION_MASK) { + dma_memory_read(&address_space_memory, dmaAddr, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } else { + /* + * The write transfer uses Host DMA Address + 8 as the target + * offset, as described in the CCAT manual Version 0.0.41 + * section 20.2. + */ + dma_memory_write(&address_space_memory, dmaAddr + 8, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } + break; + } + stn_le_p(&s->mem[addr], size, val); +} + +static uint64_t beckhoff_ccat_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + BeckhoffCcat *s =3D opaque; + uint64_t val =3D 0; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + return beckhoff_ccat_eeprom_read(opaque, addr, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + return beckhoff_ccat_dma_read(opaque, addr, size); + } else { + val =3D ldn_le_p(&s->mem[addr], size); + } + + return val; +} + +static void beckhoff_ccat_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + beckhoff_ccat_eeprom_write(opaque, addr, val, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + beckhoff_ccat_dma_write(opaque, addr, val, size); + } else { + stn_le_p(&s->mem[addr], size, val); + } +} + +static const MemoryRegionOps beckhoff_ccat_ops =3D { + .read =3D beckhoff_ccat_read, + .write =3D beckhoff_ccat_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static void beckhoff_ccat_reset(DeviceState *dev) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + + memset(&s->mem[0], 0, MAX_NUM_SLOTS * CCAT_FUNCTION_BLOCK_SIZE); + + size_t offset =3D 0 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_ENTRY); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], CCAT_INFO_BLOCK_PARAMS); + stl_le_p(&s->mem[offset + 8], CCAT_ID_1); + stl_le_p(&s->mem[offset + 12], CCAT_ID_2); + + offset =3D 11 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_EEPROM); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_EEPROM_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_EEPROM_SIZE); + + offset =3D 15 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_DMA); + stw_le_p(&s->mem[offset + 2], 0x0000); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_DMA_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_DMA_SIZE); +} + +static void beckhoff_ccat_realize(DeviceState *dev, Error **errp) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + BlockBackend *blk; + + blk =3D s->eeprom_blk; + + if (blk) { + uint64_t blk_size =3D blk_getlength(blk); + if (!is_power_of_2(blk_size)) { + error_setg(errp, "Blockend size is not a power of two."); + return; + } + + if (blk_size < 512) { + error_setg(errp, "Blockend size is too small."); + return; + } else { + blk_set_perm(blk, BLK_PERM_WRITE, BLK_PERM_ALL, errp); + + s->eeprom_size =3D blk_size; + s->eeprom_blk =3D blk; + s->eeprom_storage =3D blk_blockalign(s->eeprom_blk, s->eeprom_= size); + + if (!blk_check_size_and_read_all(s->eeprom_blk, DEVICE(s), + s->eeprom_storage, s->eeprom_= size, + errp)) { + return; + } + } + } else { + s->eeprom_size =3D EEPROM_MEMORY_SIZE; + s->eeprom_storage =3D blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } +} + +static void beckhoff_ccat_init(Object *obj) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &beckhoff_ccat_ops, s, + TYPE_BECKHOFF_CCAT, CCAT_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_beckhoff_ccat =3D { + .name =3D "beckhoff-ccat", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8_ARRAY(mem, BeckhoffCcat, CCAT_MEM_SIZE), + VMSTATE_UINT32(eeprom_size, BeckhoffCcat), + VMSTATE_VBUFFER_UINT32(eeprom_storage, BeckhoffCcat, 1, NULL, + eeprom_size), + VMSTATE_END_OF_LIST() + } +}; + +static const Property beckhoff_ccat_properties[] =3D { + DEFINE_PROP_DRIVE("eeprom", BeckhoffCcat, eeprom_blk), +}; + +static void beckhoff_ccat_class_init(ObjectClass *klass, const void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D beckhoff_ccat_realize; + device_class_set_legacy_reset(dc, beckhoff_ccat_reset); + dc->vmsd =3D &vmstate_beckhoff_ccat; + device_class_set_props(dc, beckhoff_ccat_properties); +} + +static const TypeInfo beckhoff_ccat_info =3D { + .name =3D TYPE_BECKHOFF_CCAT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BeckhoffCcat), + .instance_init =3D beckhoff_ccat_init, + .class_init =3D beckhoff_ccat_class_init, +}; + +static void beckhoff_ccat_register_types(void) +{ + type_register_static(&beckhoff_ccat_info); +} + +type_init(beckhoff_ccat_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index ffbcca9796..cd76e04a33 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -14,6 +14,7 @@ system_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l= 2x0.c')) system_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integra= tor_debug.c')) system_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) system_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) +system_ss.add(when: 'CONFIG_BECKHOFF_CCAT', if_true: files('beckhoff_ccat.= c')) =20 system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) =20 --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841179; cv=none; d=zohomail.com; s=zohoarc; b=loTerD1JWHXRosMkFBhjMaKQoxPQZpl6wg7juIioqTLEcijtiNhvChpSUHu2kXptsH5iAp+JAxnuqPiZsFa0Ii6301Y7EV/bEsR2+ft9ktTitbBgyThLJR1Y7A8NlSEakrIKVTUvuEaR+pqLLHUoAHNLd1mclindXvMVTqX+fio= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841179; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1IEAaSPzmzz5B3AM/apm91VbHSHgHQnwVHyZGTcUVH8=; b=n4pYR5NA7XLdWPoiHhfwgALEt2df0HfgFGw3tz2qINKOmH+SJ5wCLNzph5ZvUCyJV9JwQpxHzFIopjreiNQ6qqYy/KflRrvfcHuxbngNfT9CIGhilK+057kuUxYDXBK/fMh7AEh6jdoSPMd+6HO0iA2RtBS/nXsBjBlBNYNP0Jo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841179486734.1598455893678; Thu, 4 Dec 2025 01:39:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kg-0001id-0S; Thu, 04 Dec 2025 04:35:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5k9-0001C7-8C for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:21 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k6-0003S4-Q6 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:20 -0500 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-64320b9bb4bso1448102a12.0 for ; Thu, 04 Dec 2025 01:35:17 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840916; x=1765445716; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1IEAaSPzmzz5B3AM/apm91VbHSHgHQnwVHyZGTcUVH8=; b=OlPHENvKc0U09m5wD+TkZ+B9JdMfH7KSYzIhLa49u9UJPwO0i/yp/hhhpb8lESupHI qHtRoAThwwW5YQn2CzQ2J7nXQIzuQMrWSQchKjEgHA98Cc1NwyaBehThLzda8S9JZ1mp ixvMimXKPfUzXu2yGZFjqARP4Oit0YvuxrW+N2XlJRLmwjPbgYdfllQdXIKmzaBXsmy0 56V/mn0fIRRbR87/pJ9skz0TLwL0SxPuuwJSFquikL1msRMmTtNOaBPc+Or5P6UQgYlx 6wg0uPlHk61hh5NSGXB34k8o7GhZ/9hsXGhJsqokTGCimDPJRMmda8A/LjqH8qjMW9x2 Nx8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840916; x=1765445716; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=1IEAaSPzmzz5B3AM/apm91VbHSHgHQnwVHyZGTcUVH8=; b=Ighuao1Vlk1S+kWP+jmiUgkWTB8tIBd0zeVe3YdVpK21JsRBuXfDh6yxu5uAM96sQ5 IC6Ptl0EdPh7sZVmmiFPKQhwUtazKa+2LuzepaEi7n7f6ENxKAt7Y9/rtBv92vscZeNp lDS7gkzQsiF3/c5r45S5mRatcLcAf1Yplk4FOBkupbxL1RmrXfqIrsj65cUgywSXbtZa CYhbiTDCOY85VuHD/z2vdtRgN2gC4hRCagwyzcioJU8OwQCoLfryUZxeuGXZXll+6ZQv GuK5GW5wNYA45q5x8F2bNSFSk3dlEsZxwNiCSEjjNKZ0YJ7bTtPQo090AkQ2K1HUPOUB D70Q== X-Gm-Message-State: AOJu0YzI4Z2/lI1RdWwZ8EFjyMZef4/SqzvqhFf3wIscjAOsMWleedgT 5UqtJfDt5GxuMEv9IfM8Y2dIuw2U8gwYfNB+g3ISjlI6HWGTvMcvJQZwCyOp6sdr X-Gm-Gg: ASbGncvmqPnaepuimKO3otR6Wi4xhcOV/JK1lllxBdrB0I7o25Br+IsPm1bRUCGFJ8q S0hUs0PEiLV+IFogrCGeGHSxGYoNs/0uA1hWTe8Bll5RTi0/xD4VHoa/fd7QcdNCIpmNkJbp8O5 RNIO6CgFm4J748YJKScyAjFxa5Jr7GkU4eiZyGAfRQsWSFYPv2vu6PSTLkRGvCX818VE9+jA74U ODaI9SoEuQcgrvlzSwE2tlUVHnCLroh9jsZYw/UqEhwfFT2po4UNTxufJvQRc/AhRWR+ZMEaden 8S2c9G7LWBpjC8HNZe5d1tNeptmtcaS7FIbmE/gg/uUMgKixVTiThgPcGtt9rKgYdrAnQPFBXL1 fFc69zpraIyGdUOmKlDfjcsaMN74G7IhqKlFpCIQfcHZ6/EeXRmftgfiY75nh18ggu6VpMAw2AR McoCpIf+2XsbZa9C8DpnzyMIrrgHbSdCbi6uEe/swvHQ== X-Google-Smtp-Source: AGHT+IGvV+sCGJwOTFpGpCKdSMYu4U7c5oQUZ4Ip2HqD6FJoA3/JuJo/SVgHxJKIEhPAkKuNBJvIvw== X-Received: by 2002:a05:6402:1ec5:b0:647:7bfb:6ce4 with SMTP id 4fb4d7f45d1cf-647a69e6aa4mr2398833a12.1.1764840915995; Thu, 04 Dec 2025 01:35:15 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 11/15] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Date: Thu, 4 Dec 2025 10:34:58 +0100 Message-ID: <20251204093502.50582-12-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841181213019200 Content-Type: text/plain; charset="utf-8" From: YannickV The is25lp016d has 4 Block Write Protect Bits. BP3 specifies whether the upper or lower range should be protected. Therefore, we add the HAS_SR_TB flag to the is25lp016d flags. Signed-off-by: YannickV --- hw/block/m25p80.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a5336d92ff..1df223ee81 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -217,7 +217,8 @@ static const FlashPartInfo known_devices[] =3D { /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, - { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, + { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, + ER_4K | HAS_SR_TB) }, { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764840987; cv=none; d=zohomail.com; s=zohoarc; b=fp/TINhSqIJNz5/6hD7xTZniVO42ZgLuVy9xJeCZmEHug+uPbaa2TDdlo/LL2LKiNCF1l/MtAdTfj7qNvM13H1zmKNTWfmfiVpkotIMXaXHRxbtVAVjQpwcZnIoRvo/ipdRQ2TQpgIgZHs02Q75qfXuUZKm1EdFSv5AcZ/eFUhw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764840987; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YDQJUrQzwQ5JOi2EX7Frys9dODpqxnEfpv5EfNFdo4A=; b=UVgwCM9mC5+5UiD/rILgCYt3Jpsbrhe8k3QPewye6cLWpI/UCgQq47wqKlc+5fUTAj5Eg80OvGQOA4Ry4b6oHtbJMua4l8R4qomqQC/h5QL4C8ghcf8TRRY0e0htHGVIz1lBoKLDKkIbEyu05/NaVNGrijoyBkXt2PyXTE3ZNhs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764840987416626.4394867356808; Thu, 4 Dec 2025 01:36:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kT-0001QI-WC; Thu, 04 Dec 2025 04:35:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5kA-0001Ds-95 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:24 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k6-0003Sk-QE for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:21 -0500 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-6431b0a1948so1129379a12.3 for ; Thu, 04 Dec 2025 01:35:18 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840917; x=1765445717; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YDQJUrQzwQ5JOi2EX7Frys9dODpqxnEfpv5EfNFdo4A=; b=J89ySl6z1EDkevZk80qgeUx3u8zec3qIylU32/0gtxdNFag3TtVC9LliTcR3/sCdtq fB6Y111Rtl8Dz0pk/ohmX4fcNLGtZB5iPq9ojMGzyfL6IwC8iFnvh7y/iCRPhXYu6L1p PS5sn1ZvrQVft4pgmAaEo+sFVv6qLClW3SI5jgszJ3HpoOyGuCd7QinOL+XcgCbLhKhw 9k2B0RaNk4bLDfD5k6K2ah4QkAOcMInNNeEz0NNq9LoQJbhVVugi027U3WR/NFhxRFyD JfqKpNMtFiYA7ADTMOcCpOC2ExnnXTLMjAAAXHL9wAWQHH13+H/RHRjuodfOxsp03hAw QIqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840917; x=1765445717; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=YDQJUrQzwQ5JOi2EX7Frys9dODpqxnEfpv5EfNFdo4A=; b=J4V1w8XsdkGmJeIf/+2IMyn7k6XAEef43fYTQ+VlI60BE0zQXjjY/oFNrhFMe+JoG3 qmU29c/Rl9KWn5cCnwHu4ntPyKYvlh/vM0LWkSl7rwIIeV8WCtnUIPW/hkkqgIBIbMHb rVN7Dtp7/da6kHslwTFq8Q1OP5VrcIb44B8hmY+92c11Wz9f0G8b/XJBfaRd8s91CtXL o1x8YFnNt0nHyJgd9AIBgVkKK7Nb3rXEdcOCJgRxgiUJ+1PCpBiI5v9ZxynuquJyIlsc +E7bOEMwM2eAtilNtH9Igi34gRZbMC/kyDmGtuyNW+N9fadQ4HxsX51JEfTucKG58sb7 jSdA== X-Gm-Message-State: AOJu0Yxy/Vkw1a1aorwvb3oXPSnrm5ZkUZEr+hKi/Jgx6c288TrJMqA2 Zgtm64ZoduxBAQQLtISm+L9+cmiLKsHDNE+F+PkFdnfz6XlQ/PKML1WWv1z+sR37 X-Gm-Gg: ASbGncs/SnJ9pSexiwtgF8ZuJrckJqkqhRB44JZ4bDHzsvEGhTIjWialfQZKH1mPFiI hzqfXGX5Tp6CY+vjLXh25xzFbu6dCm8gkd1NvOfJbqAa6S+twlGbwYwv9jdmZc0GBg0c3MPwrbr 47KzRienjdQtWvpefAAJBxBm8ZwEX3mOWoXYv2C7poUrIYIeBpGg/R3JSmmVcSwn1u0KjVBiRGU IUDsr2GnwwuwScHwqIkzDS05qlCwFNIcpvH9dUEeVoEmgBi11zjwhsDJ9QNC/c8Kvlnk+LXGCAr SyytE5ZhTSlSppi137t/k5pQHtT6pKpoOGgVDpolkMRu2HuMvEE1jFu1MwO/bVKMTmk2eyvrPdn mZ1kpLnwCFThFGUd0IJQay2qRKMJqfh4CWQZDOv69n+N/j5XuN1QP/IoBKo5LS5hooy2mEB4FVk 2T3xThw9nY6fElL4XYpmhsQ7zhQZb+7dA= X-Google-Smtp-Source: AGHT+IFq1Dj2cz1jPd1sM4YW1icb+M+nQwDN4Zgyx9JcbDECbN+4vyvd2TJyB3LCHde5Q7QFDa2PTw== X-Received: by 2002:a05:6402:26c5:b0:647:5c87:8668 with SMTP id 4fb4d7f45d1cf-647abda024dmr1934226a12.14.1764840917071; Thu, 04 Dec 2025 01:35:17 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 12/15] hw/arm/xilinx_zynq: Split xilinx_zynq into header and implementation files Date: Thu, 4 Dec 2025 10:34:59 +0100 Message-ID: <20251204093502.50582-13-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840987889019200 Content-Type: text/plain; charset="utf-8" From: YannickV Create xilinx_zynq.h header file to expose ZynqMachineState and related definitions for machine inheritance. This enables creation of derived machines based on the Zynq platform. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 13 +------------ include/hw/arm/xilinx_zynq.h | 36 ++++++++++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 12 deletions(-) create mode 100644 include/hw/arm/xilinx_zynq.h diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index c03ed09a67..4d095ab6f3 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -41,9 +41,7 @@ #include "exec/tswap.h" #include "target/arm/cpu-qom.h" #include "qapi/visitor.h" - -#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") -OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) +#include "hw/arm/xilinx_zynq.h" =20 /* board base frequency: 33.333333 MHz */ #define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) @@ -87,15 +85,6 @@ static const int dma_irqs[8] =3D { 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 0xe5801000 + (addr) =20 -#define ZYNQ_MAX_CPUS 2 - -struct ZynqMachineState { - MachineState parent; - Clock *ps_clk; - ARMCPU *cpu[ZYNQ_MAX_CPUS]; - uint8_t boot_mode; -}; - static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h new file mode 100644 index 0000000000..ec80441e7c --- /dev/null +++ b/include/hw/arm/xilinx_zynq.h @@ -0,0 +1,36 @@ +/* + * Xilinx Zynq Baseboard System emulation. + * + * Copyright (c) 2010 Xilinx. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.= com) + * Copyright (c) 2012 Petalogix Pty Ltd. + * Written by Haibing Ma + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef QEMU_ARM_ZYNQ_H +#define QEMU_ARM_ZYNQ_H + +#include "target/arm/cpu-qom.h" +#include "hw/qdev-clock.h" + +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") +OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) + +#define ZYNQ_MAX_CPUS 2 + +struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; + ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; +}; + +#endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764840986; cv=none; d=zohomail.com; s=zohoarc; b=GOQbkArBic/XRYedtvNH3KWgMBg5bVfAm9E2Y75+8eLuARWw12PESe42jhjeWrjrR28SF9idQppuo2UrmRwqulR4gtIrAhBRbZGhl+X3dEN8LMZXlae1wt4VcNYwGJwHZK2B1O7okP1OB+8k0ZDSKR+BKpiq56mqaXl73unG69Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764840986; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QoHTI8fj0k9cPGTzgILaiqPxxBchjhp4wkj4lGHM5cM=; b=GPxtmvwikobEy3XQNlDAtfcL/4gl+ZifCas/0heBrmtc2YbBSkQVH1ridVsU3XvrvbBSxJvfmElqmRIM1G9Smi3UHucZUwk+3DJSM8Cz6fcRHUlhF2bxzJnLTViBYdSdseUhFYGBkY1DY8mQDscdmSsdvbn/n8CNDzf+VunH5ZY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764840986416230.51678635918313; Thu, 4 Dec 2025 01:36:26 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5ka-0001ZA-Tv; Thu, 04 Dec 2025 04:35:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5kC-0001ES-QI for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:26 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k8-0003Td-Aw for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:24 -0500 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-b7277324204so112333466b.0 for ; Thu, 04 Dec 2025 01:35:19 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840918; x=1765445718; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QoHTI8fj0k9cPGTzgILaiqPxxBchjhp4wkj4lGHM5cM=; b=YBXm9lSzS3F5Im/VMvx5ySqhZlR+4H07TYEBT3Em52FS9NR0QUrSOyJSm/pLbdWnzK HZZLmaleAj10MhVwBkCQgaFUvq/O3n2x2bt5kZFcoS4pHfkiFAIQvGFFe/3QBlTTVZYZ ml6TaFwUzvkUmsv7mgBWrD0p2fH+7DmG9AIPR8Ehk559y25UR2jKI/wHX16UyHIxvIQn LuQcf/eBncwVe4kCpMpBt8iSt5rdJxVG7Hj7gxoYMDSErsgzsw8IyIm2Pd3LAty/2pLX k6hjhmtvT3XwVDViSti4P4cAdo5lO0bPygBqx0pFiIUHGqo/TnF9jjcovcE9RRRvlUqT 6JyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840918; x=1765445718; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=QoHTI8fj0k9cPGTzgILaiqPxxBchjhp4wkj4lGHM5cM=; b=SrEY1JLm31m0plAwWxNsFWjLqwlWKO2ePUlorpWMXmlQ7ER0BkpPH0u9rG2EtzMgJG Ew6MG2u5DUtB5MQLFF94xmpL7WLq47b22xtHJbBr1fTVYxyYf7lAaIQGkzIxEIiPtdh5 nqA1KIkHXBXxhCGYXa5XrvJoWHKge9pHNPq5TrlEUZQ8XePsF9A6pZ+Wg4lCWLl5R5IE q0c+s4ud0+Y7QKuJ08ZHw9m7G+qZVg2YJKZNXi3bwXroKR+RnrG1imi1xaJnc25uSRCt gEEMyFhxVx3G7UCWOoAzSALHTuUSx4an2nlm8P5rjmJenl77mg/LuTcFSVrtE69Qy7QD CyIA== X-Gm-Message-State: AOJu0YwQAErWCM7XfJWJkj2v876KU31fME3qUiaKWSmGOPwj1ZrISqBI wU7lmwN2YcFyIisEo/xd9hOWuIdaX8itLosw3GQ41WcTBRm0ti9L++EDebji+Nlf X-Gm-Gg: ASbGncubMW0U+BzuxKSPl7VUognF6w8kdZdFYxIfv+4qQn1MATrk88WbeKJhtRuI4m2 gJulYK6LBz6uFdt+O82gi8tFDSDEXzoCMOglnbMf4niQlt272vEwdaKCuW8XgQviXaUINCgEtlq UAS7pNjyCVeDFE9QM9Jqs2kY/CEpO6+b5wdP0bDJ6zNzliBNFbVvQDUa+54XftZ+xuXjcUlUfVo XmjMZLA4XRQiYvvC2xz9E/ga9MIW2RVUqa2svVQd8b9Z/4SuV4BzW1JJbGgavjngdSz06Nkl9lS YOBD3tD9kUhbp2RiiaQtR4Z1m1YTgZKwLGVDTPU6hMPLhGUc8qRWPvuNc2CLwxX59hHuv7liOrT 8u7sbxY/RhCnCmsrdSx3jf+sdG2tU8+odl/wiY4JQfBDHVXUZIrNSyV6AO3hONI5ukbXvX6zrV8 nKIcx39l5UitPFEOO0tPWlh50hIVjt9Jk= X-Google-Smtp-Source: AGHT+IF8bDJxFdN26MzH3XnStPbW3ikTtYQS1+34s0dsLKh9rON8ms9vpkvUg6MGsWBeD5DUK5V5Kw== X-Received: by 2002:a17:906:478d:b0:b73:58a0:e064 with SMTP id a640c23a62f3a-b79ec6ce11amr218281866b.50.1764840918171; Thu, 04 Dec 2025 01:35:18 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 13/15] hw/arm/xilinx_zynq: Add flash-type property Date: Thu, 4 Dec 2025 10:35:00 +0100 Message-ID: <20251204093502.50582-14-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764840987772019200 Content-Type: text/plain; charset="utf-8" From: YannickV Read flash-type value as machine property and set the flash type accordingly. Signed-off-by: YannickV --- hw/arm/xilinx_zynq.c | 25 ++++++++++++++++++++----- include/hw/arm/xilinx_zynq.h | 1 + 2 files changed, 21 insertions(+), 5 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 4d095ab6f3..db4fac17c8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -120,7 +120,8 @@ static void gem_init(uint32_t base, qemu_irq irq) } =20 static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi, int unit0) + bool is_qspi, int unit0, + const char *flash_type) { int unit =3D unit0; DeviceState *dev; @@ -152,7 +153,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_a= ddr, qemu_irq irq, =20 for (j =3D 0; j < num_ss; ++j) { DriveInfo *dinfo =3D drive_get(IF_MTD, 0, unit++); - flash_dev =3D qdev_new("n25q128"); + flash_dev =3D qdev_new(flash_type); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -190,6 +191,14 @@ static void zynq_set_boot_mode(Object *obj, const char= *str, m->boot_mode =3D mode; } =20 +static void zynq_set_flash_type(Object *obj, const char *str, + Error **errp) +{ + ZynqMachineState *m =3D ZYNQ_MACHINE(obj); + g_free(m->flash_type); + m->flash_type =3D g_strdup(str); +} + static void ddr_ctrl_init(uint32_t base) { DeviceState *dev; @@ -283,9 +292,12 @@ static void zynq_init(MachineState *machine) pic[n] =3D qdev_get_gpio_in(dev, n); } =20 - n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0); - n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n); - n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n); + n =3D zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false,= 0, + zynq_machine->flash_type); + n =3D zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false,= n, + zynq_machine->flash_type); + n =3D zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, = n, + zynq_machine->flash_type); =20 sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]= ); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]= ); @@ -473,6 +485,9 @@ static void zynq_machine_class_init(ObjectClass *oc, co= nst void *data) "Supported boot modes:" " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); + + prop =3D object_class_property_add_str(oc, "flash-type", NULL, zynq_se= t_flash_type); + object_property_set_default_str(prop, "n25q128"); } =20 static const TypeInfo zynq_machine_type =3D { diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index ec80441e7c..7379fe3988 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -31,6 +31,7 @@ struct ZynqMachineState { Clock *ps_clk; ARMCPU *cpu[ZYNQ_MAX_CPUS]; uint8_t boot_mode; + char *flash_type; }; =20 #endif /* QEMU_ARM_ZYNQ_H */ --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841030; cv=none; d=zohomail.com; s=zohoarc; b=oGaqow+/RYEAurqYdK1bKyZRUgrOOj1iphmu5TE3HjAxzzxTVmSEFhrPq66roe9GhHsMl8E6cIjazvDAjX+6j5lfT071FHWrqBRjFGwPpXtXYkr0E+RfpGLGEv79DS4la0TtflYu7wbDT2WcsP8QOBY9KSRh7AnNNdB1DnJnALs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841030; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=SjUoPuVHOv7yCQYn+9czDBAPb7tQCMl2Bj+611ltDLg=; b=L1XHBwZWhNpfGRZhtSOMNMzBTrQSKPCyQ9HoGj7w7LO51SWfufU+cJqFgf47OBXMHWMF1JtD/lw+M6u0nrn7zg02mJ1yZ5htO3nbfUZ+hGRVsHra3r4yLN8lcfxMSD8FmsN7Qo1CMyZ2yP1PDp/P+AWkQwiXdGP2joQ84926k+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841029993789.9142704742327; Thu, 4 Dec 2025 01:37:09 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kp-0001uR-Jg; Thu, 04 Dec 2025 04:36:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5kE-0001Fl-Nl for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:28 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5k9-0003UD-Rx for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:25 -0500 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-b73545723ebso112059266b.1 for ; Thu, 04 Dec 2025 01:35:21 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840919; x=1765445719; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SjUoPuVHOv7yCQYn+9czDBAPb7tQCMl2Bj+611ltDLg=; b=kU9P2Z/edxk4/y4mLDReE6yLxmD+E9qOAUbwPXuEIqD8W3DURnEn1Gs7bk/RkmZc48 xu0nBEWKVcdBqFd18xPfz12t64vQD3YQcvwyQx84UTRBwyq65lRzHOsPDVj2qtJ9XlfS 4xMjASw+2L6YB3h2nXk+M4YjoUifWqoUBqAMMavVxFFngbKskQQHBfKADvLqgTKkDEU/ SzVh/9YFIZqvND76z1kP2vaTgGAF3IbVd7dbDIy/w2XZ1qWO74VOceLr7F3AR1bTL4pu GVtRBl6GPfPO9QFBFi2Q8Zp1BbP20dOPeTEURUB+U9hd2K1nEX4dTZw6GWoo9UF1hIJp r3xA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840919; x=1765445719; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=SjUoPuVHOv7yCQYn+9czDBAPb7tQCMl2Bj+611ltDLg=; b=LQuDd+GhBQc8k2MycpYGEbramalyXJYwV3dGNvdBvxERdRR9NVj6evpzddC7hyMQ74 D/YMQ2CdG3GygEAdNYxZtz7HOVMxfkOicUrclPkFxkTwtTbMIP2Yqmp3CgX1/8jwhoFW ihsUHDcfDVTsYWCp2LIJrTB2GTBhY9Lhz61gUR3adxjnhhgQKKg5j+MrhsWuyTsRf04r Q3L5NuCuV2PdrYUzRFPnqVRsO8f9w9wXk2DkXLoWMhGWpAZzs2DsOcLKForkMx2n62in uqOop3hMOAcCRPy7pTKaDoyOt94s3ufzJnkh135m9KD/h7AZhwJ3TBglBDaNoNuYWxfU Kqvg== X-Gm-Message-State: AOJu0YwUU5OCZEVSEJ0Klin5DE1xT9IJZpgLIqNlta0ucL8OJUSeRZaN W+jcq+zgfOzZTi9KZvTaGajUxGn4SnqAeqDq4FxNiujq5mkBHO1scB+NV8nf5hef X-Gm-Gg: ASbGncvTmvys4n/+OX+H2krLMn1gu4kFmOpmnMk9a5PgqdlpNd24pzaGKGwVG78Xtpn hOZevRLzeqTPw49seq7blrMFSbipUjUe/lj1z7frjUopzy4whYO7DShspSt9Nc/LZYg96A0FLCz HNT4mA49Xy90q6plcKK/w8/ZSBB1p7OTwQzz0Y4AZo6O3IFu/IzwF1EkLMDH6LIAGfQ6jKBY76S eJQfDtdxIvz5tf68XZH2alOJ9V7qdZXKU1pe/13ou2UvPqg4arG5GmIb7dayz87dKfNPG0/JpZy x3vFkA3HTKLI0BMDqGZqYsvxbE2gK3dL8dcx7tmqUw0s4EB2500JySrlLZ0akAo1+YEXrCcvFNN oQwLSFpnCPiXwDmKKcex3kotPWJ53xFrT4/7GOwytpyX8xdcqLH2S9e39elWmxwF86bLYGINlvF MEmpLaT6Fy43k+zfZtLrNmlRqQACQqeeU= X-Google-Smtp-Source: AGHT+IGhuE58R6Jfkf4F52pxLW1PeusGbMrej8Q4EsRTWnj5XnVcgmkRN6VHznSzldgIth5WHoRfqw== X-Received: by 2002:a17:907:1b1e:b0:b6d:5f52:eee8 with SMTP id a640c23a62f3a-b79dc520f60mr567068566b.29.1764840919274; Thu, 04 Dec 2025 01:35:19 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 14/15] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Date: Thu, 4 Dec 2025 10:35:01 +0100 Message-ID: <20251204093502.50582-15-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841032099019200 Content-Type: text/plain; charset="utf-8" From: YannickV Introduce a new machine type 'beckhoff-cx7200' that inherits from the xilinx-zynq-a9 machine. The CX7200 is an industrial PC based on the Xilinx Zynq-7000 SoC. The machine preserves all standard Zynq features (boot-mode selection, SPI, UART, Ethernet, etc.) while adding CX7200-specific hardware components. Signed-off-by: YannickV --- hw/arm/Kconfig | 7 +++ hw/arm/beckhoff_CX7200.c | 104 +++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 112 insertions(+) create mode 100644 hw/arm/beckhoff_CX7200.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7877506384..00810634d2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -307,6 +307,13 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG =20 +config BECKHOFF_CX7200 + bool + default y + depends on TCG && ARM + select ZYNQ + select BECKHOFF_CCAT + config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c new file mode 100644 index 0000000000..85e2fd0fd6 --- /dev/null +++ b/hw/arm/beckhoff_CX7200.c @@ -0,0 +1,104 @@ + +/* + * Modified Xilinx Zynq Baseboard System emulation for Beckhoff CX7200. + * + * Copyright (c) 2024 Beckhoff Automation GmbH & Co. KG + * + * Based on /hw/arm/xilinx_zynq.c: + * Copyright (c) 2010 Xilinx. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.= com) + * Copyright (c) 2012 Petalogix Pty Ltd. + * Original code by Haibing Ma. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/block/block.h" +#include "hw/loader.h" +#include "qemu/error-report.h" +#include "hw/arm/xilinx_zynq.h" /* For ZynqMachineState */ +#include "hw/cpu/a9mpcore.h" +#include "qom/object.h" + +#define TYPE_CX7200_MACHINE MACHINE_TYPE_NAME("beckhoff-cx7200") + +#define CX7200_PERIPHCLK_DIVIDER 2 +#define CX7200_PS7_CPU_CLK_FREQUENCY 720000000 + +static void ccat_init(uint32_t base, BlockBackend *eeprom_blk) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("beckhoff-ccat"); + if (eeprom_blk) { + qdev_prop_set_drive_err(dev, "eeprom", eeprom_blk, &error_fatal); + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + +static void beckhoff_cx7200_init(MachineState *machine) +{ + DriveInfo *di; + BlockBackend *blk; + MachineClass *parent_mc; + DeviceState *a9mpcore_dev; + A9MPPrivState *a9mp_priv_state; + + object_property_set_str(OBJECT(machine), "flash-type", "is25lp016d", + &error_fatal); + + parent_mc =3D MACHINE_CLASS(object_class_get_parent( + object_get_class(OBJECT(machine)))); + parent_mc->init(machine); + + /* Find A9MPCore and set timer frequencies directly */ + a9mpcore_dev =3D DEVICE(object_resolve_path_type("", TYPE_A9MPCORE_PRI= V, + NULL)); + if (a9mpcore_dev) { + a9mp_priv_state =3D A9MPCORE_PRIV(a9mpcore_dev); + + /* Direct struct access - devices are already realized */ + a9mp_priv_state->gtimer.freq_hz =3D CX7200_PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->gtimer.periphclk_divider =3D CX7200_PERIPHCLK_DIV= IDER; + a9mp_priv_state->mptimer.freq_hz =3D CX7200_PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->mptimer.periphclk_divider =3D CX7200_PERIPHCLK_DI= VIDER; + a9mp_priv_state->wdt.freq_hz =3D CX7200_PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->wdt.periphclk_divider =3D CX7200_PERIPHCLK_DIVIDE= R; + } else { + error_setg(&error_fatal, "Could not find A9MPCore device " + "for CX7200 timer configuration"); + } + + di =3D drive_get(IF_NONE, 0, 0); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + ccat_init(0x40000000, blk); +} + +static void beckhoff_cx7200_machine_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Beckhoff CX7200 Industrial PC (Zynq-based)"; + mc->init =3D beckhoff_cx7200_init; +} + +static const TypeInfo beckhoff_cx7200_machine_type =3D { + .name =3D TYPE_CX7200_MACHINE, + .parent =3D TYPE_ZYNQ_MACHINE, + .class_init =3D beckhoff_cx7200_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void beckhoff_cx7200_machine_register_types(void) +{ + type_register_static(&beckhoff_cx7200_machine_type); +} + +type_init(beckhoff_cx7200_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index aeaf654790..4ea5d2648c 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -2,6 +2,7 @@ arm_ss =3D ss.source_set() arm_common_ss =3D ss.source_set() arm_common_ss.add(when: 'CONFIG_ARM_VIRT', if_true: files('virt.c')) arm_common_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) +arm_common_ss.add(when: 'CONFIG_BECKHOFF_CX7200', if_true: files('beckhoff= _CX7200.c')) arm_common_ss.add(when: 'CONFIG_DIGIC', if_true: files('digic_boards.c')) arm_common_ss.add(when: 'CONFIG_EMCRAFT_SF2', if_true: files('msf2-som.c')) arm_common_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) --=20 2.47.3 From nobody Sun Dec 14 06:36:37 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1764841168; cv=none; d=zohomail.com; s=zohoarc; b=lE5KpOq9Qnha95g46nisd09rgrvs0UGjUn8yytk+dN9lGcpkfyAlzaUX5IgnulhXup1AHPTK2w5qK10YYAPoDiWb2JiGTjseIJQsEdTQtifoQhBHRHknaOv+XodjETJai+qsQiHVXpNrJp75wJ+DE+PsLDObR7R0p4/jI6Qd4Os= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764841168; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Z3TwBBdLUHAKhGiv26iGeP2UfTRRDnunnjZgIo/sg9k=; b=fPfNGbY+vS/8oyT9WV5v0wcSiTYTy7zBDZd38dAr5AxRRyNS+DmWZFgwNkhFB1kIf+RZJYzT7Uvqdkqq2FvbsqlV3NV837u5zRvpIIKFnmAN/CyxjqUPWVJDgfh5vzeILbfvNMvNKAIzFaROA7b4bg92z6XcIXiA+Tr5XP8QpFc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764841168970192.61764599649803; Thu, 4 Dec 2025 01:39:28 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vR5kr-00021I-MA; Thu, 04 Dec 2025 04:36:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vR5kE-0001Fi-ON for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:28 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vR5kA-0003Uy-K4 for qemu-devel@nongnu.org; Thu, 04 Dec 2025 04:35:26 -0500 Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-6408f9cb1dcso1037864a12.3 for ; Thu, 04 Dec 2025 01:35:21 -0800 (PST) Received: from PC-DA2D10.beckhoff.com ([195.226.174.194]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-647b2edf72asm856573a12.11.2025.12.04.01.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 04 Dec 2025 01:35:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1764840920; x=1765445720; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z3TwBBdLUHAKhGiv26iGeP2UfTRRDnunnjZgIo/sg9k=; b=NyBNLpMn/c8E5XJkmPOZ4O+1b6aNn0sLj4Ub5c2qRxVD2QUI8ekdwHVxkSRQ53nM6w XX/QqJUYd9nFt76bASE8D1NwfPPcsIiPWCmzlcZzQ64RyBOWYDaEh5gAt3wiWpDmxfFF gYloJMVGPyX0f8C5/2SrhuAXoKdpWX2w9fpPzeSFTJTUJUaFj5oGAYqZwWd743o5KJ0s WBY8Wk3q4u4QjKgvqzIoGUSGKTpxWzOMCkRNLcKf+60E6VvaNXkZw7IH9lGR0MjANwuW shweUmbeiDr8MB825BFUwtoEO+lU7mQgoY3+JbvpGkInDPAQSLgglhBGd1HFaMjqlnDO vckQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764840920; x=1765445720; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=Z3TwBBdLUHAKhGiv26iGeP2UfTRRDnunnjZgIo/sg9k=; b=mwZYEHsmkpiD5tniJRwV46ahVU3TLdxp/SwMxzcizh7eJYBv8bL+jNAwf9G8k4SF+Y dMwsNHBU86LnZB5y6TW073572msTs+1o7VJdx2qd1yEEVPaLMLKuVcMznXUI1hO7cPlm cwFhV/GZpMqYUswMBejKA+oPy8xTachvei0d/joJZRk5tSCrfOkeSab9sFKx677lfC/p CaaRwGKxqGRexkgtCfBJx2n6wGzKr958z1M7a2ajk+sb19Tb0sIWE9Fy6olp89yYVSq5 mT1ggAviDtUObc57dvaF5AfCFVv7KNp+MMcu5q8J/w6es/qFt0qPs7CdRyNct/1n/9xu /WEg== X-Gm-Message-State: AOJu0Yzd17z06B2g7hO+9en/U9dP/RaoC7DDxvqfCWEjn0W+pOL/TmwQ /Ns2gMfFLx49utyKghVkgvupaaIFQhZHDpltqBWm9kL0QMuCqMqSPfiFeuDhIVlO X-Gm-Gg: ASbGnct5spPwksVRi6WrL9sVzoKplJBz5Sm9crp5UIYYbZkXRrw9VCKIihx75i7VS+W W+G7dGd0GGoWp17U4B0s7RLtIP2NaNbwXborIf/AHs6J5WH5Fn0uWRAnGNxPiRUCduoKX9q3m5u a5VhnhAHzPYOc3Lp4zAoX+/FPULH3q1/jIlAVfBvWylPXu8e9WPowxiHaMCVIJv/xsS2tO8bNFb nAOpi/dsrR0UWaZrYn4o8pu10K/4xSpsiVf6dDPoqJmStWBL04rczWYv3jHMusrSktPeixzYkys JNr6lemFkOjKSutJaKSmij85+kHR8Nnh73xNRdUuOf3l9BaMW9ZHZZuq7V28AORZgAz6LCG+xey 5dfaTvheEjAdK43Woayvc6tQ3jE8jPDeW92AKVqLNmUOm/bokxde0QaCnguHhO4guS3EN2KFjm1 SDTZnUr1lYDACy6UplEfV+ISxyjC0n6so= X-Google-Smtp-Source: AGHT+IFUbH+VuW2Dbg3FCQP2dHb9srcTkmh0WK3swKkSr4kJHoyBHQH0LztS0gY+Yj1ieeB8bpXmkA== X-Received: by 2002:a05:6402:27d0:b0:640:c643:75dd with SMTP id 4fb4d7f45d1cf-647abd98f99mr1960795a12.12.1764840920370; Thu, 04 Dec 2025 01:35:20 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, Peter Maydell , Kevin Wolf , qemu-block@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Hanna Reitz , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , YannickV Subject: [PATCH v5 15/15] docs/system/arm: Add support for Beckhoff CX7200 Date: Thu, 4 Dec 2025 10:35:02 +0100 Message-ID: <20251204093502.50582-16-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251204093502.50582-1-corvin.koehne@gmail.com> References: <20251204093502.50582-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1764841169177019200 Content-Type: text/plain; charset="utf-8" From: YannickV This commit offers some documentation on the Beckhoff CX7200 qemu emulation. Signed-off-by: YannickV --- docs/system/arm/beckhoff-cx7200.rst | 57 +++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 58 insertions(+) create mode 100644 docs/system/arm/beckhoff-cx7200.rst diff --git a/docs/system/arm/beckhoff-cx7200.rst b/docs/system/arm/beckhoff= -cx7200.rst new file mode 100644 index 0000000000..f060319b0f --- /dev/null +++ b/docs/system/arm/beckhoff-cx7200.rst @@ -0,0 +1,57 @@ +Beckhoff CX7200 (``beckhoff-cx7200``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Beckhoff CX7200 is based on the same architecture as the Xilinx Zynq A= 9. +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. +The Beckhoff Communication Controller (CCAT) can be found in the PL of Zyn= q. + +More details here: +https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technic= al-Reference-Manual +https://www.beckhoff.com/de-de/produkte/ipc/embedded-pcs/cx7000-arm-r-cort= ex-r/cx7293.html + +The CX7200 supports following devices: + - A9 MPCORE + - cortex-a9 + - GIC v1 + - Generic timer + - wdt + - OCM 256KB + - SMC SRAM@0xe2000000 64MB + - Zynq SLCR + - SPI x2 + - QSPI + - UART + - TTC x2 + - Gigabit Ethernet Controller + - SD Controller + - XADC + - Arm PrimeCell DMA Controller + - DDR Memory + - DDR Controller + - Beckhoff Communication Controller (CCAT) + - EEPROM Interface + - DMA Controller + +Following devices are not supported: + - I2C + +Running +""""""" +Directly loading an ELF file to the CPU of the CX7200 to run f.e. TC/RTOS = (based on FreeRTOS): + +.. code-block:: bash + + $ qemu-system-arm -M beckhoff-cx7200 \ + -device loader,file=3DCX7200_Zynq_Fsbl.elf \ + -display none \ + -icount shift=3Dauto \ + + +For setting the EEPROM content of the CCAT provide the following on the co= mmand line: + +.. code-block:: bash + + -drive file=3Deeprom.bin,format=3Draw,id=3Dccat-eeprom + +The size of eeprom.bin must be aligned to a power of 2 and bigger than 256= bytes. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index a96d1867df..e634872b97 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -82,6 +82,7 @@ Board-specific documentation arm/aspeed arm/bananapi_m2u.rst arm/b-l475e-iot01a.rst + arm/beckhoff-cx7200 arm/sabrelite arm/highbank arm/digic --=20 2.47.3