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Tsirkin" , Marcel Apfelbaum Cc: Igor Mammedov , qemu-devel@nongnu.org, Andrey Ryabinin , qemu-stable@nongnu.org Subject: [PATCH] q35: Fix migration of SMRAM state Date: Wed, 3 Dec 2025 19:08:51 +0100 Message-ID: <20251203180851.6390-1-arbn@yandex-team.com> X-Mailer: git-send-email 2.51.2 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=178.154.239.72; envelope-from=arbn@yandex-team.com; helo=forwardcorp1a.mail.yandex.net X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex-team.com) X-ZM-MESSAGEID: 1764785452882019200 mch_update_smbase_smram() essentially uses wmask[MCH_HOST_BRIDGE_F_SMBASE] to track SMBASE area state. Since 'wmask' state is not migrated is not migrated, the destination QEMU always sees wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D=3D 0xff As a result, when mch_update() calls mch_update_smbase_smram() on the destination, it resets ->config[MCH_HOST_BRIDGE_F_SMBASE] and disables the smbase-window memory region=E2=80=94even if it was enabled on the sourc= e. 'info mtree' on source: address-space: KVM-SMRAM 0000000000000000-ffffffffffffffff (prio 0, i/o): mem-container-smram 0000000000000000-00000000ffffffff (prio 10, i/o): smram 0000000000030000-000000000004ffff (prio 0, i/o): alias smbase-windo= w @pc.ram 00000000000a0000-00000000000bffff (prio 0, i/o): alias smram-low @p= c.ram 000000007f000000-000000007fffffff (prio 0, i/o): alias tseg-window = @pc.ram 0000000000000000-ffffffffffffffff (prio 0, i/o): alias mem-smram @sys= tem 'info mtree' on dest after migration: address-space: KVM-SMRAM 0000000000000000-ffffffffffffffff (prio 0, i/o): mem-container-smram 0000000000000000-00000000ffffffff (prio 10, i/o): smram 00000000000a0000-00000000000bffff (prio 0, i/o): alias smram-low @p= c.ram 000000007f000000-000000007fffffff (prio 0, i/o): alias tseg-window = @pc.ram 0000000000000000-ffffffffffffffff (prio 0, i/o): alias mem-smram @sys= tem This mismatch in memory regions breaks CPR-transfer migration with VFIO: the DMA mappings sent via VFIO_IOMMU_MAP_DMA on the destination must match the source. Otherwise, the destination QEMU aborts: qemu: vfio_container_dma_map(0x..., 0x0, 0xa0000, 0x....) =3D -22 (Inva= lid argument) qemu: hardware error: vfio: DMA mapping failed, unable to continue According to mch_update_smbase_smram() the valid combinations of ->config and ->wmask for MCH_HOST_BRIDGE_F_SMBASE are: 1) ->config[] =3D=3D 0x0 && ->wmask[] =3D=3D 0xff 2) ->config[] =3D=3D MCH_HOST_BRIDGE_F_SMBASE_IN_RAM && ->wmask[] =3D=3D MCH_HOST_BRIDGE_F_SMBASE_LCK 3) ->config[] =3D=3D MCH_HOST_BRIDGE_F_SMBASE_LCK && ->wmask[] =3D=3D 0 Add mch_smbase_smram_post_load() to restore ->wmask of MCH_HOST_BRIDGE_F_SMBASE based on ->config[] value, ensuring that the follow-up call to mch_update_smbase_smram() correctly reinstates the smbase-window region if it was enabled on the source. Cc: qemu-stable@nongnu.org Fixes: f404220e279c ("q35: implement 128K SMRAM at default SMBASE address") Signed-off-by: Andrey Ryabinin --- hw/pci-host/q35.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index a708758d36..2466a1aded 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -517,9 +517,27 @@ static void mch_update(MCHPCIState *mch) IO_APIC_DEFAULT_ADDRESS - 1); } =20 +static void mch_smbase_smram_post_load(MCHPCIState *mch) +{ + PCIDevice *pd =3D PCI_DEVICE(mch); + uint8_t *reg =3D pd->config + MCH_HOST_BRIDGE_F_SMBASE; + + if (!mch->has_smram_at_smbase) { + return; + } + + if (*reg =3D=3D MCH_HOST_BRIDGE_F_SMBASE_IN_RAM) { + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D + MCH_HOST_BRIDGE_F_SMBASE_LCK; + } else if (*reg =3D=3D MCH_HOST_BRIDGE_F_SMBASE_LCK) { + pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] =3D 0; + } +} static int mch_post_load(void *opaque, int version_id) { MCHPCIState *mch =3D opaque; + + mch_smbase_smram_post_load(mch); mch_update(mch); return 0; } --=20 2.51.2