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Hi; here's an arm pullreq for whichever rc we're up to now :-) One easy bugfix for an assertion, and one docs-only change to update a URL. thanks -- PMM The following changes since commit 9ef49528b5286f078061b52ac41e0ca19fa10e36: Merge tag 'hw-misc-20251125' of https://github.com/philmd/qemu into staging (2025-11-25 14:22:39 -0800) are available in the Git repository at: https://gitlab.com/pm215/qemu.git tags/pull-target-arm-20251201 for you to fetch changes up to ebb625262c7f9837d6c7b9d8a0c1349fe8a8f4ff: docs/devel: Update URL for make-pullreq script (2025-12-01 09:39:46 +0000) ---------------------------------------------------------------- target-arm queue: * fix assertion in translation of BRA * update soon-to-break URL in docs ---------------------------------------------------------------- Harald van Dijk (1): target/arm: Fix assert on BRA. Peter Maydell (1): docs/devel: Update URL for make-pullreq script docs/devel/submitting-a-pull-request.rst | 2 +- target/arm/tcg/translate-a64.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)
From: Harald van Dijk <hdijk@accesssoftek.com> trans_BRA does gen_a64_set_pc(s, dst); set_btype_for_br(s, a->rn); gen_a64_set_pc does s->pc_save = -1; set_btype_for_br (if aa64_bti is enabled and the register is not x16 or x17) does gen_pc_plus_diff(s, pc, 0); gen_pc_plus_diff does assert(s->pc_save != -1); Hence, this assert is getting hit. We need to call set_btype_for_br before gen_a64_set_pc, and there is nothing in set_btype_for_br that depends on gen_a64_set_pc having already been called, so this commit simply swaps the calls. (The commit message for 64678fc45d8f6 says that set_brtype_for_br() must be "moved after" get_a64_set_pc(), but this is a mistake in the commit message -- the actual changes in that commit move set_brtype_for_br() *before* get_a64_set_pc() and this is necessary to avoid the assert.) Cc: qemu-stable@nongnu.org Fixes: 64678fc45d8f6 ("target/arm: Fix BTI versus CF_PCREL") Signed-off-by: Harald van Dijk <hdijk@accesssoftek.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: d2265ebb-84bc-41b7-a2d7-05dc9a5a2055@accesssoftek.com [PMM: added note about 64678fc45d8f6 to commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/tcg/translate-a64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index XXXXXXX..XXXXXXX 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -XXX,XX +XXX,XX @@ static bool trans_BRA(DisasContext *s, arg_bra *a) return false; } dst = auth_branch_target(s, cpu_reg(s,a->rn), cpu_reg_sp(s, a->rm), !a->m); - gen_a64_set_pc(s, dst); set_btype_for_br(s, a->rn); + gen_a64_set_pc(s, dst); s->base.is_jmp = DISAS_JUMP; return true; } -- 2.43.0
In the submitting-a-pull-request docs, we have a link to the make-pullreq script which might be useful for maintainers. The canonical git repo for this script has moved; update the link. Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20251125164511.255550-1-peter.maydell@linaro.org --- docs/devel/submitting-a-pull-request.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/devel/submitting-a-pull-request.rst b/docs/devel/submitting-a-pull-request.rst index XXXXXXX..XXXXXXX 100644 --- a/docs/devel/submitting-a-pull-request.rst +++ b/docs/devel/submitting-a-pull-request.rst @@ -XXX,XX +XXX,XX @@ subject tag is "PULL SUBSYSTEM s390/block/whatever" rather than just pull requests that should be applied to master. You might be interested in the `make-pullreq -<https://git.linaro.org/people/peter.maydell/misc-scripts.git/tree/make-pullreq>`__ +<https://gitlab.com/pm215/misc-scripts/-/blob/master/make-pullreq>`__ script which automates some of this process for you and includes a few sanity checks. Note that you must edit it to configure it suitably for your local situation! -- 2.43.0
v3->v4: Windows headers define an INT type which clashed with an enum value name in arm_gicv3_its.c... The following changes since commit eae587e8e3694b1aceab23239493fb4c7e1a80f5: Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-09-13' into staging (2021-09-13 11:00:30 +0100) are available in the Git repository at: https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210913-3 for you to fetch changes up to 28e987a7e7edaa3ca7feeac65edca26145df8814: hw/arm/mps2.c: Mark internal-only I2C buses as 'full' (2021-09-13 21:01:08 +0100) ---------------------------------------------------------------- target-arm queue: * mark MPS2/MPS3 board-internal i2c buses as 'full' so that command line user-created devices are not plugged into them * Take an exception if PSTATE.IL is set * Support an emulated ITS in the virt board * Add support for kudo-bmc board * Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM * cadence_uart: Fix clock handling issues that prevented u-boot from running ---------------------------------------------------------------- Bin Meng (6): hw/misc: zynq_slcr: Correctly compute output clocks in the reset exit phase hw/char: cadence_uart: Disable transmit when input clock is disabled hw/char: cadence_uart: Move clock/reset check to uart_can_receive() hw/char: cadence_uart: Convert to memop_with_attrs() ops hw/char: cadence_uart: Ignore access when unclocked or in reset for uart_{read, write}() hw/char: cadence_uart: Log a guest error when device is unclocked or in reset Chris Rauer (1): hw/arm: Add support for kudo-bmc board. Marc Zyngier (1): hw/arm/virt: KVM: Probe for KVM_CAP_ARM_VM_IPA_SIZE when creating scratch VM Peter Maydell (5): target/arm: Take an exception if PSTATE.IL is set qdev: Support marking individual buses as 'full' hw/arm/mps2-tz.c: Add extra data parameter to MakeDevFn hw/arm/mps2-tz.c: Mark internal-only I2C buses as 'full' hw/arm/mps2.c: Mark internal-only I2C buses as 'full' Richard Henderson (1): target/arm: Merge disas_a64_insn into aarch64_tr_translate_insn Shashi Mallela (9): hw/intc: GICv3 ITS initial framework hw/intc: GICv3 ITS register definitions added hw/intc: GICv3 ITS command queue framework hw/intc: GICv3 ITS Command processing hw/intc: GICv3 ITS Feature enablement hw/intc: GICv3 redistributor ITS processing tests/data/acpi/virt: Add IORT files for ITS hw/arm/virt: add ITS support in virt GIC tests/data/acpi/virt: Update IORT files for ITS docs/system/arm/nuvoton.rst | 1 + hw/intc/gicv3_internal.h | 188 ++++- include/hw/arm/virt.h | 2 + include/hw/intc/arm_gicv3_common.h | 13 + include/hw/intc/arm_gicv3_its_common.h | 32 +- include/hw/qdev-core.h | 24 + target/arm/cpu.h | 1 + target/arm/kvm_arm.h | 4 +- target/arm/syndrome.h | 5 + target/arm/translate.h | 2 + hw/arm/mps2-tz.c | 92 ++- hw/arm/mps2.c | 12 +- hw/arm/npcm7xx_boards.c | 34 + hw/arm/virt.c | 29 +- hw/char/cadence_uart.c | 61 +- hw/intc/arm_gicv3.c | 14 + hw/intc/arm_gicv3_common.c | 13 + hw/intc/arm_gicv3_cpuif.c | 7 +- hw/intc/arm_gicv3_dist.c | 5 +- hw/intc/arm_gicv3_its.c | 1322 ++++++++++++++++++++++++++++++++ hw/intc/arm_gicv3_its_common.c | 7 +- hw/intc/arm_gicv3_its_kvm.c | 2 +- hw/intc/arm_gicv3_redist.c | 153 +++- hw/misc/zynq_slcr.c | 31 +- softmmu/qdev-monitor.c | 7 +- target/arm/helper-a64.c | 1 + target/arm/helper.c | 8 + target/arm/kvm.c | 7 +- target/arm/translate-a64.c | 255 +++--- target/arm/translate.c | 21 + hw/intc/meson.build | 1 + tests/data/acpi/virt/IORT | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.memhp | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.numamem | Bin 0 -> 124 bytes tests/data/acpi/virt/IORT.pxb | Bin 0 -> 124 bytes 35 files changed, 2144 insertions(+), 210 deletions(-) create mode 100644 hw/intc/arm_gicv3_its.c create mode 100644 tests/data/acpi/virt/IORT create mode 100644 tests/data/acpi/virt/IORT.memhp create mode 100644 tests/data/acpi/virt/IORT.numamem create mode 100644 tests/data/acpi/virt/IORT.pxb