From nobody Sun Dec 14 05:56:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1764553513; cv=none; d=zohomail.com; s=zohoarc; b=G9gyheH1/J370lQt/2PP0xt1jlEbTCrms5ZFoFad7uytDhgjE6XC5QmnfyEQzeVYkxnfkydtMXPbmR9lYtdm0gy78Z+0I5evZwt2d5urptNw6KRU+lxJjJ70YfT0Jvs0X+gbMkgr1fNND34g2W/nbXoSJ+Ji25BLdKWj/3Z3pUM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764553513; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=dTyAcOIy1VEQmgiXMMmWfuiTKtYFi2sZZRQxVzYk4IQ=; b=nr5wJnPCyzDqdk+ji09jkbJ2zanTdUHTUMkwWfsntm4uNn+vTOPz6sh+KrFiEgZwj5tY9ZQ6Rj+VhkAqtwZ+kYoVlVnb3Ga/pDGIzBZEaQFezegM+Rj/cnk2s0FJmBJLYyOTWE4YWLOZLMiLCIguz24Bm61FcKUK1fHO2rFDqkI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764553513807318.03931016855256; Sun, 30 Nov 2025 17:45:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vPsx9-0001iX-1n; Sun, 30 Nov 2025 20:43:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPsx3-0001ex-Tb; Sun, 30 Nov 2025 20:43:42 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPswv-0004os-O1; Sun, 30 Nov 2025 20:43:41 -0500 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5B11h2bu056810 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Dec 2025 09:43:02 +0800 (+08) (envelope-from alvinga@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 1 Dec 2025 09:43:02 +0800 To: , CC: , , , , , , Alvin Chang , Yu-Ming Chang Subject: [PATCH v3 1/2] target/riscv: Add "debug-1.0" to specify debug specification v1.0 Date: Mon, 1 Dec 2025 09:42:54 +0800 Message-ID: <20251201014255.230069-2-alvinga@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251201014255.230069-1-alvinga@andestech.com> References: <20251201014255.230069-1-alvinga@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5B11h2bu056810 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=alvinga@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alvin Chang From: Alvin Chang via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1764553517969019200 Content-Type: text/plain; charset="utf-8" Currently RISC-V CPU has a property "debug" which is equivalent to old debug specification v0.13 version. Now we have ratified debug specification v1.0 version. To support both versions, we add "debug-1.0" as one of RISC-V CPU property to let user specify that debug v0.13 or debug v1.0 is enabled. When debug-1.0=3Dfalse CPU fallbacks to default v0.13 version. Note that "debug-1.0" depends on "debug" property ("debug" is default true). Take "max" for example, the possible settings are: * -cpu max --> debug v0.13 is default enabled * -cpu max,debug=3Dfalse --> debug is disabled * -cpu max,debug-1.0=3Dtrue --> debug is enabled and the version is v1.0 Signed-off-by: Alvin Chang Reviewed-by: Yu-Ming Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 73d4280..082035b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2637,6 +2637,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rule= s[] =3D { =20 static const Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("debug-1.0", RISCVCPU, cfg.debug_1_00, false), =20 {.name =3D "pmu-mask", .info =3D &prop_pmu_mask}, {.name =3D "pmu-num", .info =3D &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_field= s.h.inc index a154ecd..402b255 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -151,6 +151,7 @@ BOOL_FIELD(ext_XVentanaCondOps) BOOL_FIELD(mmu) BOOL_FIELD(pmp) BOOL_FIELD(debug) +BOOL_FIELD(debug_1_00) BOOL_FIELD(misa_w) =20 BOOL_FIELD(short_isa_string) --=20 2.43.0 From nobody Sun Dec 14 05:56:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1764553515; cv=none; d=zohomail.com; s=zohoarc; b=gw2V3qcEtSAm2FS/rQ0U+shulq86j/m2bAiqrxR6fx6wlSpBeL3+ChGwRqmCL/CoX9qvdQw7Y+w8+iNbChwgnnLoUtq9aBRynlR6RjfKOcgGtlVoBuAtpZMu0CDX1nJkbLCrJ30nrGrVZmzAaZvnM/zZFD5jjo/6oizZrpqtsjo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764553515; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=trxrTXpSv6O8trXF9QriTmB6uHpIDi0VYwl04Tq+DnQ=; b=jnJ0tOKlecvfUVjdvPhcBLBrDMNSd78YS5t8KwDDJ2es6DgLGuLvjOOF1TflE/ARm8YCggWKdxEMDV789tWCEOF/A9KXGhgAmoLaFEvb6NV4RoVErtch8JDtJQdwYiyng0DcGYtRm2UXSat92rpXpDV+YVnNKVdEUhbRqYohqls= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764553515260796.1537252391928; Sun, 30 Nov 2025 17:45:15 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vPsx8-0001iH-Lz; Sun, 30 Nov 2025 20:43:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPsx3-0001ey-Tn; Sun, 30 Nov 2025 20:43:42 -0500 Received: from 60-248-80-70.hinet-ip.hinet.net ([60.248.80.70] helo=Atcsqr.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vPswv-0004p1-Nq; Sun, 30 Nov 2025 20:43:41 -0500 Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 5B11h37U056811 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 1 Dec 2025 09:43:03 +0800 (+08) (envelope-from alvinga@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 1 Dec 2025 09:43:03 +0800 To: , CC: , , , , , , Alvin Chang , Yu-Ming Chang Subject: [PATCH v3 2/2] target/riscv: Simpily support versioning of debug trigger module Date: Mon, 1 Dec 2025 09:42:55 +0800 Message-ID: <20251201014255.230069-3-alvinga@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251201014255.230069-1-alvinga@andestech.com> References: <20251201014255.230069-1-alvinga@andestech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.0.15.183] X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 5B11h37U056811 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.80.70; envelope-from=alvinga@andestech.com; helo=Atcsqr.andestech.com X-Spam_score_int: -8 X-Spam_score: -0.9 X-Spam_bar: / X-Spam_report: (-0.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, RDNS_DYNAMIC=0.982, SPF_PASS=-0.001, TVD_RCVD_IP=0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Alvin Chang From: Alvin Chang via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1764553517931019200 Content-Type: text/plain; charset="utf-8" To support multiple versions of debug specification, we have added "debug-1.0" CPU property. Now the debug trigger module inspects this property to determine the supported trigger types by the CPU. In this commit we validate written trigger type with CPU debug version. For example, the debug specification v0.13 does not support mcontrol6, and the intended tdata_csr_write() on tdata1 with type=3Dmcontrol6 will be ignored. If debug v1.0 is selected, the default trigger type is mcontrol6 instead of legacy mcontrol. Signed-off-by: Alvin Chang Reviewed-by: Yu-Ming Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/debug.c | 56 +++++++++++++++++++++++++++++++++++++++++--- target/riscv/debug.h | 1 + 2 files changed, 54 insertions(+), 3 deletions(-) diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 5664466..5163193 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -64,6 +64,26 @@ static tdata_avail tdata_mapping[TRIGGER_TYPE_NUM] =3D { [TRIGGER_TYPE_UNAVAIL] =3D { true, true, true } }; =20 +/* Valid trigger types supported by debug specification v0.13 */ +static bool valid_trigger_type_v013[TRIGGER_TYPE_NUM] =3D { + [TRIGGER_TYPE_AD_MATCH] =3D true, + [TRIGGER_TYPE_INST_CNT] =3D true, + [TRIGGER_TYPE_INT] =3D true, + [TRIGGER_TYPE_EXCP] =3D true, + [TRIGGER_TYPE_UNAVAIL] =3D true +}; + +/* Valid trigger types supported by debug specification v1.0 */ +static bool valid_trigger_type_v100[TRIGGER_TYPE_NUM] =3D { + [TRIGGER_TYPE_AD_MATCH] =3D true, + [TRIGGER_TYPE_INST_CNT] =3D true, + [TRIGGER_TYPE_INT] =3D true, + [TRIGGER_TYPE_EXCP] =3D true, + [TRIGGER_TYPE_AD_MATCH6] =3D true, + [TRIGGER_TYPE_EXT_SRC] =3D true, + [TRIGGER_TYPE_DISABLED] =3D true +}; + /* only breakpoint size 1/2/4/8 supported */ static int access_size[SIZE_NUM] =3D { [SIZE_ANY] =3D 0, @@ -95,6 +115,20 @@ static inline target_ulong get_trigger_type(CPURISCVSta= te *env, return extract_trigger_type(env, env->tdata1[trigger_index]); } =20 +static inline bool validate_trigger_type(CPURISCVState *env, + target_ulong trigger_type) +{ + if (trigger_type >=3D TRIGGER_TYPE_NUM) { + return false; + } + + if (riscv_cpu_cfg(env)->debug_1_00) { + return valid_trigger_type_v100[trigger_type]; + } + + return valid_trigger_type_v013[trigger_type]; +} + static trigger_action_t get_trigger_action(CPURISCVState *env, target_ulong trigger_index) { @@ -889,6 +923,13 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) trigger_type =3D get_trigger_type(env, env->trigger_cur); } =20 + if (!validate_trigger_type(env, trigger_type)) { + /* Since the tdada1.type is WARL, we simpily ignore write here. */ + qemu_log_mask(LOG_UNIMP, "trigger type: %d is not supported\n", + trigger_type); + return; + } + switch (trigger_type) { case TRIGGER_TYPE_AD_MATCH: type2_reg_write(env, env->trigger_cur, tdata_index, val); @@ -918,8 +959,11 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) target_ulong tinfo_csr_read(CPURISCVState *env) { /* assume all triggers support the same types of triggers */ - return BIT(TRIGGER_TYPE_AD_MATCH) | - BIT(TRIGGER_TYPE_AD_MATCH6); + if (riscv_cpu_cfg(env)->debug_1_00) { + return BIT(TRIGGER_TYPE_AD_MATCH) | BIT(TRIGGER_TYPE_AD_MATCH6); + } + + return BIT(TRIGGER_TYPE_AD_MATCH); } =20 void riscv_cpu_debug_excp_handler(CPUState *cs) @@ -1056,9 +1100,15 @@ void riscv_trigger_realize(CPURISCVState *env) =20 void riscv_trigger_reset_hold(CPURISCVState *env) { - target_ulong tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); + target_ulong tdata1; int i; =20 + if (riscv_cpu_cfg(env)->debug_1_00) { + tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH6, 0, 0); + } else { + tdata1 =3D build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0); + } + /* init to type 2 triggers */ for (i =3D 0; i < RV_MAX_TRIGGERS; i++) { /* diff --git a/target/riscv/debug.h b/target/riscv/debug.h index f76b8f9..0127cb9 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -43,6 +43,7 @@ typedef enum { TRIGGER_TYPE_AD_MATCH6 =3D 6, /* new address/data match trigger */ TRIGGER_TYPE_EXT_SRC =3D 7, /* external source trigger */ TRIGGER_TYPE_UNAVAIL =3D 15, /* trigger exists, but unavailable */ + TRIGGER_TYPE_DISABLED =3D 15, /* trigger exists, but disabled */ TRIGGER_TYPE_NUM } trigger_type_t; =20 --=20 2.43.0