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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4790b0cc186sm56851335e9.13.2025.11.26.12.22.08 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 26 Nov 2025 12:22:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764188530; x=1764793330; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xZit3asfOgEOVwzxp+et8Gfv2AWjf+pVkM2qBGtjPUY=; b=uwNaIK2+PCXCvgFoiLPu7mTWIsiLfL/EqTYwvA1A5NdLzQfIDpVVkASvq7O8HA96ZD EOEU/wJq40BXNL4DPOqkGIamlMKgGOgUbGWb/Hg/k1aNEL3L5W1df7i2ZQ9N36z2fMW+ uNTo1rS1mg7Wow7fWZAZNrLoK/e621PYvwddpeohgg3+42XAV3AFyZhbuGRRxGw+pqYG URwf93/Lp3pXlQ7cYQtqy3J7xkgi2fsGbcvddGsJMUCMroeev3fCdeDZOLTu/PqCEKXI 02PivDwLOqj3DSX2O/zu7vfIilhGf4CAPdRLVlyCL5PSF8/zSTYdmeyp/AR+WiOq9rUT +YPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764188530; x=1764793330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=xZit3asfOgEOVwzxp+et8Gfv2AWjf+pVkM2qBGtjPUY=; b=mfu1CwVNncD9D1p85MRoCeK8aKxPLqwm4wBKy/DAdURoeOfGSgeXVKAl5+7VTuKY+y KEMWq4AHXqeAZgZUL7utei6v/H6arKHBJ13ikv52tPDBFStqfYCGDsewtL+QMoaDLN9U g6hQcdZsD90+w1l14rv8sVG1JPqKVPhcfFfD7CZ+ckOjxbN+FXQ7NAnNCngA5iCHFkQ3 20v2fzyeP8QGR0axzORd0JA32UUjpw+RjeTE3Vqo4A4cVXHpK7S7kYWIXF6IzEGaCC8w Izwc/oEi8EzWrPy4Pl/DMbd0NkRhvPxlfFsFp712Z9HAJFVIl3rymEKUKzYUxlDSpIyr /w8A== X-Gm-Message-State: AOJu0YzUt9Q6qoGz5Nyi0vBswq7yMG2YHMp5yYvnVzV1d4kykmnUYr43 gbdIgQftkCizlnYDFqyL1PDmNOkmKLqR390xIem9m3kPGtfNaLmnwzBdMTTjt2DlH5cR42NWwcR XeE51SSFAf2tc X-Gm-Gg: ASbGncs3SErMQA2CBZpvvZs+ipI5BsM/Xk3jYETZK/2gygd3k4fJcEHU1CEKk+++Zoa AQO6ALRGkpxkcoYBprwjOW46Kzhr3MBzKUHjFJB4ip6g2TtI45i42Xj8r7s6WgcoKNUsJOsxZi7 Ct49qpoyViaspG7/z1UMID0VoNvuzI0xUUCiABZOzT3Yd3cvKF/XKl9vNuDp2zrrRidNw2iskCk oRPDfnJZxsPXE3UN/iNXUepAvtAVuNIdHVEcfU1jTZx0wYJ/zlMYcky9BwUoeLTHAz0p6Pb5Yaz Z9KSOsNykqrqpSGZ50rGQgnrkJP6f2vZ0yAUUWdgFUzsioEsUfYA8GB1RrqOKVheBHqgDAZaEtX 45R3720zYlv/6mpTYSp+ReOemSzOA2EEk6KBrGQ2IzfLGYP/1PkZjo2nIS4t+tnn0Lxuo1zWLUz zRMzNDQLlZf+yHxVKfSFKi87JghvHmuxGqi13kwLLxT/bp+37VOQj6rvko03sz X-Google-Smtp-Source: AGHT+IG4dSZCvZgG3Tvo+D195zC/W9JpFSfCDJ2icMJnmkn52udzdUtFfmNtEE/FAYba1+LsC9avLA== X-Received: by 2002:a05:600c:3541:b0:477:7f4a:44b4 with SMTP id 5b1f17b1804b1-477c0162dfamr202858115e9.1.1764188529766; Wed, 26 Nov 2025 12:22:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Brian Cain Subject: [PATCH-for-11.0 v3 01/22] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Date: Wed, 26 Nov 2025 21:21:37 +0100 Message-ID: <20251126202200.23100-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126202200.23100-1-philmd@linaro.org> References: <20251126202200.23100-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764189620752019200 We only build the Hexagon target using little endianness order, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. Mechanical change running: $ tgt=3Dhexagon; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Brian Cain Reviewed-by: Richard Henderson --- target/hexagon/macros.h | 6 +++--- target/hexagon/op_helper.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 088e5961ab7..6c2862a2320 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -519,9 +519,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) #else #define MEM_LOAD1 cpu_ldub_data_ra -#define MEM_LOAD2 cpu_lduw_data_ra -#define MEM_LOAD4 cpu_ldl_data_ra -#define MEM_LOAD8 cpu_ldq_data_ra +#define MEM_LOAD2 cpu_lduw_le_data_ra +#define MEM_LOAD4 cpu_ldl_le_data_ra +#define MEM_LOAD8 cpu_ldq_le_data_ra =20 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ do { \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index e2e80ca7efa..08db1e9c56b 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -77,13 +77,13 @@ static void commit_store(CPUHexagonState *env, int slot= _num, uintptr_t ra) cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); break; case 2: - cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); + cpu_stw_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, = ra); break; case 4: - cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); + cpu_stl_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, = ra); break; case 8: - cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra); + cpu_stq_le_data_ra(env, va, env->mem_log_stores[slot_num].data64, = ra); break; default: g_assert_not_reached(); --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764194869; cv=none; d=zohomail.com; s=zohoarc; b=QvNr/AxEzoYAipdRgblau5IRm48tflQvYSzSPdczDhnobyUKzgcgU/4C2msz4MFAYExYnk5ny98cgs1qciImMCpjBUGSgpTCan2sC5EPpDuzL7+KYpiS1GIdsmydiw/W/pzlJqfZ2I9DaEd4/J0F/wbPLQnHNv3jfuQbaVZSqj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764194869; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=5F4dDYY71Q++E/ouz6o5QMXDI/1gbMs/5Vg/XDgnw60=; b=Yx8z0j8MBiAUb1On9C4s379Zty3EjM1KNhLv8rRgov9f+MX8A/UDCImRAecP9h3QTnCvk17MCQHU5Nxn8lMiBGSbngD1fZjYZs9cl8bZXkJknTFgVd+gE7dX4OmGLgU2aOKNWUonDxsEz+SNqg9VMGM8nUJZ9eYiVkXCy5WkQdg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764194869283436.60980400956987; Wed, 26 Nov 2025 14:07:49 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM21-0002Ik-IT; Wed, 26 Nov 2025 15:22:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM1z-0002Dw-Qd for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:22:27 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM1u-00026G-BT for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:22:26 -0500 Received: by mail-wm1-x341.google.com with SMTP id 5b1f17b1804b1-4775ae77516so930445e9.1 for ; Wed, 26 Nov 2025 12:22:20 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Use the explicit little-endian variants. Mechanical change running: $ tgt=3Di386; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting indentation in helper_vmload() to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/ops_sse.h | 12 ++--- target/i386/tcg/seg_helper.h | 12 ++--- linux-user/vm86.c | 4 +- target/i386/tcg/mem_helper.c | 8 ++-- target/i386/tcg/mpx_helper.c | 28 +++++------ target/i386/tcg/seg_helper.c | 16 +++---- target/i386/tcg/system/excp_helper.c | 8 ++-- target/i386/tcg/system/svm_helper.c | 69 +++++++++++++++------------- 8 files changed, 80 insertions(+), 77 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index a2e4d480399..213db53382c 100644 --- a/target/i386/ops_sse.h +++ b/target/i386/ops_sse.h @@ -2326,7 +2326,7 @@ void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *= env, =20 for (i =3D 0; i < (2 << SHIFT); i++) { if (v->L(i) >> 31) { - cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC()); + cpu_stl_le_data_ra(env, a0 + i * 4, s->L(i), GETPC()); } } } @@ -2338,7 +2338,7 @@ void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *= env, =20 for (i =3D 0; i < (1 << SHIFT); i++) { if (v->Q(i) >> 63) { - cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC()); + cpu_stq_le_data_ra(env, a0 + i * 8, s->Q(i), GETPC()); } } } @@ -2369,7 +2369,7 @@ void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env, if (v->L(i) >> 31) { target_ulong addr =3D a0 + ((target_ulong)(int32_t)s->L(i) << scale); - d->L(i) =3D cpu_ldl_data_ra(env, addr, GETPC()); + d->L(i) =3D cpu_ldl_le_data_ra(env, addr, GETPC()); } v->L(i) =3D 0; } @@ -2383,7 +2383,7 @@ void glue(helper_vpgatherdq, SUFFIX)(CPUX86State *env, if (v->Q(i) >> 63) { target_ulong addr =3D a0 + ((target_ulong)(int32_t)s->L(i) << scale); - d->Q(i) =3D cpu_ldq_data_ra(env, addr, GETPC()); + d->Q(i) =3D cpu_ldq_le_data_ra(env, addr, GETPC()); } v->Q(i) =3D 0; } @@ -2397,7 +2397,7 @@ void glue(helper_vpgatherqd, SUFFIX)(CPUX86State *env, if (v->L(i) >> 31) { target_ulong addr =3D a0 + ((target_ulong)(int64_t)s->Q(i) << scale); - d->L(i) =3D cpu_ldl_data_ra(env, addr, GETPC()); + d->L(i) =3D cpu_ldl_le_data_ra(env, addr, GETPC()); } v->L(i) =3D 0; } @@ -2415,7 +2415,7 @@ void glue(helper_vpgatherqq, SUFFIX)(CPUX86State *env, if (v->Q(i) >> 63) { target_ulong addr =3D a0 + ((target_ulong)(int64_t)s->Q(i) << scale); - d->Q(i) =3D cpu_ldq_data_ra(env, addr, GETPC()); + d->Q(i) =3D cpu_ldq_le_data_ra(env, addr, GETPC()); } v->Q(i) =3D 0; } diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ea98e1a98ed..20ce47d62d9 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -40,18 +40,18 @@ int cpu_mmu_index_kernel(CPUX86State *env); * and use *_mmuidx_ra directly. */ #define cpu_lduw_kernel_ra(e, p, r) \ - cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_lduw_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldl_kernel_ra(e, p, r) \ - cpu_ldl_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_ldl_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldq_kernel_ra(e, p, r) \ - cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_ldq_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) =20 #define cpu_stw_kernel_ra(e, p, v, r) \ - cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stw_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stl_kernel_ra(e, p, v, r) \ - cpu_stl_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stl_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stq_kernel_ra(e, p, v, r) \ - cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stq_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) =20 #define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0) #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0) diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 5091d53fb84..4e120875a06 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -44,7 +44,7 @@ static inline int is_revectored(int nr, struct target_rev= ectored_struct *bitmap) static inline void vm_putw(CPUX86State *env, uint32_t segptr, unsigned int reg16, unsigned int val) { - cpu_stw_data(env, segptr + (reg16 & 0xffff), val); + cpu_stw_le_data(env, segptr + (reg16 & 0xffff), val); } =20 void save_v86_state(CPUX86State *env) @@ -157,7 +157,7 @@ static void do_int(CPUX86State *env, int intno) &ts->vm86plus.int21_revectored)) goto cannot_handle; int_addr =3D (intno << 2); - segoffs =3D cpu_ldl_data(env, int_addr); + segoffs =3D cpu_ldl_le_data(env, int_addr); if ((segoffs >> 16) =3D=3D TARGET_BIOSSEG) goto cannot_handle; LOG_VM86("VM86: emulating int 0x%x. CS:IP=3D%04x:%04x\n", diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 9e7c2d80293..c15a32d60ad 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -30,8 +30,8 @@ void helper_boundw(CPUX86State *env, target_ulong a0, int= v) { int low, high; =20 - low =3D cpu_ldsw_data_ra(env, a0, GETPC()); - high =3D cpu_ldsw_data_ra(env, a0 + 2, GETPC()); + low =3D cpu_ldsw_le_data_ra(env, a0, GETPC()); + high =3D cpu_ldsw_le_data_ra(env, a0 + 2, GETPC()); v =3D (int16_t)v; if (v < low || v > high) { if (env->hflags & HF_MPX_EN_MASK) { @@ -45,8 +45,8 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int= v) { int low, high; =20 - low =3D cpu_ldl_data_ra(env, a0, GETPC()); - high =3D cpu_ldl_data_ra(env, a0 + 4, GETPC()); + low =3D cpu_ldl_le_data_ra(env, a0, GETPC()); + high =3D cpu_ldl_le_data_ra(env, a0 + 4, GETPC()); if (v < low || v > high) { if (env->hflags & HF_MPX_EN_MASK) { env->bndcs_regs.sts =3D 0; diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fa8abcc4820..73d33bf5e4a 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -44,7 +44,7 @@ static uint64_t lookup_bte64(CPUX86State *env, uint64_t b= ase, uintptr_t ra) } =20 bde =3D (extract64(base, 20, 28) << 3) + (extract64(bndcsr, 20, 44) <<= 12); - bt =3D cpu_ldq_data_ra(env, bde, ra); + bt =3D cpu_ldq_le_data_ra(env, bde, ra); if ((bt & 1) =3D=3D 0) { env->bndcs_regs.sts =3D bde | 2; raise_exception_ra(env, EXCP05_BOUND, ra); @@ -64,7 +64,7 @@ static uint32_t lookup_bte32(CPUX86State *env, uint32_t b= ase, uintptr_t ra) } =20 bde =3D (extract32(base, 12, 20) << 2) + (bndcsr & TARGET_PAGE_MASK); - bt =3D cpu_ldl_data_ra(env, bde, ra); + bt =3D cpu_ldl_le_data_ra(env, bde, ra); if ((bt & 1) =3D=3D 0) { env->bndcs_regs.sts =3D bde | 2; raise_exception_ra(env, EXCP05_BOUND, ra); @@ -79,9 +79,9 @@ uint64_t helper_bndldx64(CPUX86State *env, target_ulong b= ase, target_ulong ptr) uint64_t bte, lb, ub, pt; =20 bte =3D lookup_bte64(env, base, ra); - lb =3D cpu_ldq_data_ra(env, bte, ra); - ub =3D cpu_ldq_data_ra(env, bte + 8, ra); - pt =3D cpu_ldq_data_ra(env, bte + 16, ra); + lb =3D cpu_ldq_le_data_ra(env, bte, ra); + ub =3D cpu_ldq_le_data_ra(env, bte + 8, ra); + pt =3D cpu_ldq_le_data_ra(env, bte + 16, ra); =20 if (pt !=3D ptr) { lb =3D ub =3D 0; @@ -96,9 +96,9 @@ uint64_t helper_bndldx32(CPUX86State *env, target_ulong b= ase, target_ulong ptr) uint32_t bte, lb, ub, pt; =20 bte =3D lookup_bte32(env, base, ra); - lb =3D cpu_ldl_data_ra(env, bte, ra); - ub =3D cpu_ldl_data_ra(env, bte + 4, ra); - pt =3D cpu_ldl_data_ra(env, bte + 8, ra); + lb =3D cpu_ldl_le_data_ra(env, bte, ra); + ub =3D cpu_ldl_le_data_ra(env, bte + 4, ra); + pt =3D cpu_ldl_le_data_ra(env, bte + 8, ra); =20 if (pt !=3D ptr) { lb =3D ub =3D 0; @@ -113,9 +113,9 @@ void helper_bndstx64(CPUX86State *env, target_ulong bas= e, target_ulong ptr, uint64_t bte; =20 bte =3D lookup_bte64(env, base, ra); - cpu_stq_data_ra(env, bte, lb, ra); - cpu_stq_data_ra(env, bte + 8, ub, ra); - cpu_stq_data_ra(env, bte + 16, ptr, ra); + cpu_stq_le_data_ra(env, bte, lb, ra); + cpu_stq_le_data_ra(env, bte + 8, ub, ra); + cpu_stq_le_data_ra(env, bte + 16, ptr, ra); } =20 void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr, @@ -125,9 +125,9 @@ void helper_bndstx32(CPUX86State *env, target_ulong bas= e, target_ulong ptr, uint32_t bte; =20 bte =3D lookup_bte32(env, base, ra); - cpu_stl_data_ra(env, bte, lb, ra); - cpu_stl_data_ra(env, bte + 4, ub, ra); - cpu_stl_data_ra(env, bte + 8, ptr, ra); + cpu_stl_le_data_ra(env, bte, lb, ra); + cpu_stl_le_data_ra(env, bte + 4, ub, ra); + cpu_stl_le_data_ra(env, bte + 8, ptr, ra); } =20 void helper_bnd_jmp(CPUX86State *env) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 227336c4ef2..58aac720119 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -65,20 +65,20 @@ typedef struct StackAccess static void pushw(StackAccess *sa, uint16_t val) { sa->sp -=3D 2; - cpu_stw_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), + cpu_stw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), val, sa->mmu_index, sa->ra); } =20 static void pushl(StackAccess *sa, uint32_t val) { sa->sp -=3D 4; - cpu_stl_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), + cpu_stl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), val, sa->mmu_index, sa->ra); } =20 static uint16_t popw(StackAccess *sa) { - uint16_t ret =3D cpu_lduw_mmuidx_ra(sa->env, + uint16_t ret =3D cpu_lduw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), sa->mmu_index, sa->ra); sa->sp +=3D 2; @@ -87,7 +87,7 @@ static uint16_t popw(StackAccess *sa) =20 static uint32_t popl(StackAccess *sa) { - uint32_t ret =3D cpu_ldl_mmuidx_ra(sa->env, + uint32_t ret =3D cpu_ldl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), sa->mmu_index, sa->ra); sa->sp +=3D 4; @@ -905,12 +905,12 @@ static void do_interrupt_protected(CPUX86State *env, = int intno, int is_int, static void pushq(StackAccess *sa, uint64_t val) { sa->sp -=3D 8; - cpu_stq_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra); + cpu_stq_le_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra); } =20 static uint64_t popq(StackAccess *sa) { - uint64_t ret =3D cpu_ldq_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa-= >ra); + uint64_t ret =3D cpu_ldq_le_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, = sa->ra); sa->sp +=3D 8; return ret; } @@ -1887,7 +1887,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, pushl(&sa, env->segs[R_SS].selector); pushl(&sa, env->regs[R_ESP]); for (i =3D param_count - 1; i >=3D 0; i--) { - val =3D cpu_ldl_data_ra(env, + val =3D cpu_ldl_le_data_ra(env, old_ssp + ((env->regs[R_ESP] + i= * 4) & old_sp_mask), GETPC()); pushl(&sa, val); @@ -1896,7 +1896,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, pushw(&sa, env->segs[R_SS].selector); pushw(&sa, env->regs[R_ESP]); for (i =3D param_count - 1; i >=3D 0; i--) { - val =3D cpu_lduw_data_ra(env, + val =3D cpu_lduw_le_data_ra(env, old_ssp + ((env->regs[R_ESP] + = i * 2) & old_sp_mask), GETPC()); pushw(&sa, val); diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index f622b5d588e..d7ea77c8558 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -90,7 +90,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, ui= nt64_t ra) if (likely(in->haddr)) { return ldl_p(in->haddr); } - return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); + return cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) @@ -98,7 +98,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, ui= nt64_t ra) if (likely(in->haddr)) { return ldq_p(in->haddr); } - return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); + return cpu_ldq_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 /* @@ -116,9 +116,9 @@ static bool ptw_setl_slow(const PTETranslate *in, uint3= 2_t old, uint32_t new) cpu_exec_end(cpu); /* Does x86 really perform a rmw cycle on mmio for ptw? */ start_exclusive(); - cmp =3D cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + cmp =3D cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); if (cmp =3D=3D old) { - cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); + cpu_stl_le_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); } end_exclusive(); cpu_exec_start(cpu); diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index 4b86796518f..3e236094d6f 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -30,13 +30,13 @@ static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, const SegmentCache *sc) { - cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), sc->selector, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), sc->base, mmu_idx, 0); - cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + cpu_stl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), sc->limit, mmu_idx, 0); - cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), ((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00), mmu_idx, 0); @@ -58,16 +58,16 @@ static void svm_load_seg(CPUX86State *env, int mmu_idx,= hwaddr addr, unsigned int flags; =20 sc->selector =3D - cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, select= or), mmu_idx, 0); sc->base =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), mmu_idx, 0); sc->limit =3D - cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + cpu_ldl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), mmu_idx, 0); flags =3D - cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib= ), mmu_idx, 0); sc->flags =3D ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); =20 @@ -507,32 +507,35 @@ void helper_vmload(CPUX86State *env, int aflag) =20 #ifdef TARGET_X86_64 env->kernelgsbase =3D - cpu_ldq_mmuidx_ra(env, - addr + offsetof(struct vmcb, save.kernel_gs_base= ), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.kernel_gs_b= ase), + mmu_idx, 0); env->lstar =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + mmu_idx, 0); env->cstar =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + mmu_idx, 0); env->fmask =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask= ), + mmu_idx, 0); svm_canonicalization(env, &env->kernelgsbase); #endif env->star =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + mmu_idx, 0); env->sysenter_cs =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= cs), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_cs= ), + mmu_idx, 0); env->sysenter_esp =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= esp), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_es= p), + mmu_idx, 0); env->sysenter_eip =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= eip), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_ei= p), + mmu_idx, 0); } =20 void helper_vmsave(CPUX86State *env, int aflag) @@ -567,22 +570,22 @@ void helper_vmsave(CPUX86State *env, int aflag) &env->ldt); =20 #ifdef TARGET_X86_64 - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_bas= e), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_= base), env->kernelgsbase, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), env->lstar, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), env->cstar, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), env->fmask, mmu_idx, 0); #endif - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), env->star, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_c= s), env->sysenter_cs, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_e= sp), env->sysenter_esp, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_e= ip), env->sysenter_eip, mmu_idx, 0); } =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Use the explicit little-endian variants. [*] RISC-V "V" Vector Extension v1.0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee86..caa8dd9c125 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ } =20 GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le) +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le) +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ @@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ } =20 GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le) +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le) +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le) =20 static inline QEMU_ALWAYS_INLINE void vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_t= lb, --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764195821; cv=none; d=zohomail.com; s=zohoarc; b=hk98H/lmSkpOO54VukUKXvJJ4Ifu9xvivppSMWHVAlXDHpn1VjZkJL0WFtt1mU0kYqmJCuhNJmV0LaPEKF5K4vZs03ISAJMqeZTXlk4ai8/hSigrkXOfz8p9iHqZaa1tzau+7qFSt0PIPj4BzGY/30Wv8X8zI/bHTx0viao+di8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764195821; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VIPG/naiBj4JXek6sevzzf+dt9iCr5C8g6EGc2RUz7w=; b=XWCHSx8i2oAbFnwsAt0eHjKUx3gsDxRhrHoIkSKW4nFgjRhyauJa7j3QuII5qUDYlTVGFETzUMEV+AAxh71X8rqvOMD9nWoyK0N/z0HOL8E+GgLHwJ/XThJuJXLcsuPTGaRLa5bSSPuNIMRnVpDqSmujTHBeWyRnuIkWqory/M0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764195821591510.84723806177374; Wed, 26 Nov 2025 14:23:41 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM29-0002Ql-JU; Wed, 26 Nov 2025 15:22:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM27-0002MV-1Y for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:22:35 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM24-0002Kr-Hl for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:22:34 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-477619f8ae5so494175e9.3 for ; Wed, 26 Nov 2025 12:22:32 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f49a7bsm42205519f8f.19.2025.11.26.12.22.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 26 Nov 2025 12:22:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764188551; x=1764793351; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VIPG/naiBj4JXek6sevzzf+dt9iCr5C8g6EGc2RUz7w=; b=ndFSz1FNhmbqaFgjHpnbdbmqyMLvsCc2i1k1jc8VyUvqkRScn9IZCvIgIISWLzJ5FF YwL9NRJCetB3Hk1iizW3giaWvn/4sMFFwD4xtbuO/oCR0lGPsA0PoA2N7rHR6aarmy9H IzJpLV1eOA/tWVnf0M853ADCU7tPecp3PWlSosE+Bsayf7qVaFPxKQKyt64AbCBrY5AS RzrUdqEdXgjvgFAHALd2U18kAv7BctBS/6GrkYWcsu3rs3IC7jaywuFkvWmudEmy8BAH jvD4PdtsqDTnKByAN1sHuZDNKq6V1VOwtLJJ1XAdGRMEILphOOPTCa24JbFm5wATEhwj TbSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764188551; x=1764793351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=VIPG/naiBj4JXek6sevzzf+dt9iCr5C8g6EGc2RUz7w=; b=wJR5lPNyqteJLisfUlMWLm/FecYIENC0BgQtjrw1D5wB2w7xdxcnKk1Xj5vF5+D+rn Im6JKdjuT51s+hzYDCpo6BCVmzqmCsklerVltnz1yxLDcYH8OI6n1AVMYrBSBm8oSCc7 uO9zy1BBqgfcR6GQjRABrtZyulpV0mNAFzEloRmmjmBPYXYqY+vZec97C9Elo4G9/mmM hhEr6tJ8WJDYYynD0spndKKcuPBXWeXKT3lGw4Ux9lxTYDNbMseZpzVsfJQODXdI5Hxe qUUFTzC0h4DXzvfXnLgajjoOJLvmY/7ilxLqH35ff9J+G8/LslWQ8bXKyUUNZXTZ+Srj ezoA== X-Gm-Message-State: AOJu0YwOju+V5UvsTK6Jgr1kaH2xpGaiYyBucjkbMgxbSZy+fA8Dc6gR Pnl2a9WGTgJ6pBm8kUDNyDOEpvTyU56WFQL9E1YuZM7jZOEn5T/dQC6JFhwkh6kzGNjYnbsbH6O HnYJy5vG2W0G9 X-Gm-Gg: ASbGncsNDLnPoCn2ub4RTEYyAO8PR67fBi9Y0HYHKTCmiKLZjlytXGG/9k2nfHixOMg RNAkZeDCFpvSCor/8bva5+6ykX1jUR6wacSQVa2r+Np7YB3XY7SrgSFq8+R9iLIJvRdcdujCtWs I6OEmKXw07JEcW6au9CbmzdV8FVRR4oCWh6Ad9GgAxa+Lk3Ove3gdM8IpoSKDqZoRa2LovZ3ax5 BclR9Ss8AAD8h0bwetxv6sU7JwQpJXG0ULndPL0fZ0rEF34Gm0SgXcgzeSqN7LLzgDyqSZqxK0g qH52tSbYVFBpsi3jljrbLAOC2dlXpeaPnRS4gB5RbX4YCC4p3ICWHRbiztBiFJB+6JS3pOK5sf7 6vATMkhOEOWEKtHDeNEEGFn7M3kaxqwmksEJn2Pus3zR8KFAdXxIEnb+uhx8sAranyn/wXoSHJU sCV1CER+eK0cvn6NLX9pHSvUamsfT4hP6vCZ4u3jtQG7eQfu+7jYyq7yGf2Veb X-Google-Smtp-Source: AGHT+IE+J4hkPc+qoDBzLlo50hXYN9XPtG+xb4Q3feL46FZeUSlPs/IpusCjFjCSzhOQ7W/cwQ0vJA== X-Received: by 2002:a05:600c:1994:b0:477:5aaa:57a6 with SMTP id 5b1f17b1804b1-477c016e402mr186697295e9.10.1764188550847; Wed, 26 Nov 2025 12:22:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, Richard Henderson , qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH-for-11.0 v3 04/22] target/rx: Use little-endian variant of cpu_ld/st_data*() Date: Wed, 26 Nov 2025 21:21:40 +0100 Message-ID: <20251126202200.23100-5-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126202200.23100-1-philmd@linaro.org> References: <20251126202200.23100-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764195822839019200 We only build the RX target using little endianness order, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. Mechanical change running: $ tgt=3Drx; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/helper.c | 14 +++++++------- target/rx/op_helper.c | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/rx/helper.c b/target/rx/helper.c index e9a7aaf610d..83cd491eb4a 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -68,10 +68,10 @@ void rx_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); + cpu_stl_le_data(env, env->isp, save_psw); env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); - env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); + cpu_stl_le_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_le_data(env, env->intb + env->ack_irq * 4); env->psw_ipl =3D env->ack_ipl; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); qemu_set_irq(env->ack, env->ack_irq); @@ -82,14 +82,14 @@ void rx_cpu_do_interrupt(CPUState *cs) const char *expname =3D "unknown exception"; =20 env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); + cpu_stl_le_data(env, env->isp, save_psw); env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); + cpu_stl_le_data(env, env->isp, env->pc); =20 if (vec < 0x100) { - env->pc =3D cpu_ldl_data(env, 0xffffff80 + vec * 4); + env->pc =3D cpu_ldl_le_data(env, 0xffffff80 + vec * 4); } else { - env->pc =3D cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); + env->pc =3D cpu_ldl_le_data(env, env->intb + (vec & 0xff) * 4); } =20 if (vec =3D=3D 30) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 2b190a4b2cf..ca3e9e85fc7 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -217,20 +217,20 @@ void helper_scmpu(CPURXState *env) static uint32_t (* const cpu_ldufn[])(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) =3D { - cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, + cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra, }; =20 static uint32_t (* const cpu_ldfn[])(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) =3D { - cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, + cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra, }; =20 static void (* const cpu_stfn[])(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t retaddr) =3D { - cpu_stb_data_ra, cpu_stw_data_ra, cpu_stl_data_ra, + cpu_stb_data_ra, cpu_stw_le_data_ra, cpu_stl_le_data_ra, }; =20 void helper_sstr(CPURXState *env, uint32_t sz) --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764205416; cv=none; d=zohomail.com; s=zohoarc; b=KN8YkTeiBC2TfFQZzGRB+O0jvVkFIfwxdnpIMYAtugj9AaW9BOdbay7H15Z5Q/85XXDjM/pkng/cK+dzVScUdAz5xlGssgo1ASdnyqt6NjFpu7bS7Sv95YAI+E+ims5wHY8AFd6r9zb5s7IRTNWAu69GwnXFRoU9pPnZSC7b+dA= ARC-Message-Signature: i=1; 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Use the explicit little-endian variants. Mechanical change running: $ tgt=3Dtricore; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting spaces style manually to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/tricore/op_helper.c | 152 ++++++++++++++++++------------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 2c8281a67e0..fde2c0f8383 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2451,84 +2451,84 @@ static bool cdc_zero(uint32_t *psw) =20 static void save_context_upper(CPUTriCoreState *env, uint32_t ea) { - cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, psw_read(env)); - cpu_stl_data(env, ea+8, env->gpr_a[10]); - cpu_stl_data(env, ea+12, env->gpr_a[11]); - cpu_stl_data(env, ea+16, env->gpr_d[8]); - cpu_stl_data(env, ea+20, env->gpr_d[9]); - cpu_stl_data(env, ea+24, env->gpr_d[10]); - cpu_stl_data(env, ea+28, env->gpr_d[11]); - cpu_stl_data(env, ea+32, env->gpr_a[12]); - cpu_stl_data(env, ea+36, env->gpr_a[13]); - cpu_stl_data(env, ea+40, env->gpr_a[14]); - cpu_stl_data(env, ea+44, env->gpr_a[15]); - cpu_stl_data(env, ea+48, env->gpr_d[12]); - cpu_stl_data(env, ea+52, env->gpr_d[13]); - cpu_stl_data(env, ea+56, env->gpr_d[14]); - cpu_stl_data(env, ea+60, env->gpr_d[15]); + cpu_stl_le_data(env, ea, env->PCXI); + cpu_stl_le_data(env, ea + 4, psw_read(env)); + cpu_stl_le_data(env, ea + 8, env->gpr_a[10]); + cpu_stl_le_data(env, ea + 12, env->gpr_a[11]); + cpu_stl_le_data(env, ea + 16, env->gpr_d[8]); + cpu_stl_le_data(env, ea + 20, env->gpr_d[9]); + cpu_stl_le_data(env, ea + 24, env->gpr_d[10]); + cpu_stl_le_data(env, ea + 28, env->gpr_d[11]); + cpu_stl_le_data(env, ea + 32, env->gpr_a[12]); + cpu_stl_le_data(env, ea + 36, env->gpr_a[13]); + cpu_stl_le_data(env, ea + 40, env->gpr_a[14]); + cpu_stl_le_data(env, ea + 44, env->gpr_a[15]); + cpu_stl_le_data(env, ea + 48, env->gpr_d[12]); + cpu_stl_le_data(env, ea + 52, env->gpr_d[13]); + cpu_stl_le_data(env, ea + 56, env->gpr_d[14]); + cpu_stl_le_data(env, ea + 60, env->gpr_d[15]); } =20 static void save_context_lower(CPUTriCoreState *env, uint32_t ea) { - cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, env->gpr_a[11]); - cpu_stl_data(env, ea+8, env->gpr_a[2]); - cpu_stl_data(env, ea+12, env->gpr_a[3]); - cpu_stl_data(env, ea+16, env->gpr_d[0]); - cpu_stl_data(env, ea+20, env->gpr_d[1]); - cpu_stl_data(env, ea+24, env->gpr_d[2]); - cpu_stl_data(env, ea+28, env->gpr_d[3]); - cpu_stl_data(env, ea+32, env->gpr_a[4]); - cpu_stl_data(env, ea+36, env->gpr_a[5]); - cpu_stl_data(env, ea+40, env->gpr_a[6]); - cpu_stl_data(env, ea+44, env->gpr_a[7]); - cpu_stl_data(env, ea+48, env->gpr_d[4]); - cpu_stl_data(env, ea+52, env->gpr_d[5]); - cpu_stl_data(env, ea+56, env->gpr_d[6]); - cpu_stl_data(env, ea+60, env->gpr_d[7]); + cpu_stl_le_data(env, ea, env->PCXI); + cpu_stl_le_data(env, ea + 4, env->gpr_a[11]); + cpu_stl_le_data(env, ea + 8, env->gpr_a[2]); + cpu_stl_le_data(env, ea + 12, env->gpr_a[3]); + cpu_stl_le_data(env, ea + 16, env->gpr_d[0]); + cpu_stl_le_data(env, ea + 20, env->gpr_d[1]); + cpu_stl_le_data(env, ea + 24, env->gpr_d[2]); + cpu_stl_le_data(env, ea + 28, env->gpr_d[3]); + cpu_stl_le_data(env, ea + 32, env->gpr_a[4]); + cpu_stl_le_data(env, ea + 36, env->gpr_a[5]); + cpu_stl_le_data(env, ea + 40, env->gpr_a[6]); + cpu_stl_le_data(env, ea + 44, env->gpr_a[7]); + cpu_stl_le_data(env, ea + 48, env->gpr_d[4]); + cpu_stl_le_data(env, ea + 52, env->gpr_d[5]); + cpu_stl_le_data(env, ea + 56, env->gpr_d[6]); + cpu_stl_le_data(env, ea + 60, env->gpr_d[7]); } =20 static void restore_context_upper(CPUTriCoreState *env, uint32_t ea, uint32_t *new_PCXI, uint32_t *new_PSW) { - *new_PCXI =3D cpu_ldl_data(env, ea); - *new_PSW =3D cpu_ldl_data(env, ea+4); - env->gpr_a[10] =3D cpu_ldl_data(env, ea+8); - env->gpr_a[11] =3D cpu_ldl_data(env, ea+12); - env->gpr_d[8] =3D cpu_ldl_data(env, ea+16); - env->gpr_d[9] =3D cpu_ldl_data(env, ea+20); - env->gpr_d[10] =3D cpu_ldl_data(env, ea+24); - env->gpr_d[11] =3D cpu_ldl_data(env, ea+28); - env->gpr_a[12] =3D cpu_ldl_data(env, ea+32); - env->gpr_a[13] =3D cpu_ldl_data(env, ea+36); - env->gpr_a[14] =3D cpu_ldl_data(env, ea+40); - env->gpr_a[15] =3D cpu_ldl_data(env, ea+44); - env->gpr_d[12] =3D cpu_ldl_data(env, ea+48); - env->gpr_d[13] =3D cpu_ldl_data(env, ea+52); - env->gpr_d[14] =3D cpu_ldl_data(env, ea+56); - env->gpr_d[15] =3D cpu_ldl_data(env, ea+60); + *new_PCXI =3D cpu_ldl_le_data(env, ea); + *new_PSW =3D cpu_ldl_le_data(env, ea + 4); + env->gpr_a[10] =3D cpu_ldl_le_data(env, ea + 8); + env->gpr_a[11] =3D cpu_ldl_le_data(env, ea + 12); + env->gpr_d[8] =3D cpu_ldl_le_data(env, ea + 16); + env->gpr_d[9] =3D cpu_ldl_le_data(env, ea + 20); + env->gpr_d[10] =3D cpu_ldl_le_data(env, ea + 24); + env->gpr_d[11] =3D cpu_ldl_le_data(env, ea + 28); + env->gpr_a[12] =3D cpu_ldl_le_data(env, ea + 32); + env->gpr_a[13] =3D cpu_ldl_le_data(env, ea + 36); + env->gpr_a[14] =3D cpu_ldl_le_data(env, ea + 40); + env->gpr_a[15] =3D cpu_ldl_le_data(env, ea + 44); + env->gpr_d[12] =3D cpu_ldl_le_data(env, ea + 48); + env->gpr_d[13] =3D cpu_ldl_le_data(env, ea + 52); + env->gpr_d[14] =3D cpu_ldl_le_data(env, ea + 56); + env->gpr_d[15] =3D cpu_ldl_le_data(env, ea + 60); } =20 static void restore_context_lower(CPUTriCoreState *env, uint32_t ea, uint32_t *ra, uint32_t *pcxi) { - *pcxi =3D cpu_ldl_data(env, ea); - *ra =3D cpu_ldl_data(env, ea+4); - env->gpr_a[2] =3D cpu_ldl_data(env, ea+8); - env->gpr_a[3] =3D cpu_ldl_data(env, ea+12); - env->gpr_d[0] =3D cpu_ldl_data(env, ea+16); - env->gpr_d[1] =3D cpu_ldl_data(env, ea+20); - env->gpr_d[2] =3D cpu_ldl_data(env, ea+24); - env->gpr_d[3] =3D cpu_ldl_data(env, ea+28); - env->gpr_a[4] =3D cpu_ldl_data(env, ea+32); - env->gpr_a[5] =3D cpu_ldl_data(env, ea+36); - env->gpr_a[6] =3D cpu_ldl_data(env, ea+40); - env->gpr_a[7] =3D cpu_ldl_data(env, ea+44); - env->gpr_d[4] =3D cpu_ldl_data(env, ea+48); - env->gpr_d[5] =3D cpu_ldl_data(env, ea+52); - env->gpr_d[6] =3D cpu_ldl_data(env, ea+56); - env->gpr_d[7] =3D cpu_ldl_data(env, ea+60); + *pcxi =3D cpu_ldl_le_data(env, ea); + *ra =3D cpu_ldl_le_data(env, ea + 4); + env->gpr_a[2] =3D cpu_ldl_le_data(env, ea + 8); + env->gpr_a[3] =3D cpu_ldl_le_data(env, ea + 12); + env->gpr_d[0] =3D cpu_ldl_le_data(env, ea + 16); + env->gpr_d[1] =3D cpu_ldl_le_data(env, ea + 20); + env->gpr_d[2] =3D cpu_ldl_le_data(env, ea + 24); + env->gpr_d[3] =3D cpu_ldl_le_data(env, ea + 28); + env->gpr_a[4] =3D cpu_ldl_le_data(env, ea + 32); + env->gpr_a[5] =3D cpu_ldl_le_data(env, ea + 36); + env->gpr_a[6] =3D cpu_ldl_le_data(env, ea + 40); + env->gpr_a[7] =3D cpu_ldl_le_data(env, ea + 44); + env->gpr_d[4] =3D cpu_ldl_le_data(env, ea + 48); + env->gpr_d[5] =3D cpu_ldl_le_data(env, ea + 52); + env->gpr_d[6] =3D cpu_ldl_le_data(env, ea + 56); + env->gpr_d[7] =3D cpu_ldl_le_data(env, ea + 60); } =20 void helper_call(CPUTriCoreState *env, uint32_t next_pc) @@ -2566,7 +2566,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_= pc) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2632,7 +2632,7 @@ void helper_ret(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * wo= rd); */ restore_context_upper(env, ea, &new_PCXI, &new_PSW); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* FCX[19: 0] =3D PCXI[19: 0]; */ env->FCX =3D (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff); /* PCXI =3D new_PCXI; */ @@ -2662,7 +2662,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const= 9) ea =3D ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6); =20 /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[= 3], A[4] , A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */ save_context_lower(env, ea); @@ -2726,7 +2726,7 @@ void helper_rfe(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * word= ); */ restore_context_upper(env, ea, &new_PCXI, &new_PSW); /* M(EA, word) =3D FCX;*/ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* FCX[19: 0] =3D PCXI[19: 0]; */ env->FCX =3D (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff); /* PCXI =3D new_PCXI; */ @@ -2744,10 +2744,10 @@ void helper_rfm(CPUTriCoreState *env) icr_set_ccpn(env, pcxi_get_pcpn(env)); =20 /* {PCXI, PSW, A[10], A[11]} =3D M(DCX, 4 * word); */ - env->PCXI =3D cpu_ldl_data(env, env->DCX); - psw_write(env, cpu_ldl_data(env, env->DCX+4)); - env->gpr_a[10] =3D cpu_ldl_data(env, env->DCX+8); - env->gpr_a[11] =3D cpu_ldl_data(env, env->DCX+12); + env->PCXI =3D cpu_ldl_le_data(env, env->DCX); + psw_write(env, cpu_ldl_le_data(env, env->DCX+4)); + env->gpr_a[10] =3D cpu_ldl_le_data(env, env->DCX+8); + env->gpr_a[11] =3D cpu_ldl_le_data(env, env->DCX+12); =20 if (tricore_has_feature(env, TRICORE_FEATURE_131)) { env->DBGTCR =3D 0; @@ -2794,7 +2794,7 @@ void helper_svlcx(CPUTriCoreState *env) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2837,7 +2837,7 @@ void helper_svucx(CPUTriCoreState *env) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2887,9 +2887,9 @@ void helper_rslcx(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * wo= rd); */ restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Dhppa; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/hppa/op_helper.c | 44 ++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 0458378abb2..65faf03cd0a 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -107,7 +107,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong a= ddr, target_ulong val, cpu_stb_data_ra(env, addr, val, ra); break; case 2: - cpu_stw_data_ra(env, addr, val, ra); + cpu_stw_be_data_ra(env, addr, val, ra); break; case 1: /* The 3 byte store must appear atomic. */ @@ -115,11 +115,11 @@ static void do_stby_b(CPUHPPAState *env, target_ulong= addr, target_ulong val, atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); - cpu_stw_data_ra(env, addr + 1, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val, ra); } break; default: - cpu_stl_data_ra(env, addr, val, ra); + cpu_stl_be_data_ra(env, addr, val, ra); break; } } @@ -132,7 +132,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, cpu_stb_data_ra(env, addr, val, ra); break; case 6: - cpu_stw_data_ra(env, addr, val, ra); + cpu_stw_be_data_ra(env, addr, val, ra); break; case 5: /* The 3 byte store must appear atomic. */ @@ -140,11 +140,11 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); - cpu_stw_data_ra(env, addr + 1, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val, ra); } break; case 4: - cpu_stl_data_ra(env, addr, val, ra); + cpu_stl_be_data_ra(env, addr, val, ra); break; case 3: /* The 5 byte store must appear atomic. */ @@ -152,7 +152,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, = ra); } else { cpu_stb_data_ra(env, addr, val >> 32, ra); - cpu_stl_data_ra(env, addr + 1, val, ra); + cpu_stl_be_data_ra(env, addr + 1, val, ra); } break; case 2: @@ -160,8 +160,8 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, if (parallel) { atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, = ra); } else { - cpu_stw_data_ra(env, addr, val >> 32, ra); - cpu_stl_data_ra(env, addr + 2, val, ra); + cpu_stw_be_data_ra(env, addr, val >> 32, ra); + cpu_stl_be_data_ra(env, addr + 2, val, ra); } break; case 1: @@ -170,12 +170,12 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, = ra); } else { cpu_stb_data_ra(env, addr, val >> 48, ra); - cpu_stw_data_ra(env, addr + 1, val >> 32, ra); - cpu_stl_data_ra(env, addr + 3, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val >> 32, ra); + cpu_stl_be_data_ra(env, addr + 3, val, ra); } break; default: - cpu_stq_data_ra(env, addr, val, ra); + cpu_stq_be_data_ra(env, addr, val, ra); break; } } @@ -211,12 +211,12 @@ static void do_stby_e(CPUHPPAState *env, target_ulong= addr, target_ulong val, if (parallel) { atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); } else { - cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); } break; case 2: - cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra); break; case 1: cpu_stb_data_ra(env, addr - 1, val >> 24, ra); @@ -239,8 +239,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr - 7, val, 0xffffffffffffff00ull, 7, ra); } else { - cpu_stl_data_ra(env, addr - 7, val >> 32, ra); - cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stl_be_data_ra(env, addr - 7, val >> 32, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); } break; @@ -250,8 +250,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr - 6, val, 0xffffffffffff0000ull, 6, ra); } else { - cpu_stl_data_ra(env, addr - 6, val >> 32, ra); - cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + cpu_stl_be_data_ra(env, addr - 6, val >> 32, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra); } break; case 5: @@ -260,24 +260,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask64(env, addr - 5, val, 0xffffffffff000000ull, 5, ra); } else { - cpu_stl_data_ra(env, addr - 5, val >> 32, ra); + cpu_stl_be_data_ra(env, addr - 5, val >> 32, ra); cpu_stb_data_ra(env, addr - 1, val >> 24, ra); } break; case 4: - cpu_stl_data_ra(env, addr - 4, val >> 32, ra); + cpu_stl_be_data_ra(env, addr - 4, val >> 32, ra); break; case 3: /* The 3 byte store must appear atomic. */ if (parallel) { atomic_store_mask32(env, addr - 3, val >> 32, 0xffffff00u, ra); } else { - cpu_stw_data_ra(env, addr - 3, val >> 48, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 48, ra); cpu_stb_data_ra(env, addr - 1, val >> 40, ra); } break; case 2: - cpu_stw_data_ra(env, addr - 2, val >> 48, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 48, ra); break; case 1: cpu_stb_data_ra(env, addr - 1, val >> 56, ra); --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764193631; cv=none; d=zohomail.com; s=zohoarc; b=HV8sLof6DXuK08sciseV1RDVme3Jen2frSPXlwmAMPJ6klzNjG/qRlb9/VlFpJ+YIsmw+iwvUfje9EqujvueukgzYo6/BlLI6Cx2Ov6cOKOSMGppQlQNwgtDTtR5llqtR5UNs46jORL9vx00OeI2jglhDVJ+RVQH99Kyd+Eep5M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764193631; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Dm68k; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting indentation in do_stack_frame() to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/fpu_helper.c | 12 +++--- target/m68k/op_helper.c | 91 ++++++++++++++++++++-------------------- 2 files changed, 52 insertions(+), 51 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 56012863c85..f49f841d489 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -510,8 +510,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32= _t addr, FPReg *fp, uint32_t high; uint64_t low; =20 - high =3D cpu_ldl_data_ra(env, addr, ra); - low =3D cpu_ldq_data_ra(env, addr + 4, ra); + high =3D cpu_ldl_be_data_ra(env, addr, ra); + low =3D cpu_ldq_be_data_ra(env, addr + 4, ra); =20 fp->l.upper =3D high >> 16; fp->l.lower =3D low; @@ -522,8 +522,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32= _t addr, FPReg *fp, static int cpu_st_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, uintptr_t ra) { - cpu_stl_data_ra(env, addr, fp->l.upper << 16, ra); - cpu_stq_data_ra(env, addr + 4, fp->l.lower, ra); + cpu_stl_be_data_ra(env, addr, fp->l.upper << 16, ra); + cpu_stq_be_data_ra(env, addr + 4, fp->l.lower, ra); =20 return 12; } @@ -533,7 +533,7 @@ static int cpu_ld_float64_ra(CPUM68KState *env, uint32_= t addr, FPReg *fp, { uint64_t val; =20 - val =3D cpu_ldq_data_ra(env, addr, ra); + val =3D cpu_ldq_be_data_ra(env, addr, ra); fp->d =3D float64_to_floatx80(*(float64 *)&val, &env->fp_status); =20 return 8; @@ -545,7 +545,7 @@ static int cpu_st_float64_ra(CPUM68KState *env, uint32_= t addr, FPReg *fp, float64 val; =20 val =3D floatx80_to_float64(fp->d, &env->fp_status); - cpu_stq_data_ra(env, addr, *(uint64_t *)&val, ra); + cpu_stq_be_data_ra(env, addr, *(uint64_t *)&val, ra); =20 return 8; } diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index e9c20a8e032..7139a8445d4 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -32,8 +32,8 @@ static void cf_rte(CPUM68KState *env) uint32_t fmt; =20 sp =3D env->aregs[7]; - fmt =3D cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); - env->pc =3D cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); + fmt =3D cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); sp |=3D (fmt >> 28) & 3; env->aregs[7] =3D sp + 8; =20 @@ -48,13 +48,13 @@ static void m68k_rte(CPUM68KState *env) =20 sp =3D env->aregs[7]; throwaway: - sr =3D cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + sr =3D cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 2; - env->pc =3D cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 4; if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) { /* all except 68000 */ - fmt =3D cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + fmt =3D cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 2; switch (fmt >> 12) { case 0: @@ -250,12 +250,12 @@ static void cf_interrupt_all(CPUM68KState *env, int i= s_hw) /* ??? This could cause MMU faults. */ sp &=3D ~3; sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0); sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0); env->aregs[7] =3D sp; /* Jump to vector. */ - env->pc =3D cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, = 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_ID= X, 0); =20 do_plugin_vcpu_interrupt_cb(cs, retaddr); } @@ -270,24 +270,25 @@ static inline void do_stack_frame(CPUM68KState *env, = uint32_t *sp, switch (format) { case 4: *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0); *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); break; case 3: case 2: *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); break; } *sp -=3D 2; - cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index = << 2), - MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, *sp, + (format << 12) + (cs->exception_index << 2), + MMU_KERNEL_IDX, 0); } *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0); *sp -=3D 2; - cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0); } =20 static void m68k_interrupt_all(CPUM68KState *env, int is_hw) @@ -346,49 +347,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int= is_hw) env->mmu.fault =3D true; /* push data 3 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* push data 2 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* push data 1 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 1 / push data 0 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 1 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 data */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 data */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); /* fault address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); /* write back 1 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* special status word */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0); /* effective address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); =20 do_stack_frame(env, &sp, 7, oldsr, 0, env->pc); env->mmu.fault =3D false; @@ -436,7 +437,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int i= s_hw) =20 env->aregs[7] =3D sp; /* Jump to vector. */ - env->pc =3D cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, = 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_ID= X, 0); =20 do_plugin_vcpu_interrupt_cb(cs, last_pc); } @@ -784,11 +785,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2) int16_t l1, l2; uintptr_t ra =3D GETPC(); =20 - l1 =3D cpu_lduw_data_ra(env, a1, ra); - l2 =3D cpu_lduw_data_ra(env, a2, ra); + l1 =3D cpu_lduw_be_data_ra(env, a1, ra); + l2 =3D cpu_lduw_be_data_ra(env, a2, ra); if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stw_data_ra(env, a1, u1, ra); - cpu_stw_data_ra(env, a2, u2, ra); + cpu_stw_be_data_ra(env, a1, u1, ra); + cpu_stw_be_data_ra(env, a2, u2, ra); } =20 if (c1 !=3D l1) { @@ -845,11 +846,11 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs= , uint32_t a1, uint32_t a2, } } else { /* We're executing in a serial context -- no need to be atomic. */ - l1 =3D cpu_ldl_data_ra(env, a1, ra); - l2 =3D cpu_ldl_data_ra(env, a2, ra); + l1 =3D cpu_ldl_be_data_ra(env, a1, ra); + l2 =3D cpu_ldl_be_data_ra(env, a2, ra); if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stl_data_ra(env, a1, u1, ra); - cpu_stl_data_ra(env, a2, u2, ra); + cpu_stl_be_data_ra(env, a1, u1, ra); + cpu_stl_be_data_ra(env, a2, u2, ra); } } =20 @@ -951,12 +952,12 @@ static uint64_t bf_load(CPUM68KState *env, uint32_t a= ddr, int blen, case 0: return cpu_ldub_data_ra(env, addr, ra); case 1: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); case 2: case 3: - return cpu_ldl_data_ra(env, addr, ra); + return cpu_ldl_be_data_ra(env, addr, ra); case 4: - return cpu_ldq_data_ra(env, addr, ra); + return cpu_ldq_be_data_ra(env, addr, ra); default: g_assert_not_reached(); } @@ -970,14 +971,14 @@ static void bf_store(CPUM68KState *env, uint32_t addr= , int blen, cpu_stb_data_ra(env, addr, data, ra); break; case 1: - cpu_stw_data_ra(env, addr, data, ra); + cpu_stw_be_data_ra(env, addr, data, ra); break; case 2: case 3: - cpu_stl_data_ra(env, addr, data, ra); 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Ds390x; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------ target/s390x/tcg/vec_helper.c | 8 +++--- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 24675fc818d..482c3febf91 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XStat= e *env, uint64_t addr, case 1: return cpu_ldub_data_ra(env, addr, ra); case 2: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); default: abort(); } @@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *en= v, uint64_t addr, cpu_stb_data_ra(env, addr, value, ra); break; case 2: - cpu_stw_data_ra(env, addr, value, ra); + cpu_stw_be_data_ra(env, addr, value, ra); break; default: abort(); @@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) env->cc_op =3D 2; return; } - v =3D cpu_lduw_data_ra(env, str + len, ra); + v =3D cpu_lduw_be_data_ra(env, str + len, ra); if (v =3D=3D c) { /* Character found. Set R1 to the location; R2 is unmodified.= */ env->cc_op =3D 1; @@ -1022,7 +1022,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uin= t64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - env->aregs[i] =3D cpu_ldl_data_ra(env, a2, ra); + env->aregs[i] =3D cpu_ldl_be_data_ra(env, a2, ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1042,7 +1042,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, a2, env->aregs[i], ra); + cpu_stl_be_data_ra(env, a2, env->aregs[i], ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1363,7 +1363,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, =20 /* Process full words as available. */ for (len =3D 0; len + 4 <=3D max_len; len +=3D 4, src +=3D 4) { - cksm +=3D (uint32_t)cpu_ldl_data_ra(env, src, ra); + cksm +=3D (uint32_t)cpu_ldl_be_data_ra(env, src, ra); } =20 switch (max_len - len) { @@ -1372,11 +1372,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, len +=3D 1; break; case 2: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; len +=3D 2; break; case 3: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; cksm +=3D cpu_ldub_data_ra(env, src + 2, ra) << 8; len +=3D 3; break; @@ -1955,7 +1955,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint64_t val =3D cpu_ldq_data_ra(env, src, ra); + uint64_t val =3D cpu_ldq_be_data_ra(env, src, ra); if (env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; } @@ -1992,7 +1992,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint32_t val =3D cpu_ldl_data_ra(env, src, ra); + uint32_t val =3D cpu_ldl_be_data_ra(env, src, ra); uint64_t val64 =3D deposit64(env->cregs[i], 0, 32, val); if ((uint32_t)env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; @@ -2028,7 +2028,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stq_data_ra(env, dest, env->cregs[i], ra); + cpu_stq_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint64_t); =20 if (i =3D=3D r3) { @@ -2048,7 +2048,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, dest, env->cregs[i], ra); + cpu_stl_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint32_t); =20 if (i =3D=3D r3) { @@ -2065,7 +2065,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64= _t real_addr) real_addr =3D wrap_address(env, real_addr) & TARGET_PAGE_MASK; =20 for (i =3D 0; i < TARGET_PAGE_SIZE; i +=3D 8) { - cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); } =20 return 0; @@ -2324,11 +2324,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, = uint64_t r2, uint32_t m4) for (i =3D 0; i < entries; i++) { /* addresses are not wrapped in 24/31bit mode but table index = is */ raddr =3D table + ((index + i) & 0x7ff) * sizeof(entry); - entry =3D cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); + entry =3D cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); if (!(entry & REGION_ENTRY_I)) { /* we are allowed to not store if already invalid */ entry |=3D REGION_ENTRY_I; - cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); } } } @@ -2355,9 +2355,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, u= int64_t vaddr, pte_addr +=3D VADDR_PAGE_TX(vaddr) * 8; =20 /* Mark the page table entry as invalid */ - pte =3D cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); + pte =3D cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); pte |=3D PAGE_ENTRY_I; - cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); =20 /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ @@ -2695,7 +2695,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 0; } - s0 =3D cpu_lduw_data_ra(env, addr, ra); + s0 =3D cpu_lduw_be_data_ra(env, addr, ra); if ((s0 & 0xfc00) !=3D 0xd800) { /* one word character */ l =3D 2; @@ -2706,7 +2706,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - s1 =3D cpu_lduw_data_ra(env, addr + 2, ra); + s1 =3D cpu_lduw_be_data_ra(env, addr + 2, ra); c =3D extract32(s0, 6, 4) + 1; c =3D (c << 6) | (s0 & 0x3f); c =3D (c << 10) | (s1 & 0x3ff); @@ -2730,7 +2730,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - c =3D cpu_ldl_data_ra(env, addr, ra); + c =3D cpu_ldl_be_data_ra(env, addr, ra); if ((c >=3D 0xd800 && c <=3D 0xdbff) || c > 0x10ffff) { /* invalid unicode character */ return 2; @@ -2792,7 +2792,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 1; } - cpu_stw_data_ra(env, addr, c, ra); + cpu_stw_be_data_ra(env, addr, c, ra); *olen =3D 2; } else { /* two word character */ @@ -2802,8 +2802,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, d1 =3D 0xdc00 | extract32(c, 0, 10); d0 =3D 0xd800 | extract32(c, 10, 6); d0 =3D deposit32(d0, 6, 4, extract32(c, 16, 5) - 1); - cpu_stw_data_ra(env, addr + 0, d0, ra); - cpu_stw_data_ra(env, addr + 2, d1, ra); + cpu_stw_be_data_ra(env, addr + 0, d0, ra); + cpu_stw_be_data_ra(env, addr + 2, d1, ra); *olen =3D 4; } =20 @@ -2816,7 +2816,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 1; } - cpu_stl_data_ra(env, addr, c, ra); + cpu_stl_be_data_ra(env, addr, c, ra); *olen =3D 4; return -1; } diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index 46ec4a947dd..304745c971b 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t a= ddr, uint64_t bytes) if (likely(bytes >=3D 16)) { uint64_t t0, t1; =20 - t0 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t0 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); addr =3D wrap_address(env, addr + 8); - t1 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t1 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); s390_vec_write_element64(v1, 0, t0); s390_vec_write_element64(v1, 1, t1); } else { @@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, u= int64_t addr, probe_write_access(env, addr, MIN(bytes, 16), GETPC()); =20 if (likely(bytes >=3D 16)) { - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETP= C()); addr =3D wrap_address(env, addr + 8); - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETP= C()); } else { int i; =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Dsparc; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/sparc/ldst_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2c63eb9e036..bd0257d313a 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1228,13 +1228,13 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, ret =3D cpu_ldub_data(env, addr); break; case 2: - ret =3D cpu_lduw_data(env, addr); + ret =3D cpu_lduw_be_data(env, addr); break; case 4: - ret =3D cpu_ldl_data(env, addr); + ret =3D cpu_ldl_be_data(env, addr); break; case 8: - ret =3D cpu_ldq_data(env, addr); + ret =3D cpu_ldq_be_data(env, addr); break; default: g_assert_not_reached(); --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764204858; cv=none; d=zohomail.com; s=zohoarc; b=D/S784NCx+FmygTRLF4Vd2WXiC614pfgt1aX2dgqf2xV9fCPQhmzZGvKAOqOvcSUTfy2kujm2fkZovbJPjtis1rwp9eq1VuIQa0c+4GJQlVj+jRHUXD4XGroHc+ahfjlIYuXtMI3yRxArutdk7MQWLX7ruUmhgfrfx7UQQiQKbM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764204858; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6h9P9iv/p2bvUhSVVmHLosiz6MFHN9Sri9gbONaHVNg=; b=eROvD/PJD22NMcLILMxB59mxMBKLQBXLJI7boBnLv+0Zaf0kGxoq1PvTVPsTxyIl388MomxIGvUWh83W0QQJ0XaWcKdkeb3Ih6uopxs0aaF939o2hr6GVIKd5ag2jTyc43P1Xr2zeumRBSMMyM8xN0LN8jOjiXr98x0/eyCDSBM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176420485784621.989128726793183; Wed, 26 Nov 2025 16:54:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM2p-0003la-6Z; Wed, 26 Nov 2025 15:23:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM2n-0003gJ-Qf for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:17 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM2l-0002TA-OW for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:17 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-47755de027eso687545e9.0 for ; Wed, 26 Nov 2025 12:23:15 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Set the return address argument. See commit 852d481faf7 ("SH: Improve movca.l/ocbi emulation") for more context on this code. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/op_helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 557b1bf4972..669bc84cb64 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -136,6 +136,8 @@ void helper_discard_movcal_backup(CPUSH4State *env) =20 void helper_ocbi(CPUSH4State *env, uint32_t address) { + unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx); memory_content **current =3D &(env->movcal_backup); while (*current) { @@ -143,7 +145,8 @@ void helper_ocbi(CPUSH4State *env, uint32_t address) if ((a & ~0x1F) =3D=3D (address & ~0x1F)) { memory_content *next =3D (*current)->next; - cpu_stl_data(env, a, (*current)->value); + + cpu_stl_mmu(env, a, (*current)->value, oi, GETPC()); =20 if (next =3D=3D NULL) { --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764188847; cv=none; d=zohomail.com; s=zohoarc; b=J3zxC2rsrpuDruSCdLPt6eD6GFPGqSCke3qX8uVbyrVLpSF/PbkTKTcVfIQM7tNeowjTrl7HeKN9x+mms+so+a3WpDeWCjvG1hFbZH5KEYRNC4RgYQle/gffwSbgzSAJp448Kqf+ViHtWK3HkFXnJ+CMHJrmXLnRVTPkGIWjkRg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764188847; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HDoRFtIf4DtlaKu8FqeCDNwKdTIWIuyOpEl6R55IExI=; b=RosioD3u+Ce/tGvGVowUc1lPK47d77uig6HzwMgwO1X9wruvQ5UE+pzxoGCsTyFTBqpTK08A/Y2ZvRZr9+CdlTAsYerzr1wTkUmTv4mAErKPcMnKhKlwzLkAv9rQIsIAfAbIvJt1mqPB79pNnMflDpVBwjHjij63Qxb/ED1XCm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764188847527106.5190938121658; Wed, 26 Nov 2025 12:27:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM37-0003wy-6n; Wed, 26 Nov 2025 15:23:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM2z-0003pY-MY for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:30 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM2t-0002UV-EQ for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:28 -0500 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-42b2dc17965so194408f8f.3 for ; Wed, 26 Nov 2025 12:23:22 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Per the "MIPS=C2=AE SIMD Architecture" (MD00926 rev 1.03): 3.1 Registers Layout MSA vectors are stored in memory starting from the 0th element at the lowest byte address. The byte order of each element follows the big- or little-endian convention of the system configuration. Use the explicit big-endian variants of cpu_ld/st_data*(). Running files in tests/tcg/mips/user/ase/msa shows: NLOC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms | NLOC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.22 ms | NLOC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLOC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLZC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | NLZC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLZC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms | NLZC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCNT.B | PASS: 80 | FAIL: 0 | elapsed time: 0.17 ms | PCNT.H | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | PCNT.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCNT.D | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | BINSL.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | BINSR.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSR.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | BINSR.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | BINSR.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BMNZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | BMZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | BSEL.V | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms | BCLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | BNEG.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BNEG.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | BNEG.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BNEG.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | BSET.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.D | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MADD_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms | MADD_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.83 ms | MADDR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | MADDR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUB_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUB_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUBR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MUL_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MUL_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULR_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULR_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | FMAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms | FMAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMAX.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | FMAX.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms | FMIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMIN.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | FMIN.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADD_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ADDS_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | ADDS_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | ADDS_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.80 ms | ADDS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | HADD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | AVE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | AVER_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | AVER_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CEQ.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CEQ.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CEQ.W | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | CEQ.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | CLT_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLT_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLT_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLT_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | DIV_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | DIV_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | DIV_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.39 ms | DIV_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | DIV_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | DOTP_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | DOTP_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DPADD_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | DPADD_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | DPADD_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | DPSUB_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | DPSUB_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | DPSUB_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MAX_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | MAX_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | MAX_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MAX_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MIN_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MIN_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MIN_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MOD_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MOD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MOD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms | MOD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | MOD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MADDV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MADDV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.63 ms | MADDV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MADDV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUBV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | MSUBV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | MULV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MULV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.44 ms | ASUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ASUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | HSUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | HSUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | SUBS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | SUBS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBSUS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBSUU_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVEV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | ILVEV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ILVEV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | ILVEV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | ILVOD.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ILVL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ILVR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AND.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | NOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | OR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | XOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MOVE.V | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCKEV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | PCKEV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | PCKEV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.68 ms | PCKEV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | PCKOD.B | PASS: 112 | FAIL: 0 | elapsed time: 0.61 ms | PCKOD.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | PCKOD.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | PCKOD.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | VSHF.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | VSHF.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | VSHF.W | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | VSHF.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | SLL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | SLL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SLL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SLL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | SRA.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRA.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SRA.W | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms | SRA.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRAR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRAR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRAR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRAR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SRLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa_helper.c | 51 ++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index f554b3d10ee..d6ce17abf9a 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8231,8 +8231,8 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, uint64_t d0, d1; =20 /* Load 8 bytes at a time. Vector element ordering makes this LE. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); pwd->d[0] =3D d0; pwd->d[1] =3D d1; } @@ -8248,9 +8248,9 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, * Load 8 bytes at a time. Use little-endian load, then for * big-endian target, we must then swap the four halfwords. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { d0 =3D bswap16x4(d0); d1 =3D bswap16x4(d1); } @@ -8269,9 +8269,9 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, * Load 8 bytes at a time. Use little-endian load, then for * big-endian target, we must then bswap the two words. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { d0 =3D bswap32x2(d0); d1 =3D bswap32x2(d1); } @@ -8286,8 +8286,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 - d0 =3D cpu_ldq_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_data_ra(env, addr + 8, ra); + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { + d0 =3D bswap64(d0); + d1 =3D bswap64(d1); + } pwd->d[0] =3D d0; pwd->d[1] =3D d1; } @@ -8320,8 +8324,8 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, ra); =20 /* Store 8 bytes at a time. Vector element ordering makes this LE. */ - cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); + cpu_stq_be_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_be_data_ra(env, addr + 8, pwd->d[1], ra); } =20 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8337,12 +8341,12 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, /* Store 8 bytes at a time. See helper_msa_ld_h. */ d0 =3D pwd->d[0]; d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { + if (!mips_env_is_bigendian(env)) { d0 =3D bswap16x4(d0); d1 =3D bswap16x4(d1); } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8358,12 +8362,12 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, /* Store 8 bytes at a time. See helper_msa_ld_w. */ d0 =3D pwd->d[0]; d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { + if (!mips_env_is_bigendian(env)) { d0 =3D bswap32x2(d0); d1 =3D bswap32x2(d1); } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8372,9 +8376,16 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); =20 - cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; + if (!mips_env_is_bigendian(env)) { + d0 =3D bswap64(d0); + d1 =3D bswap64(d1); + } + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764208538; cv=none; d=zohomail.com; s=zohoarc; b=mN+zsDIdfoUNvtZzk9xNgDsyRNCmnhqJ0tUTYvHx5QjKqiRb9DMcazcNPVRAUXlwANR4lbAlweSFpgCwfLf7kKszpSVu6QZ93AycaBcdkF3j9bMF+2lDTMOp/KT44ZCJCVIvlK+tXdpzUKLnsEQ9+4H0AvUHE13LoGfoGONOrrQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764208538; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vceLppWO/UrgbDY1SaGLlR83M8KLMGCrBYU9iCa1jJA=; b=hvltpK9gzej0fVozLlys5Ud0pF2AG8gdgZ3owgm74A0DUtcS5T9PhxWknHKEKQGmDvbImCLJbFsL08lgg/9t4DtbiXknUQ9Eqs2lcJorGV7gFWKiHHCfCtAZC9U28gPU+ltOC4Asg6Rg5odxhTQkNxZFG5Tzt4gTFW9r2lZBdVc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764208538620619.0069466213779; Wed, 26 Nov 2025 17:55:38 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM3A-00044g-SX; Wed, 26 Nov 2025 15:23:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM34-0003tk-IN for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:35 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM32-0002VW-O8 for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:34 -0500 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-47118259fd8so738445e9.3 for ; Wed, 26 Nov 2025 12:23:29 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 10319bf03a6..c1c4a60cf3f 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -29,7 +29,7 @@ =20 #ifndef CONFIG_USER_ONLY =20 -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ +#define HELPER_LD_ATOMIC(name, almask, cpu_load) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ if (arg & almask) { = \ @@ -41,12 +41,23 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int mem_idx) \ env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ GETPC()); = \ env->lladdr =3D arg; = \ - env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ + env->llval =3D cpu_load(env, arg, mem_idx, GETPC()); = \ return env->llval; = \ } -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) + +static target_ulong loads4(CPUMIPSState *env, target_ulong arg, + unsigned mem_idx, uintptr_t ra) +{ + return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra); +} +HELPER_LD_ATOMIC(ll, 0x3, loads4) #ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +static target_ulong loadu8(CPUMIPSState *env, target_ulong arg, + unsigned mem_idx, uintptr_t ra) +{ + return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra); +} +HELPER_LD_ATOMIC(lld, 0x7, loadu8) #endif #undef HELPER_LD_ATOMIC =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764194247; cv=none; d=zohomail.com; s=zohoarc; b=PU2MjDAODkM8n7iXqJGlO4SQ3oL5gOk3x3l9fG70UZsDYWfuz/y6lHw2mA5edqOqiaM21xTHTVEEQ6H49Nk9dsEtGjeK4ltIzmUBJDn8guknRPc3rgMAMNv0+20mzQ66S7SsYx/STR/6XX+aBLoD2WMGRfMMIIomv4DiJLSRZkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764194247; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=MRknozkFZhdeVPmoAAlQwK+1qO2Yf+FkoXswe+IPjmc=; b=W9j8WFxm9u7fowMsdoOoZDb1ITJqGmzt/Q18HL2hutyTRonP9Y7b0HQkyIPpsbjkqsdhd79Q0qkcf+a1xM4HuGU99UcQHUNXrU7CGQsB1cOO+CL4Wj62vcflGmqNnKgZVJRW2okiT+WO6bmxVAKVfInjJAYS3pRytQ21M9YGPjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764194247668863.2445093337888; Wed, 26 Nov 2025 13:57:27 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM3C-0004Ig-I4; Wed, 26 Nov 2025 15:23:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM39-00042z-Ag for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:40 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM37-0002Wi-4B for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:39 -0500 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-42bb288c17bso129293f8f.2 for ; Wed, 26 Nov 2025 12:23:36 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 4 +++- target/mips/tcg/translate.c | 9 +++++---- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index c1c4a60cf3f..013cd825dac 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -30,8 +30,10 @@ #ifndef CONFIG_USER_ONLY =20 #define HELPER_LD_ATOMIC(name, almask, cpu_load) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_= idx)\ { = \ + MemOpIdx oi =3D memop_idx; = \ + unsigned mem_idx =3D get_mmuidx(oi); = \ if (arg & almask) { = \ if (!(env->hflags & MIPS_HFLAG_DM)) { = \ env->CP0_BadVAddr =3D arg; = \ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 54849e9ff1a..c476271d6d5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1932,16 +1932,17 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1= , int mem_idx, \ tcg_gen_st_tl(ret, tcg_env, offsetof(CPUMIPSState, llval)); = \ } #else -#define OP_LD_ATOMIC(insn, ignored_memop) = \ +#define OP_LD_ATOMIC(insn, mop) = \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, = \ DisasContext *ctx) = \ { = \ - gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(mem_idx)); = \ + MemOpIdx oi =3D make_memop_idx(mop | mo_endian(ctx), mem_idx); = \ + gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); = \ } #endif -OP_LD_ATOMIC(ll, mo_endian(ctx) | MO_SL); +OP_LD_ATOMIC(ll, MO_SL); #if defined(TARGET_MIPS64) -OP_LD_ATOMIC(lld, mo_endian(ctx) | MO_UQ); +OP_LD_ATOMIC(lld, MO_UQ); #endif #undef OP_LD_ATOMIC =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764193267; cv=none; d=zohomail.com; s=zohoarc; b=UZiDmJSjY0jjEvke7UVlX7ig/9PiPxUo5A2FbTmwkv62p+F/U86zuer7T+LngB7nDtmFjz1gdn+969n8AhgTBvBgw+Ib8poAcdPfhxA11CWDW7USjPyZKI1mRxAqFEqW1yx1LSWoNZfwNKh+NzipmBzu80JtsV187wz9BTCEmIo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764193267; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7fTaxNly4DgcgF2+VUNXcxi8mtgdCJ/FSAiYjjUPHnU=; b=Rn+/2eOFhHq8h1HCkByagqCnjdX6q9sxNyrFT4r19bGZaMzJJrg8LI3bHWVauGT9G0HGHXP2R1qmyCZ+W4ILZTXpF64oVK/awyadXTTGms7yVxU47PuPLiNlH9//KDiYOzHhLsC6BPvOwz0oUW11bVHRiB4UqabRI36+QWj6moo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764193266977418.44083806084495; Wed, 26 Nov 2025 13:41:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM3J-0004l5-AD; Wed, 26 Nov 2025 15:23:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM3H-0004bd-36 for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:47 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM3E-0002YX-FB for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:46 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-47774d3536dso1468775e9.0 for ; Wed, 26 Nov 2025 12:23:44 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Use it to check the address alignment. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 013cd825dac..bef384575c2 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -29,12 +29,14 @@ =20 #ifndef CONFIG_USER_ONLY =20 -#define HELPER_LD_ATOMIC(name, almask, cpu_load) = \ +#define HELPER_LD_ATOMIC(name, cpu_load) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_= idx)\ { = \ MemOpIdx oi =3D memop_idx; = \ unsigned mem_idx =3D get_mmuidx(oi); = \ - if (arg & almask) { = \ + MemOp op =3D get_memop(oi); = \ + unsigned size =3D memop_size(op); = \ + if (arg & (size - 1)) { = \ if (!(env->hflags & MIPS_HFLAG_DM)) { = \ env->CP0_BadVAddr =3D arg; = \ } = \ @@ -52,14 +54,14 @@ static target_ulong loads4(CPUMIPSState *env, target_ul= ong arg, { return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra); } -HELPER_LD_ATOMIC(ll, 0x3, loads4) +HELPER_LD_ATOMIC(ll, loads4) #ifdef TARGET_MIPS64 static target_ulong loadu8(CPUMIPSState *env, target_ulong arg, unsigned mem_idx, uintptr_t ra) { return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra); } -HELPER_LD_ATOMIC(lld, 0x7, loadu8) +HELPER_LD_ATOMIC(lld, loadu8) #endif #undef HELPER_LD_ATOMIC =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764188820; cv=none; d=zohomail.com; s=zohoarc; b=WktscmT4nsuTUNUjAIhW+spIHukzxg33/RciSsQeOaWnHraOuqyGwuD3TE3yq7Okwr6LOlt3OODpMsVFesXV2/155x0cc+woBaJ045PJ73IR7CNnh+LrMInJrZNDw2nZtpIxyYJwZfp4m5JIewFX5BPSJZCOwwBnfNT8SAuTMCE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764188820; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mT9mHQh/gZZ2dKo4MF+31YkpX2DzjKOcapwS4tgx374=; b=W+cOLG5dNVKAHspywmbcMO1WPLoVlKbvhkOJmkdNJZrQFP8vhiPwxVQjeXds9vC97JmENzF7pQe3Qli3rpgYZw8zNHhbqMa8QeRq3CTO240Rlf4erQAkmq2lBsDy8ZHPjm0RNEVhCXH+vBkiFwFJfvfm5BOBnMj3LyE/kW33xIg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764188820310629.6168677750456; Wed, 26 Nov 2025 12:27:00 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM3T-0005A2-En; Wed, 26 Nov 2025 15:23:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM3Q-00051d-Pg for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:57 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM3N-0002bZ-VK for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:23:56 -0500 Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-42b3c965ca9so124997f8f.1 for ; Wed, 26 Nov 2025 12:23:51 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 11 +++++------ target/mips/tcg/translate.c | 2 +- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index bef384575c2..85f73c9081d 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -33,7 +33,6 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_= idx)\ { = \ MemOpIdx oi =3D memop_idx; = \ - unsigned mem_idx =3D get_mmuidx(oi); = \ MemOp op =3D get_memop(oi); = \ unsigned size =3D memop_size(op); = \ if (arg & (size - 1)) { = \ @@ -45,21 +44,21 @@ target_ulong helper_##name(CPUMIPSState *env, target_ul= ong arg, int memop_idx)\ env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ GETPC()); = \ env->lladdr =3D arg; = \ - env->llval =3D cpu_load(env, arg, mem_idx, GETPC()); = \ + env->llval =3D cpu_load(env, arg, oi, GETPC()); = \ return env->llval; = \ } =20 static target_ulong loads4(CPUMIPSState *env, target_ulong arg, - unsigned mem_idx, uintptr_t ra) + MemOpIdx oi, uintptr_t ra) { - return (target_long)(int32_t)cpu_ldl_mmuidx_ra(env, arg, mem_idx, ra); + return (target_long)(int32_t)cpu_ldl_mmu(env, arg, oi, ra); } HELPER_LD_ATOMIC(ll, loads4) #ifdef TARGET_MIPS64 static target_ulong loadu8(CPUMIPSState *env, target_ulong arg, - unsigned mem_idx, uintptr_t ra) + MemOpIdx oi, uintptr_t ra) { - return (target_ulong)cpu_ldq_mmuidx_ra(env, arg, mem_idx, ra); + return (target_ulong)cpu_ldq_mmu(env, arg, oi, ra); } HELPER_LD_ATOMIC(lld, loadu8) #endif diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index c476271d6d5..bb9e91069d6 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1936,7 +1936,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, = int mem_idx, \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, = \ DisasContext *ctx) = \ { = \ - MemOpIdx oi =3D make_memop_idx(mop | mo_endian(ctx), mem_idx); = \ + MemOpIdx oi =3D make_memop_idx(mop | mo_endian(ctx) | MO_UNALN, mem_id= x);\ gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); = \ } #endif --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764188821; cv=none; d=zohomail.com; s=zohoarc; b=huIMiGHJmcmtRqDZXBIQWxfRukVvcJxpkjqLWi9rL6LX1Cz4MA/8UvkZGsgn2XetBYa3JVZZ7t8VTWvt27NgDIDdZdQvFVqIgRfjIvETmLFsu/NoQuBXlVmOAGdENT6HY0TZtH0ynVk1PxwQsOI/KoTacRBRykNR8aZgg1kxOrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764188821; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=EfwJWQq9l5xaVFukygP6b1kdZjjf6Z4zWUecnl8bZmA=; b=Kk8eDAQ44hqWYafCWHHlR2QALFOC5SaatQn00nRmd6bob+chniFvJ2qqD53CRZv7jm1GBvWEnizlywB533z+kwvdpFQFKUi4QRTlgzXE9GLH1HTtEjl+2PzE4UkbQEFBekJAQJWWtLTujB+gKArfa8DMR5cNf4tVoHng1YlVEhs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764188821026373.2519668639819; Wed, 26 Nov 2025 12:27:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM3Z-0005a2-P8; Wed, 26 Nov 2025 15:24:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM3U-0005KM-V0 for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:01 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM3S-0002cf-Fe for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:00 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-47798ded6fcso534415e9.1 for ; Wed, 26 Nov 2025 12:23:57 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 51 +++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index 85f73c9081d..f3652034afa 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -29,23 +29,26 @@ =20 #ifndef CONFIG_USER_ONLY =20 -#define HELPER_LD_ATOMIC(name, cpu_load) = \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int memop_= idx)\ -{ = \ - MemOpIdx oi =3D memop_idx; = \ - MemOp op =3D get_memop(oi); = \ - unsigned size =3D memop_size(op); = \ - if (arg & (size - 1)) { = \ - if (!(env->hflags & MIPS_HFLAG_DM)) { = \ - env->CP0_BadVAddr =3D arg; = \ - } = \ - do_raise_exception(env, EXCP_AdEL, GETPC()); = \ - } = \ - env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , \ - GETPC()); = \ - env->lladdr =3D arg; = \ - env->llval =3D cpu_load(env, arg, oi, GETPC()); = \ - return env->llval; = \ +static target_ulong do_ll(target_ulong (*cpu_load_mmu)(CPUMIPSState *, + target_ulong, + MemOpIdx, uintptr_t= ), + CPUMIPSState *env, target_ulong arg, + MemOpIdx oi, uintptr_t ra) +{ + MemOp op =3D get_memop(oi); + unsigned size =3D memop_size(op); + + if (arg & (size - 1)) { + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr =3D arg; + } + do_raise_exception(env, EXCP_AdEL, ra); + } + env->CP0_LLAddr =3D cpu_mips_translate_address(env, arg, MMU_DATA_LOAD= , ra); + env->llval =3D cpu_load_mmu(env, arg, oi, ra); + env->lladdr =3D arg; + + return env->llval; } =20 static target_ulong loads4(CPUMIPSState *env, target_ulong arg, @@ -53,16 +56,24 @@ static target_ulong loads4(CPUMIPSState *env, target_ul= ong arg, { return (target_long)(int32_t)cpu_ldl_mmu(env, arg, oi, ra); } -HELPER_LD_ATOMIC(ll, loads4) + +target_ulong helper_ll(CPUMIPSState *env, target_ulong arg, int memop_idx) +{ + return do_ll(loads4, env, arg, memop_idx, GETPC()); +} + #ifdef TARGET_MIPS64 static target_ulong loadu8(CPUMIPSState *env, target_ulong arg, MemOpIdx oi, uintptr_t ra) { return (target_ulong)cpu_ldq_mmu(env, arg, oi, ra); } -HELPER_LD_ATOMIC(lld, loadu8) + +target_ulong helper_lld(CPUMIPSState *env, target_ulong arg, int memop_idx) +{ + return do_ll(loadu8, env, arg, memop_idx, GETPC()); +} #endif -#undef HELPER_LD_ATOMIC =20 #endif /* !CONFIG_USER_ONLY */ =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764199738; cv=none; d=zohomail.com; s=zohoarc; b=JFa5iDrqs2LurtcKKHf4j/kTrfn8Y2z0U9slSrEpSc8Q4t+pamwg8l7JVtwykaO2YCrSuMdZUpgvIKl5IqruWmGmKCmJCgDdsWSltrR9uIT901RGxT17sqFTssk98vXn4x8dbL34mxo9sC1RHHPqqw0Aog7Z5Ata2+0g6MYGrzE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764199738; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=OFt8xjFc2jyIEqMIXlWNQ0K51n6YypSN5PbrP8ZEBgM=; b=AovOvTvxj8hEbtcjzqPSNCeX0BS6chEImYRVi0nX50qBaBVwJCwhQOUMiMAJh65WqNN/CRkcOoPtQ0uuapedTMSCqj9BjHmWoDo153qYMn1Mn4w+RCwrlSogS16z3jiV/FUBDU/qdud644P11tkUYj3RXzwlqAK+PB+DeSuu48U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17641997386231021.7562929873693; Wed, 26 Nov 2025 15:28:58 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM40-0005rP-2u; Wed, 26 Nov 2025 15:24:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM3c-0005h4-E3 for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:10 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM3Z-0002e3-8s for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:07 -0500 Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-477a2ab455fso972165e9.3 for ; Wed, 26 Nov 2025 12:24:04 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Expand MO_TE to mo_endian_env(env). Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/ldst_helper.c | 49 +++++++++++++++++++---------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index f3652034afa..716b60e3a39 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -237,8 +237,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, = target_ulong arg2, static const int multiple_regs[] =3D { 16, 17, 18, 19, 20, 21, 22, 23, 30 = }; =20 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) + uint32_t mmu_idx) { + MemOp op =3D mo_endian_env(env) | MO_UL | MO_UNALN; + MemOpIdx oi =3D make_memop_idx(op, mmu_idx); target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 @@ -247,20 +249,22 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, =20 for (i =3D 0; i < base_reglist; i++) { env->active_tc.gpr[multiple_regs[i]] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()= ); + (target_long)cpu_ldl_mmu(env, addr, oi, GETPC()); addr +=3D 4; } } =20 if (do_r31) { env->active_tc.gpr[31] =3D - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + (target_long)cpu_ldl_mmu(env, addr, oi, GETPC()); } } =20 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) + uint32_t mmu_idx) { + MemOp op =3D mo_endian_env(env) | MO_UL | MO_UNALN; + MemOpIdx oi =3D make_memop_idx(op, mmu_idx); target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; =20 @@ -268,58 +272,59 @@ void helper_swm(CPUMIPSState *env, target_ulong addr,= target_ulong reglist, target_ulong i; =20 for (i =3D 0; i < base_reglist; i++) { - cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); + cpu_stl_mmu(env, addr, env->active_tc.gpr[multiple_regs[i]], + oi, GETPC()); addr +=3D 4; } } =20 if (do_r31) { - cpu_stl_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + cpu_stl_mmu(env, addr, env->active_tc.gpr[31], oi, GETPC()); } } =20 #if defined(TARGET_MIPS64) void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) + uint32_t mmu_idx) { target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; + uintptr_t retaddr =3D GETPC(); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UQ | MO_UNALN, + mmu_idx); =20 if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + for (unsigned i =3D 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] =3D cpu_ldq_mmu(env, addr, + oi, retaddr= ); addr +=3D 8; } } =20 if (do_r31) { - env->active_tc.gpr[31] =3D - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + env->active_tc.gpr[31] =3D cpu_ldq_mmu(env, addr, oi, retaddr); } } =20 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) + uint32_t mmu_idx) { target_ulong base_reglist =3D reglist & 0xf; target_ulong do_r31 =3D reglist & 0x10; + uintptr_t retaddr =3D GETPC(); + MemOpIdx oi =3D make_memop_idx(mo_endian_env(env) | MO_UQ | MO_UNALN, + mmu_idx); =20 if (base_reglist > 0 && base_reglist <=3D ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i =3D 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[= i]], - mem_idx, GETPC()); + for (unsigned i =3D 0; i < base_reglist; i++) { + cpu_stq_mmu(env, addr, env->active_tc.gpr[multiple_regs[i]], + oi, retaddr); addr +=3D 8; } } =20 if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETP= C()); + cpu_stq_mmu(env, addr, env->active_tc.gpr[31], oi, retaddr); } } =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/tcg-excp_helper.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/ppc/tcg-excp_helper.c b/target/ppc/tcg-excp_helper.c index edecfb85725..244aeb23c16 100644 --- a/target/ppc/tcg-excp_helper.c +++ b/target/ppc/tcg-excp_helper.c @@ -160,14 +160,17 @@ static void do_hash(CPUPPCState *env, target_ulong ea= , target_ulong ra, target_ulong rb, uint64_t key, bool store) { uint64_t calculated_hash =3D hash_digest(ra, rb, key), loaded_hash; + unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ | MO_UNALN, mmu_idx); + uintptr_t retaddr =3D GETPC(); =20 if (store) { - cpu_stq_data_ra(env, ea, calculated_hash, GETPC()); + cpu_stq_mmu(env, ea, calculated_hash, oi, retaddr); } else { - loaded_hash =3D cpu_ldq_data_ra(env, ea, GETPC()); + loaded_hash =3D cpu_ldq_mmu(env, ea, oi, retaddr); if (loaded_hash !=3D calculated_hash) { raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, - POWERPC_EXCP_TRAP, GETPC()); + POWERPC_EXCP_TRAP, retaddr); } } } --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764188826; cv=none; d=zohomail.com; s=zohoarc; b=H73U1Y3huCzN6lI+p90bVWrnum+ZSNdrZtxoJOEA6+iWotHWFeYcMiAKOvaQn7wF8idkM/1qG73nPPkV3mKdpeoOjeUSEgfgkglJpufz8ippnpyXESIi1JpHnR9mouVdpypsCZxVle2Lg7zhsdPVkUjVZ5cba8nqL9he7Bd4m10= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764188826; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=/DOfQD31qkMald+3OmhYsWbl0ISNPTLiwY4/obsMvFY=; b=g6PeE72i6Ny3jQGvxJxSs4J4YXJdGH/J3MDkBm7KClfCyPJetPYKC+48qmt+M9ntBDR50PNlhQqaFs29B83F0lNPU9OCOuG2ukaFLQ/6Rc8GruIx2MIWfYZg3T43eBoZx5YmRal8r6xb6qpYk+Z9+Vz4NSDRv68NMAYv3lHPbIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764188826590258.24924286126884; Wed, 26 Nov 2025 12:27:06 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM4G-0006ZF-HI; Wed, 26 Nov 2025 15:24:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM3w-00062H-El for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:33 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM3o-0002fz-U3 for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:27 -0500 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-47796a837c7so689085e9.0 for ; Wed, 26 Nov 2025 12:24:18 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/mem_helper.c | 36 ++++++++++++++++++++++++++---------- 1 file changed, 26 insertions(+), 10 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 6ab71a6fcb4..a43726d4223 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -97,8 +97,10 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uin= t32_t reg) } } else { /* Slow path -- at least some of the operation requires i/o. */ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx); + for (; reg < 32; reg++) { - env->gpr[reg] =3D cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr); + env->gpr[reg] =3D cpu_ldl_mmu(env, addr, oi, raddr); addr =3D addr_add(env, addr, 4); } } @@ -120,7 +122,9 @@ void helper_stmw(CPUPPCState *env, target_ulong addr, u= int32_t reg) } else { /* Slow path -- at least some of the operation requires i/o. */ for (; reg < 32; reg++) { - cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr); + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_i= dx); + + cpu_stl_mmu(env, addr, env->gpr[reg], oi, raddr); addr =3D addr_add(env, addr, 4); } } @@ -161,9 +165,11 @@ static void do_lsw(CPUPPCState *env, target_ulong addr= , uint32_t nb, break; } } else { + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx); + /* Slow path -- at least some of the operation requires i/o. */ for (; nb > 3; nb -=3D 4) { - env->gpr[reg] =3D cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr); + env->gpr[reg] =3D cpu_ldl_mmu(env, addr, oi, raddr); reg =3D (reg + 1) % 32; addr =3D addr_add(env, addr, 4); } @@ -174,10 +180,12 @@ static void do_lsw(CPUPPCState *env, target_ulong add= r, uint32_t nb, val =3D cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24; break; case 2: - val =3D cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16; + oi =3D make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx); + val =3D cpu_ldw_mmu(env, addr, oi, raddr) << 16; break; case 3: - val =3D cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16; + oi =3D make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx); + val =3D cpu_ldw_mmu(env, addr, oi, raddr) << 16; addr =3D addr_add(env, addr, 2); val |=3D cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8; break; @@ -250,8 +258,11 @@ void helper_stsw(CPUPPCState *env, target_ulong addr, = uint32_t nb, break; } } else { + MemOpIdx oi; + + oi =3D make_memop_idx(MO_TE | MO_UL | MO_UNALN, mmu_idx); for (; nb > 3; nb -=3D 4) { - cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr); + cpu_stl_mmu(env, addr, env->gpr[reg], oi, raddr); reg =3D (reg + 1) % 32; addr =3D addr_add(env, addr, 4); } @@ -261,10 +272,12 @@ void helper_stsw(CPUPPCState *env, target_ulong addr,= uint32_t nb, cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr); break; case 2: - cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr); + oi =3D make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx); + cpu_stw_mmu(env, addr, val >> 16, oi, raddr); break; case 3: - cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr); + oi =3D make_memop_idx(MO_TE | MO_UW | MO_UNALN, mmu_idx); + cpu_stw_mmu(env, addr, val >> 16, oi, raddr); addr =3D addr_add(env, addr, 2); cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr); break; @@ -293,8 +306,10 @@ static void dcbz_common(CPUPPCState *env, target_ulong= addr, haddr =3D probe_write(env, addr, dcbz_size, mmu_idx, retaddr); if (unlikely(!haddr)) { /* Slow path */ + MemOpIdx oi =3D make_memop_idx(MO_TE | MO_UQ | MO_UNALN, mmu_idx); + for (int i =3D 0; i < dcbz_size; i +=3D 8) { - cpu_stq_mmuidx_ra(env, addr + i, 0, mmu_idx, retaddr); + cpu_stq_mmu(env, addr + i, 0, oi, retaddr); } return; } @@ -342,9 +357,10 @@ void helper_icbi(CPUPPCState *env, target_ulong addr) void helper_icbiep(CPUPPCState *env, target_ulong addr) { #if !defined(CONFIG_USER_ONLY) + MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, PPC_TLB_EPID_LOAD); /* See comments above */ addr &=3D ~(env->dcache_line_size - 1); - cpu_ldl_mmuidx_ra(env, addr, PPC_TLB_EPID_LOAD, GETPC()); + cpu_ldl_mmu(env, addr, oi, GETPC()); #endif } =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Since the returned value is discarded, don't bother to set the access endianness. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/mem_helper.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index a43726d4223..cff385b6020 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -344,14 +344,18 @@ void helper_dcbzl(CPUPPCState *env, target_ulong addr) =20 void helper_icbi(CPUPPCState *env, target_ulong addr) { + unsigned mmu_idx =3D cpu_mmu_index(env_cpu(env), false); + MemOpIdx oi =3D make_memop_idx(MO_UL | MO_UNALN, mmu_idx); + addr &=3D ~(env->dcache_line_size - 1); /* * Invalidate one cache line : * PowerPC specification says this is to be treated like a load * (not a fetch) by the MMU. To be sure it will be so, - * do the load "by hand". + * do the load "by hand". As the returned data is not consumed, + * endianness is irrelevant. */ - cpu_ldl_data_ra(env, addr, GETPC()); + cpu_ldl_mmu(env, addr, oi, GETPC()); } =20 void helper_icbiep(CPUPPCState *env, target_ulong addr) --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764188821; cv=none; d=zohomail.com; s=zohoarc; b=JpD0coRI2PGyle03iWQvpPcNEHeTa5yYkMbsGHJiltDPBfKTh435YFhx2coE+uh00NP4ccq/bus6w+KOBtb9ZKbe1/PEzC8/GGxJxVrik28Hksw3AqnyIdbvjK9NCBlWBY2UsZZVEJhaPRwS4ObDJPXx5fXPTAgmpVXwmAIRcSQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764188821; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=VnIOi7CrJFSwpeAe7LUTjMPzfQSZarulbCgikZO0egs=; b=iao7ZDObe357z0SP9m5lj/n5k7UC2vMNlgNuJdqlfb34w+xudXlLeCWeM0EqgE5UULRuiVACB+DI+IKFIiDfcGc0ALOvRVdtAyYpHBbmkGvmA/sdC7ldT4axWSn4gXAOTd5cqoPiKiGC9LCfV0ic3OE9a1q54nPdcgg1kIuZxjo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764188821941706.3128785597019; Wed, 26 Nov 2025 12:27:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM4J-00074l-P7; Wed, 26 Nov 2025 15:24:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM4D-0006L3-Js for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:47 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM45-0002hd-HR for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:42 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-47790b080e4so377765e9.3 for ; Wed, 26 Nov 2025 12:24:32 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/mem_helper.c | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index cff385b6020..cfc67a527c1 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -31,15 +31,6 @@ =20 /* #define DEBUG_OP */ =20 -static inline bool needs_byteswap(const CPUPPCState *env) -{ -#if TARGET_BIG_ENDIAN - return FIELD_EX64(env->msr, MSR, LE); -#else - return !FIELD_EX64(env->msr, MSR, LE); -#endif -} - /*************************************************************************= ****/ /* Memory load and stores */ =20 @@ -421,11 +412,10 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ul= ong addr, uint32_t reg, int adjust =3D HI_IDX * (n_elems - 1); \ int sh =3D sizeof(r->element[0]) >> 1; \ int index =3D (addr & 0xf) >> sh; \ - if (FIELD_EX64(env->msr, MSR, LE)) { \ - index =3D n_elems - index - 1; \ - } \ + bool byteswap =3D FIELD_EX64(env->msr, MSR, LE); \ \ - if (needs_byteswap(env)) { \ + if (byteswap) { \ + index =3D n_elems - index - 1; \ r->element[LO_IDX ? index : (adjust - index)] =3D \ swap(access(env, addr, GETPC())); \ } else { \ @@ -435,8 +425,8 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulon= g addr, uint32_t reg, } #define I(x) (x) LVE(LVEBX, cpu_ldub_data_ra, I, u8) -LVE(LVEHX, cpu_lduw_data_ra, bswap16, u16) -LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) +LVE(LVEHX, cpu_lduw_be_data_ra, bswap16, u16) +LVE(LVEWX, cpu_ldl_be_data_ra, bswap32, u32) #undef I #undef LVE =20 @@ -448,11 +438,10 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) int adjust =3D HI_IDX * (n_elems - 1); \ int sh =3D sizeof(r->element[0]) >> 1; \ int index =3D (addr & 0xf) >> sh; \ - if (FIELD_EX64(env->msr, MSR, LE)) { \ - index =3D n_elems - index - 1; \ - } \ + bool byteswap =3D FIELD_EX64(env->msr, MSR, LE); \ \ - if (needs_byteswap(env)) { \ + if (byteswap) { \ + index =3D n_elems - index - 1; \ access(env, addr, swap(r->element[LO_IDX ? index : \ (adjust - index)]), \ GETPC()); \ @@ -463,8 +452,8 @@ LVE(LVEWX, cpu_ldl_data_ra, bswap32, u32) } #define I(x) (x) STVE(STVEBX, cpu_stb_data_ra, I, u8) -STVE(STVEHX, cpu_stw_data_ra, bswap16, u16) -STVE(STVEWX, cpu_stl_data_ra, bswap32, u32) +STVE(STVEHX, cpu_stw_be_data_ra, bswap16, u16) +STVE(STVEWX, cpu_stl_be_data_ra, bswap32, u32) #undef I #undef LVE =20 --=20 2.51.0 From nobody Sat Nov 29 10:15:17 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764193663; cv=none; d=zohomail.com; s=zohoarc; b=ai2TPZuqVLT/EkTsJIPTkJ0Ey2++K2CFkmRh3eTL/Xd0XIBXSat1umEZYG+PFadJVvcYGa5MaLa6RAA7ZBMLrTSb3tPe4WygsZPsOdfUAr0/s3s6wcF96ly5DOQ8KDrIA0NAw3wtMCPewJ6xcnCqOiQWYdL3dmtm7QJWpNMdwmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764193663; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=6yJMqELVhfkz7BjcKLlw9hrXWFRteZQ0RZVkFPdtBPU=; b=V4Eo5cCD/z/8YPx+o3kQlkzkHjJz2KaeajMCCnjGt6D8pLIm8uR1y9Ug+kzGh7/LZ3vK7+LXA4ej3hwRFg1kkKsuLoQwpBNL/KAlGWGeCa/zLnCFoAwfCbB4uPQOSHfgmmimhnZ90sWlCgzc9kbEi8ikrjpCPheZwb0wFcNV0/o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176419366370210.397459827796752; Wed, 26 Nov 2025 13:47:43 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOM4I-0006vu-JD; Wed, 26 Nov 2025 15:24:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOM4D-0006L6-KF for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:47 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOM49-0002ia-BO for qemu-devel@nongnu.org; Wed, 26 Nov 2025 15:24:43 -0500 Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-477619f8ae5so502025e9.3 for ; Wed, 26 Nov 2025 12:24:39 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/accel/tcg/cpu-ldst.h | 46 ------------------------------------ 1 file changed, 46 deletions(-) diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index 0de7f5eaa6b..12dd38599a6 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -428,52 +428,6 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint6= 4_t val) cpu_stq_le_data_ra(env, addr, val, 0); } =20 -#if TARGET_BIG_ENDIAN -# define cpu_lduw_data cpu_lduw_be_data -# define cpu_ldsw_data cpu_ldsw_be_data -# define cpu_ldl_data cpu_ldl_be_data -# define cpu_ldq_data cpu_ldq_be_data -# define cpu_lduw_data_ra cpu_lduw_be_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra -# define cpu_ldl_data_ra cpu_ldl_be_data_ra -# define cpu_ldq_data_ra cpu_ldq_be_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra -# define cpu_stw_data cpu_stw_be_data -# define cpu_stl_data cpu_stl_be_data -# define cpu_stq_data cpu_stq_be_data -# define cpu_stw_data_ra cpu_stw_be_data_ra -# define cpu_stl_data_ra cpu_stl_be_data_ra -# define cpu_stq_data_ra cpu_stq_be_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra -#else -# define cpu_lduw_data cpu_lduw_le_data -# define cpu_ldsw_data cpu_ldsw_le_data -# define cpu_ldl_data cpu_ldl_le_data -# define cpu_ldq_data cpu_ldq_le_data -# define cpu_lduw_data_ra cpu_lduw_le_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra -# define cpu_ldl_data_ra cpu_ldl_le_data_ra -# define cpu_ldq_data_ra cpu_ldq_le_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra -# define cpu_stw_data cpu_stw_le_data -# define cpu_stl_data cpu_stl_le_data -# define cpu_stq_data cpu_stq_le_data -# define cpu_stw_data_ra cpu_stw_le_data_ra -# define cpu_stl_data_ra cpu_stl_le_data_ra -# define cpu_stq_data_ra cpu_stq_le_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra -#endif - static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { CPUState *cs =3D env_cpu(env); --=20 2.51.0