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Date: Wed, 26 Nov 2025 12:36:47 +0000 Message-ID: <20251126124116.351685-2-jim.macarthur@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251126124116.351685-1-jim.macarthur@linaro.org> References: <20251126124116.351685-1-jim.macarthur@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=jim.macarthur@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764160946101019200 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jim MacArthur --- target/arm/cpu-sysregs.h.inc | 1 + target/arm/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu-sysregs.h.inc b/target/arm/cpu-sysregs.h.inc index 2bb2861c62..2ba49d8478 100644 --- a/target/arm/cpu-sysregs.h.inc +++ b/target/arm/cpu-sysregs.h.inc @@ -14,6 +14,7 @@ DEF(ID_AA64MMFR0_EL1, 3, 0, 0, 7, 0) DEF(ID_AA64MMFR1_EL1, 3, 0, 0, 7, 1) DEF(ID_AA64MMFR2_EL1, 3, 0, 0, 7, 2) DEF(ID_AA64MMFR3_EL1, 3, 0, 0, 7, 3) +DEF(ID_AA64MMFR4_EL1, 3, 0, 0, 7, 4) DEF(ID_PFR0_EL1, 3, 0, 0, 1, 0) DEF(ID_PFR1_EL1, 3, 0, 0, 1, 1) DEF(ID_DFR0_EL1, 3, 0, 0, 1, 2) diff --git a/target/arm/helper.c b/target/arm/helper.c index 27ebc6f29b..c20334fa65 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6566,11 +6566,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR3) }, - { .name =3D "ID_AA64MMFR4_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, + { .name =3D "ID_AA64MMFR4_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D 0 }, + .resetvalue =3D GET_IDREG(isar, ID_AA64MMFR4) }, { .name =3D "ID_AA64MMFR5_EL1_RESERVED", .state =3D ARM_CP_STA= TE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 7, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.43.0 From nobody Sat Nov 29 10:15:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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ASID is still ignored. Any writes to TTBR0_EL0 and TTBR1_EL0, including changing the ASID, will still cause a complete flush of the TLB. Signed-off-by: Jim MacArthur --- target/arm/cpu-features.h | 7 +++++++ target/arm/helper.c | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 579fa8f8f4..d56bda9ce0 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -346,6 +346,8 @@ FIELD(ID_AA64MMFR3, SDERR, 52, 4) FIELD(ID_AA64MMFR3, ADERR, 56, 4) FIELD(ID_AA64MMFR3, SPEC_FPACC, 60, 4) =20 +FIELD(ID_AA64MMFR4, ASID2, 8, 4) + FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) FIELD(ID_AA64DFR0, TRACEVER, 4, 4) FIELD(ID_AA64DFR0, PMUVER, 8, 4) @@ -1369,6 +1371,11 @@ static inline bool isar_feature_aa64_aie(const ARMIS= ARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, AIE) !=3D 0; } =20 +static inline bool isar_feature_aa64_asid2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR4, ASID2) !=3D 0; +} + static inline bool isar_feature_aa64_mec(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, MEC) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c20334fa65..7812a82bab 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6102,6 +6102,9 @@ static void tcr2_el1_write(CPUARMState *env, const AR= MCPRegInfo *ri, if (cpu_isar_feature(aa64_aie, cpu)) { valid_mask |=3D TCR2_AIE; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6121,6 +6124,9 @@ static void tcr2_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, if (cpu_isar_feature(aa64_mec, cpu)) { valid_mask |=3D TCR2_AMEC0 | TCR2_AMEC1; } + if (cpu_isar_feature(aa64_asid2, cpu)) { + valid_mask |=3D TCR2_FNG1 | TCR2_FNG0 | TCR2_A2; + } value &=3D valid_mask; raw_write(env, ri, value); } --=20 2.43.0 From nobody Sat Nov 29 10:15:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764160957; cv=none; d=zohomail.com; s=zohoarc; b=Jo0IxPk34xkxMoqVH75feYXrmKirlibLQyTwsyPPR8IlCZJ3IKL6Mtmz84OylxuqKWR7SP2Cz8IbyYUmQWjMjZMILSAB1QCr3cV3px258dS7k9XLnygrOv5pAa1wkabS3LJqeFY2U8JnpMQwWUeaLAs5UYh213jtPMkoeGqEun0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764160957; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Mn1h9ya9N+o+rWO96EM7+0sskwR9RqKMkNCUOJ59t/M=; b=SdYmPiaRLK8evMpocjZmHVOdL5j5v3mhNj0e+yQNw4CsRybs87ArWBBJPcXWISM+4X88fQw92cOELr1CW4czJPVtq+hIRBvUq4hCGAkfld8YiBLOrqsq3+jl+r4jMQiqA4w5DitFFrQtoUJMMyGeX/i/4KSf6U+5XWtntNAGqXw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764160957415169.93337199426435; Wed, 26 Nov 2025 04:42:37 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOEqJ-0002kF-UW; Wed, 26 Nov 2025 07:41:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOEpq-0001q0-3u for qemu-devel@nongnu.org; Wed, 26 Nov 2025 07:41:29 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOEpo-0003OA-3y for qemu-devel@nongnu.org; Wed, 26 Nov 2025 07:41:25 -0500 Received: by mail-wr1-x42d.google.com with SMTP id ffacd0b85a97d-42b3108f41fso4051623f8f.3 for ; Wed, 26 Nov 2025 04:41:22 -0800 (PST) Received: from jimm-x1.. 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Wed, 26 Nov 2025 04:41:21 -0800 (PST) From: Jim MacArthur To: qemu-devel@nongnu.org Cc: Jim MacArthur Subject: [PATCH V3 3/4] target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max Date: Wed, 26 Nov 2025 12:36:49 +0000 Message-ID: <20251126124116.351685-4-jim.macarthur@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251126124116.351685-1-jim.macarthur@linaro.org> References: <20251126124116.351685-1-jim.macarthur@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=jim.macarthur@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764160958145019200 Content-Type: text/plain; charset="utf-8" Signed-off-by: Jim MacArthur --- target/arm/tcg/cpu64.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 6871956382..ef4c0c8d73 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1334,6 +1334,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, AIE, 1); /* FEAT_AIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 + t =3D GET_IDREG(isar, ID_AA64MMFR4); + t =3D FIELD_DP64(t, ID_AA64MMFR4, ASID2, 1); /* FEAT_ASID2 */ + SET_IDREG(isar, ID_AA64MMFR4, t); + t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ --=20 2.43.0 From nobody Sat Nov 29 10:15:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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If not present, check these read as RES0. Signed-off-by: Jim MacArthur --- tests/tcg/aarch64/system/asid2.c | 75 ++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 tests/tcg/aarch64/system/asid2.c diff --git a/tests/tcg/aarch64/system/asid2.c b/tests/tcg/aarch64/system/as= id2.c new file mode 100644 index 0000000000..a4887e4ce2 --- /dev/null +++ b/tests/tcg/aarch64/system/asid2.c @@ -0,0 +1,75 @@ +/* + * ASID2 Feature presence and enabled TCR2_EL1 bits test + * + * Copyright (c) 2025 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include + +#define ID_AA64MMFR3_EL1 "S3_0_C0_C7_3" +#define ID_AA64MMFR4_EL1 "S3_0_C0_C7_4" +#define TCR2_EL1 "S3_0_C2_C0_3" + +int main() +{ + /* + * Test for presence of ASID2 and three feature bits enabled by it: + * https://developer.arm.com/documentation/109697/2025_09/Feature-desc= riptions/The-Armv9-5-architecture-extension + * Bits added are FNG1, FNG0, and A2. These should be RES0 if A2 is + * not enabled and read as the written value if A2 is enabled. + */ + + uint64_t out; + uint64_t idreg3; + uint64_t idreg4; + int tcr2_present; + int asid2_present; + + /* Mask is FNG1, FNG0, and A2 */ + const uint64_t feature_mask =3D (1ULL << 18 | 1ULL << 17 | 1ULL << 16); + const uint64_t in =3D feature_mask; + + asm("mrs %[x1], " ID_AA64MMFR3_EL1 "\n\t" + : [x1] "=3Dr" (idreg3)); + + tcr2_present =3D ((idreg3 & 0xF) !=3D 0); + + if (!tcr2_present) { + ml_printf("TCR2 is not present, cannot perform test"); + return 0; + } + + asm("mrs %[x1], " ID_AA64MMFR4_EL1 "\n\t" + : [x1] "=3Dr" (idreg4)); + + asid2_present =3D ((idreg4 & 0xF00) !=3D 0); + + asm("msr " TCR2_EL1 ", %[x0]\n\t" + "mrs %[x1], " TCR2_EL1 "\n\t" + : [x1] "=3Dr" (out) + : [x0] "r" (in)); + + if (asid2_present) { + if ((out & feature_mask) =3D=3D in) { + ml_printf("OK\n"); + return 0; + } else { + ml_printf("FAIL: ASID2 present, but read value %lx !=3D " + "written value %lx\n", + out & feature_mask, in); + return 1; + } + } else { + if (out =3D=3D 0) { + ml_printf("TCR2_EL1 reads as RES0 as expected\n"); + return 0; + } else { + ml_printf("FAIL: ASID2, missing but read value %lx !=3D 0\n", + out & feature_mask, in); + return 1; + } + } +} --=20 2.43.0