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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479052def4bsm34010905e9.13.2025.11.25.23.50.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Nov 2025 23:50:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764143412; x=1764748212; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FtKth+b9TdPq30wZ/hp2A5R8f47SbZbi440xtKAdXk8=; b=qYVlRNYGYA5cNJqhkN+2bLxqpeXfz1XmZijuqPswk5ntnnmCgI848pUGHVJJUDIdTb glKzOkckztnN5YUSQSWf+b71D6RNPSZ5PdqCi0ArMBwtc2SmBPbPVQAgYfuVOolLTziC nVbA1rO6P0I+nzJmZYCBhlLWR9hdQ36ymgUsG/tiOepoCyhYLsBdLmbR4enzgz7hqtMp rvcIKimA2paQeaZMa8VdlfN6zsrkZ7M6/3DzdPWy9blxq7y2W+eQRP2SlxuTnc6Txjol 9hQdR6kC/tDEoTQGECncvZXtGf7DIpWs/0qjPjiTtxapF6dgobd3PcrWQV2F1PF58WV1 bThQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764143412; x=1764748212; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=FtKth+b9TdPq30wZ/hp2A5R8f47SbZbi440xtKAdXk8=; b=W8qOWXPfesDKYc2Ed9iNVkoU3YuIPSpuadtaD46xlM8PkYIXugsTHoLpvOjgZLae62 GZNL+A+neYzWyzwz4MKY/saAz3CZSU6V6yp3IRD/wT1n8SKnk8vj4LWimXNiYY7Iak8d UWZxJOckavsaWKnm9lyekqbR+Lf0vvLHBT0H7hIQR6Cm+Zq5tRAahlV5DHRH0qOdZ6Pg e/RIvstC3DypWCSlkDVQmUpu75zOg4ZPJDJLEvAVXoiW7UwpKBI/gSpB8qk7rVMNsjP2 ycCExfJslRSJga04kcznwDH0XPLZmm/Ot4fn01fc+4o/RKZVtUPT1L8Y1pDgBqo/8UDW ylRQ== X-Gm-Message-State: AOJu0YyiXJOr4PQZt/b3ju5JC58B2lyaYaxB0N72u8jqBWfHPW1Z/HPP p/wKXKxP80UL/yzoLb4YouKHysQxRfySjwoqd4i3cXsO7xBRfmp5+fwAJsdJXfBi35zwzAFKSQQ S9zMoSo5/QQ== X-Gm-Gg: ASbGncvtzMpTlgEyvmf48pCd6WoRk9fHt+0DvboHuSBoDfS9yiG4HqrSKptayOAOaFe HgrqIHf5LYqc4tGekmOj/lZJkuBAL2b0Yjc2brDnsXfPOlNgG6U6SfkgrouInhPhsc/TxrrNaEf 3sMhbFlYr9KBIhsRfgGRN4NoGH7+tqBOIVgiNDr6lKa4gLyVISQYbXsFH+k/TVZkXgF1yghIQLr Rt7jwQZBxhLY1c2Hcw6Gc/Bevrk8ogqa/Idrfz9jS14/nrBdi8RQc5KLMRS3/Ruaq4zlkO+oyAU 4OPH6geaV28MGobZmXa2RE2FrFim7jYzNPxjiPved151x368ujUVJ+/iSADYYnKwNiMllMWX/Vc XIWs1TyioN2KH3xeUQ5m8VTyEbiM8/HHlAkoFNbCpNwzGlTL0QrC2tZNMoIC4TXZDjlybxdGgJB ezvcNgxSxNcl5WYoZmtFIw3VTHfbRA+Fyh/2M+egCo1Fpr7b6utgpKIr232p3V X-Google-Smtp-Source: AGHT+IE39MONzmqfOsccrgSI1GSL9Vf9zFIhUSES1/kq2pkLjgVmAkmngwovYocZuZ44faHQKiAklw== X-Received: by 2002:a05:600c:1554:b0:46e:7e22:ff6a with SMTP id 5b1f17b1804b1-47904aebeb2mr62332085e9.15.1764143412544; Tue, 25 Nov 2025 23:50:12 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Brian Cain Subject: [PATCH-for-11.0 v2 01/12] target/hexagon: Use little-endian variant of cpu_ld/st_data*() Date: Wed, 26 Nov 2025 08:49:52 +0100 Message-ID: <20251126075003.4826-2-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126075003.4826-1-philmd@linaro.org> References: <20251126075003.4826-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764143485963019200 We only build the Hexagon target using little endianness order, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. Mechanical change running: $ tgt=3Dhexagon; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Brian Cain Reviewed-by: Richard Henderson --- target/hexagon/macros.h | 6 +++--- target/hexagon/op_helper.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 088e5961ab7..6c2862a2320 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -519,9 +519,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA) #else #define MEM_LOAD1 cpu_ldub_data_ra -#define MEM_LOAD2 cpu_lduw_data_ra -#define MEM_LOAD4 cpu_ldl_data_ra -#define MEM_LOAD8 cpu_ldq_data_ra +#define MEM_LOAD2 cpu_lduw_le_data_ra +#define MEM_LOAD4 cpu_ldl_le_data_ra +#define MEM_LOAD8 cpu_ldq_le_data_ra =20 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \ do { \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index e2e80ca7efa..08db1e9c56b 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -77,13 +77,13 @@ static void commit_store(CPUHexagonState *env, int slot= _num, uintptr_t ra) cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); break; case 2: - cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); + cpu_stw_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, = ra); break; case 4: - cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra); + cpu_stl_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, = ra); break; case 8: - cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra); + cpu_stq_le_data_ra(env, va, env->mem_log_stores[slot_num].data64, = ra); break; default: g_assert_not_reached(); --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143503; cv=none; d=zohomail.com; s=zohoarc; b=MMkyBridBQKHPplyvvMhUygSSoG814T1RGd+GvD1rPP/qyMA5A32dSPqFnqLVrYn5qm05PPDHU9XZfZ5dPUPhuS33fa2l4uSmbx6ztaKsqhKypiq3euJB5j4vIGXFc+Tg7WRk4gLEbAJ6jtUTPG74jTZHjKcVgYTgRiSR/J+npM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143503; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=idPfVbwdmuwP3E4rOS4isKmneb6eqTi31QSmeF+nOd0=; b=ZGQcroIlnAAKcWf1KOkbn54vn658NxQSwJmpgn1haReBNL4/3rXIdSo9C8x3r4PTlYrpvjGdHI+0vaFTqBQkgI6SvmIrWxkYUduoVphWb1Y5IpRQzovl9UFWwm8LkO6vkdqoYwPtFSqAf90B58uEXnW20cjy3KLX062MVzWQ0n0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176414350051890.17309113039119; Tue, 25 Nov 2025 23:51:40 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOAJ2-00015f-EF; Wed, 26 Nov 2025 02:51:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOAIC-0000W4-Uw for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:50:26 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOAI9-0003PA-QE for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:50:24 -0500 Received: by mail-wr1-x436.google.com with SMTP id ffacd0b85a97d-42b427cda88so4299343f8f.0 for ; Tue, 25 Nov 2025 23:50:21 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42cb7f3635bsm39401408f8f.17.2025.11.25.23.50.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Nov 2025 23:50:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764143420; x=1764748220; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=idPfVbwdmuwP3E4rOS4isKmneb6eqTi31QSmeF+nOd0=; b=VUVx0g9JkPS6h+kxN+ZJYns9cQ4r4S/3q0HFTaGjwZzJSNsz/HyHKY21JSv1yT9Cp9 FfF9vuoZRPmXK2nAcI5e4mnHoI43wuG46zYxvHnfXmoC92wz21+jrilfqfStuLici6uC 9RI7bBaCFgEOFhQzzKWYtd+jFgUSNMHoV0rieWf0qqafid302BwC2LYQnHV1WIJFt7Mz 2zsjMiFYMSHF7qqT1lgVH5tZzY0RhrAMXFgb7JxLNQAXaWSOfn6v3zMdKO5v0Ug7/hYX U/KrnU8Y8unbWQ+D19qYLLat6BNKimYR3I1neTqs8Mg2T0bgNLK8ckGOpMF6Kp+RKmor YwLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764143420; x=1764748220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=idPfVbwdmuwP3E4rOS4isKmneb6eqTi31QSmeF+nOd0=; b=kIjGVIYH4SMbRzCjPkc9w+ZR3PkB5ABUIQqHF6223FtW+wgSO6OL4kSHh0M4sSVfwc gbYmAYvAZG1gH6Vcv4SjLl/OKKrbsTAOL0B9UYdF2zc3ZIemFQBMcSnwVU6Q77gybtpe zANGUYpF63cZXIYjl97Bk6qbA6vykGLKORlr3EQm0oCyZ2mnUZSfcpCTks1LKfkWv3Ch +f7R+luQkS/NZW2ULCUROX7BK34PYCPEbrSQfJS2j95KEq6mqTt9OSvV+fLSsv5KeHus sz7CJ/0ij54p0CwDwOyGwmF3CGUNlZu3ozV/FFVxW0m/XKBxyGphUQOiKKJ8Y4PHasq8 HxFQ== X-Gm-Message-State: AOJu0YwnUUAEfUFZ2bv6c95OheplMQ8yWNWdWcL091PvAZ2gCZghIjtx 1eL/YYLEQkVJs1p998Slb2NyKhKZ/VutCHAsZBu1s70E7IYoaAUz8/nSzXNYYWE+LzxAoUio2jH F+EfxLfSfkQ== X-Gm-Gg: ASbGncsRsF9b09B2+dsYYvjDx9SpYMFqSEhmwJLCG4hPK0BFxKrIh3vMYIE5jUCiNxD VoMyNl3pXMm/tfMSNipM2aI9qf03RFJYXxQze+YQASZu8AfQBmVLlQ4dFCer3TwYLz07NDz9+Xb 4KqYnbWenBkG9kEranZlAcj3UucSWWQvn3x8gfH5kAYdXx81Ykcua4tDCcJcScLPYig20zAngZR iNzGDXvU6DyRuz1PDex+aKQYfze0069jJycsoOMFBkyUku4tyrMDlgz/o2hbE4EUdu5e4aE86Wt eGW3gqjQV4WNiHGnF6QG9+eGTvs3FxdqFLW8wJ6ZyDCEyRrIC9xGItZaW+cFbL+jWUmesgG/Qdb 3xCSJUEXomNnoLNnbB0CgsdNQh2kc4VbhQNfAj6/iqPjcJqfi1srDwU4ECg4BO8f8T+2ZZMksES lDKbvK6embhiALPt8tuI00mV1WuMYMPahZ1XFq1FwHmtX2V0QaXbpalywJtUX7 X-Google-Smtp-Source: AGHT+IFqpM8TIbsX9+OktdGWynr78Kv86N6nuOEDGHi9XeiZ/g0BxOANv1L9qpRHDbEceeh2G1vVRA== X-Received: by 2002:a05:6000:2883:b0:42b:3806:2ba6 with SMTP id ffacd0b85a97d-42cc1cbce07mr19755082f8f.25.1764143419945; Tue, 25 Nov 2025 23:50:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Helge Deller Subject: [PATCH-for-11.0 v2 02/12] target/hppa: Use little-endian variant of cpu_ld/st_data*() Date: Wed, 26 Nov 2025 08:49:53 +0100 Message-ID: <20251126075003.4826-3-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126075003.4826-1-philmd@linaro.org> References: <20251126075003.4826-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764143507769019200 We only build the HPPA target using little endianness order, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. Mechanical change running: $ tgt=3Dhppa; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/hppa/op_helper.c | 44 ++++++++++++++++++++--------------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 0458378abb2..65faf03cd0a 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -107,7 +107,7 @@ static void do_stby_b(CPUHPPAState *env, target_ulong a= ddr, target_ulong val, cpu_stb_data_ra(env, addr, val, ra); break; case 2: - cpu_stw_data_ra(env, addr, val, ra); + cpu_stw_be_data_ra(env, addr, val, ra); break; case 1: /* The 3 byte store must appear atomic. */ @@ -115,11 +115,11 @@ static void do_stby_b(CPUHPPAState *env, target_ulong= addr, target_ulong val, atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); - cpu_stw_data_ra(env, addr + 1, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val, ra); } break; default: - cpu_stl_data_ra(env, addr, val, ra); + cpu_stl_be_data_ra(env, addr, val, ra); break; } } @@ -132,7 +132,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, cpu_stb_data_ra(env, addr, val, ra); break; case 6: - cpu_stw_data_ra(env, addr, val, ra); + cpu_stw_be_data_ra(env, addr, val, ra); break; case 5: /* The 3 byte store must appear atomic. */ @@ -140,11 +140,11 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask32(env, addr, val, 0x00ffffffu, ra); } else { cpu_stb_data_ra(env, addr, val >> 16, ra); - cpu_stw_data_ra(env, addr + 1, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val, ra); } break; case 4: - cpu_stl_data_ra(env, addr, val, ra); + cpu_stl_be_data_ra(env, addr, val, ra); break; case 3: /* The 5 byte store must appear atomic. */ @@ -152,7 +152,7 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr, val, 0x000000ffffffffffull, 5, = ra); } else { cpu_stb_data_ra(env, addr, val >> 32, ra); - cpu_stl_data_ra(env, addr + 1, val, ra); + cpu_stl_be_data_ra(env, addr + 1, val, ra); } break; case 2: @@ -160,8 +160,8 @@ static void do_stdby_b(CPUHPPAState *env, target_ulong = addr, uint64_t val, if (parallel) { atomic_store_mask64(env, addr, val, 0x0000ffffffffffffull, 6, = ra); } else { - cpu_stw_data_ra(env, addr, val >> 32, ra); - cpu_stl_data_ra(env, addr + 2, val, ra); + cpu_stw_be_data_ra(env, addr, val >> 32, ra); + cpu_stl_be_data_ra(env, addr + 2, val, ra); } break; case 1: @@ -170,12 +170,12 @@ static void do_stdby_b(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask64(env, addr, val, 0x00ffffffffffffffull, 7, = ra); } else { cpu_stb_data_ra(env, addr, val >> 48, ra); - cpu_stw_data_ra(env, addr + 1, val >> 32, ra); - cpu_stl_data_ra(env, addr + 3, val, ra); + cpu_stw_be_data_ra(env, addr + 1, val >> 32, ra); + cpu_stl_be_data_ra(env, addr + 3, val, ra); } break; default: - cpu_stq_data_ra(env, addr, val, ra); + cpu_stq_be_data_ra(env, addr, val, ra); break; } } @@ -211,12 +211,12 @@ static void do_stby_e(CPUHPPAState *env, target_ulong= addr, target_ulong val, if (parallel) { atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); } else { - cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); } break; case 2: - cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra); break; case 1: cpu_stb_data_ra(env, addr - 1, val >> 24, ra); @@ -239,8 +239,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr - 7, val, 0xffffffffffffff00ull, 7, ra); } else { - cpu_stl_data_ra(env, addr - 7, val >> 32, ra); - cpu_stw_data_ra(env, addr - 3, val >> 16, ra); + cpu_stl_be_data_ra(env, addr - 7, val >> 32, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 16, ra); cpu_stb_data_ra(env, addr - 1, val >> 8, ra); } break; @@ -250,8 +250,8 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong = addr, uint64_t val, atomic_store_mask64(env, addr - 6, val, 0xffffffffffff0000ull, 6, ra); } else { - cpu_stl_data_ra(env, addr - 6, val >> 32, ra); - cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + cpu_stl_be_data_ra(env, addr - 6, val >> 32, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 16, ra); } break; case 5: @@ -260,24 +260,24 @@ static void do_stdby_e(CPUHPPAState *env, target_ulon= g addr, uint64_t val, atomic_store_mask64(env, addr - 5, val, 0xffffffffff000000ull, 5, ra); } else { - cpu_stl_data_ra(env, addr - 5, val >> 32, ra); + cpu_stl_be_data_ra(env, addr - 5, val >> 32, ra); cpu_stb_data_ra(env, addr - 1, val >> 24, ra); } break; case 4: - cpu_stl_data_ra(env, addr - 4, val >> 32, ra); + cpu_stl_be_data_ra(env, addr - 4, val >> 32, ra); break; case 3: /* The 3 byte store must appear atomic. */ if (parallel) { atomic_store_mask32(env, addr - 3, val >> 32, 0xffffff00u, ra); } else { - cpu_stw_data_ra(env, addr - 3, val >> 48, ra); + cpu_stw_be_data_ra(env, addr - 3, val >> 48, ra); cpu_stb_data_ra(env, addr - 1, val >> 40, ra); } break; case 2: - cpu_stw_data_ra(env, addr - 2, val >> 48, ra); + cpu_stw_be_data_ra(env, addr - 2, val >> 48, ra); break; case 1: cpu_stb_data_ra(env, addr - 1, val >> 56, ra); --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143486; cv=none; d=zohomail.com; s=zohoarc; b=QCMRHBRvBwH/1iQ6aJcHyE/GuoVADPAceRSzwzuiVYtrj57hhLBsxHNJ6i0I37BtEg5UYo8KYpCIQ0STPFI2mQBRyT/jGhNQFntklUwa82zstHh7UYA0MKGiGnpLKGMZ3/X4LbCqqdT78yc+ywqiSru8AwrDdDOLFrQcuT3/yms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143486; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Use the explicit little-endian variants. Mechanical change running: $ tgt=3Di386; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting indentation in helper_vmload() to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/i386/ops_sse.h | 12 ++--- target/i386/tcg/seg_helper.h | 12 ++--- linux-user/vm86.c | 4 +- target/i386/tcg/mem_helper.c | 8 ++-- target/i386/tcg/mpx_helper.c | 28 +++++------ target/i386/tcg/seg_helper.c | 16 +++---- target/i386/tcg/system/excp_helper.c | 8 ++-- target/i386/tcg/system/svm_helper.c | 69 +++++++++++++++------------- 8 files changed, 80 insertions(+), 77 deletions(-) diff --git a/target/i386/ops_sse.h b/target/i386/ops_sse.h index a2e4d480399..213db53382c 100644 --- a/target/i386/ops_sse.h +++ b/target/i386/ops_sse.h @@ -2326,7 +2326,7 @@ void glue(helper_vpmaskmovd_st, SUFFIX)(CPUX86State *= env, =20 for (i =3D 0; i < (2 << SHIFT); i++) { if (v->L(i) >> 31) { - cpu_stl_data_ra(env, a0 + i * 4, s->L(i), GETPC()); + cpu_stl_le_data_ra(env, a0 + i * 4, s->L(i), GETPC()); } } } @@ -2338,7 +2338,7 @@ void glue(helper_vpmaskmovq_st, SUFFIX)(CPUX86State *= env, =20 for (i =3D 0; i < (1 << SHIFT); i++) { if (v->Q(i) >> 63) { - cpu_stq_data_ra(env, a0 + i * 8, s->Q(i), GETPC()); + cpu_stq_le_data_ra(env, a0 + i * 8, s->Q(i), GETPC()); } } } @@ -2369,7 +2369,7 @@ void glue(helper_vpgatherdd, SUFFIX)(CPUX86State *env, if (v->L(i) >> 31) { target_ulong addr =3D a0 + ((target_ulong)(int32_t)s->L(i) << scale); - d->L(i) =3D cpu_ldl_data_ra(env, addr, GETPC()); + d->L(i) =3D cpu_ldl_le_data_ra(env, addr, GETPC()); } v->L(i) =3D 0; } @@ -2383,7 +2383,7 @@ void glue(helper_vpgatherdq, SUFFIX)(CPUX86State *env, if (v->Q(i) >> 63) { target_ulong addr =3D a0 + ((target_ulong)(int32_t)s->L(i) << scale); - d->Q(i) =3D cpu_ldq_data_ra(env, addr, GETPC()); + d->Q(i) =3D cpu_ldq_le_data_ra(env, addr, GETPC()); } v->Q(i) =3D 0; } @@ -2397,7 +2397,7 @@ void glue(helper_vpgatherqd, SUFFIX)(CPUX86State *env, if (v->L(i) >> 31) { target_ulong addr =3D a0 + ((target_ulong)(int64_t)s->Q(i) << scale); - d->L(i) =3D cpu_ldl_data_ra(env, addr, GETPC()); + d->L(i) =3D cpu_ldl_le_data_ra(env, addr, GETPC()); } v->L(i) =3D 0; } @@ -2415,7 +2415,7 @@ void glue(helper_vpgatherqq, SUFFIX)(CPUX86State *env, if (v->Q(i) >> 63) { target_ulong addr =3D a0 + ((target_ulong)(int64_t)s->Q(i) << scale); - d->Q(i) =3D cpu_ldq_data_ra(env, addr, GETPC()); + d->Q(i) =3D cpu_ldq_le_data_ra(env, addr, GETPC()); } v->Q(i) =3D 0; } diff --git a/target/i386/tcg/seg_helper.h b/target/i386/tcg/seg_helper.h index ea98e1a98ed..20ce47d62d9 100644 --- a/target/i386/tcg/seg_helper.h +++ b/target/i386/tcg/seg_helper.h @@ -40,18 +40,18 @@ int cpu_mmu_index_kernel(CPUX86State *env); * and use *_mmuidx_ra directly. */ #define cpu_lduw_kernel_ra(e, p, r) \ - cpu_lduw_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_lduw_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldl_kernel_ra(e, p, r) \ - cpu_ldl_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_ldl_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) #define cpu_ldq_kernel_ra(e, p, r) \ - cpu_ldq_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) + cpu_ldq_le_mmuidx_ra(e, p, cpu_mmu_index_kernel(e), r) =20 #define cpu_stw_kernel_ra(e, p, v, r) \ - cpu_stw_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stw_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stl_kernel_ra(e, p, v, r) \ - cpu_stl_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stl_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) #define cpu_stq_kernel_ra(e, p, v, r) \ - cpu_stq_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) + cpu_stq_le_mmuidx_ra(e, p, v, cpu_mmu_index_kernel(e), r) =20 #define cpu_lduw_kernel(e, p) cpu_lduw_kernel_ra(e, p, 0) #define cpu_ldl_kernel(e, p) cpu_ldl_kernel_ra(e, p, 0) diff --git a/linux-user/vm86.c b/linux-user/vm86.c index 5091d53fb84..4e120875a06 100644 --- a/linux-user/vm86.c +++ b/linux-user/vm86.c @@ -44,7 +44,7 @@ static inline int is_revectored(int nr, struct target_rev= ectored_struct *bitmap) static inline void vm_putw(CPUX86State *env, uint32_t segptr, unsigned int reg16, unsigned int val) { - cpu_stw_data(env, segptr + (reg16 & 0xffff), val); + cpu_stw_le_data(env, segptr + (reg16 & 0xffff), val); } =20 void save_v86_state(CPUX86State *env) @@ -157,7 +157,7 @@ static void do_int(CPUX86State *env, int intno) &ts->vm86plus.int21_revectored)) goto cannot_handle; int_addr =3D (intno << 2); - segoffs =3D cpu_ldl_data(env, int_addr); + segoffs =3D cpu_ldl_le_data(env, int_addr); if ((segoffs >> 16) =3D=3D TARGET_BIOSSEG) goto cannot_handle; LOG_VM86("VM86: emulating int 0x%x. CS:IP=3D%04x:%04x\n", diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 9e7c2d80293..c15a32d60ad 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -30,8 +30,8 @@ void helper_boundw(CPUX86State *env, target_ulong a0, int= v) { int low, high; =20 - low =3D cpu_ldsw_data_ra(env, a0, GETPC()); - high =3D cpu_ldsw_data_ra(env, a0 + 2, GETPC()); + low =3D cpu_ldsw_le_data_ra(env, a0, GETPC()); + high =3D cpu_ldsw_le_data_ra(env, a0 + 2, GETPC()); v =3D (int16_t)v; if (v < low || v > high) { if (env->hflags & HF_MPX_EN_MASK) { @@ -45,8 +45,8 @@ void helper_boundl(CPUX86State *env, target_ulong a0, int= v) { int low, high; =20 - low =3D cpu_ldl_data_ra(env, a0, GETPC()); - high =3D cpu_ldl_data_ra(env, a0 + 4, GETPC()); + low =3D cpu_ldl_le_data_ra(env, a0, GETPC()); + high =3D cpu_ldl_le_data_ra(env, a0 + 4, GETPC()); if (v < low || v > high) { if (env->hflags & HF_MPX_EN_MASK) { env->bndcs_regs.sts =3D 0; diff --git a/target/i386/tcg/mpx_helper.c b/target/i386/tcg/mpx_helper.c index fa8abcc4820..73d33bf5e4a 100644 --- a/target/i386/tcg/mpx_helper.c +++ b/target/i386/tcg/mpx_helper.c @@ -44,7 +44,7 @@ static uint64_t lookup_bte64(CPUX86State *env, uint64_t b= ase, uintptr_t ra) } =20 bde =3D (extract64(base, 20, 28) << 3) + (extract64(bndcsr, 20, 44) <<= 12); - bt =3D cpu_ldq_data_ra(env, bde, ra); + bt =3D cpu_ldq_le_data_ra(env, bde, ra); if ((bt & 1) =3D=3D 0) { env->bndcs_regs.sts =3D bde | 2; raise_exception_ra(env, EXCP05_BOUND, ra); @@ -64,7 +64,7 @@ static uint32_t lookup_bte32(CPUX86State *env, uint32_t b= ase, uintptr_t ra) } =20 bde =3D (extract32(base, 12, 20) << 2) + (bndcsr & TARGET_PAGE_MASK); - bt =3D cpu_ldl_data_ra(env, bde, ra); + bt =3D cpu_ldl_le_data_ra(env, bde, ra); if ((bt & 1) =3D=3D 0) { env->bndcs_regs.sts =3D bde | 2; raise_exception_ra(env, EXCP05_BOUND, ra); @@ -79,9 +79,9 @@ uint64_t helper_bndldx64(CPUX86State *env, target_ulong b= ase, target_ulong ptr) uint64_t bte, lb, ub, pt; =20 bte =3D lookup_bte64(env, base, ra); - lb =3D cpu_ldq_data_ra(env, bte, ra); - ub =3D cpu_ldq_data_ra(env, bte + 8, ra); - pt =3D cpu_ldq_data_ra(env, bte + 16, ra); + lb =3D cpu_ldq_le_data_ra(env, bte, ra); + ub =3D cpu_ldq_le_data_ra(env, bte + 8, ra); + pt =3D cpu_ldq_le_data_ra(env, bte + 16, ra); =20 if (pt !=3D ptr) { lb =3D ub =3D 0; @@ -96,9 +96,9 @@ uint64_t helper_bndldx32(CPUX86State *env, target_ulong b= ase, target_ulong ptr) uint32_t bte, lb, ub, pt; =20 bte =3D lookup_bte32(env, base, ra); - lb =3D cpu_ldl_data_ra(env, bte, ra); - ub =3D cpu_ldl_data_ra(env, bte + 4, ra); - pt =3D cpu_ldl_data_ra(env, bte + 8, ra); + lb =3D cpu_ldl_le_data_ra(env, bte, ra); + ub =3D cpu_ldl_le_data_ra(env, bte + 4, ra); + pt =3D cpu_ldl_le_data_ra(env, bte + 8, ra); =20 if (pt !=3D ptr) { lb =3D ub =3D 0; @@ -113,9 +113,9 @@ void helper_bndstx64(CPUX86State *env, target_ulong bas= e, target_ulong ptr, uint64_t bte; =20 bte =3D lookup_bte64(env, base, ra); - cpu_stq_data_ra(env, bte, lb, ra); - cpu_stq_data_ra(env, bte + 8, ub, ra); - cpu_stq_data_ra(env, bte + 16, ptr, ra); + cpu_stq_le_data_ra(env, bte, lb, ra); + cpu_stq_le_data_ra(env, bte + 8, ub, ra); + cpu_stq_le_data_ra(env, bte + 16, ptr, ra); } =20 void helper_bndstx32(CPUX86State *env, target_ulong base, target_ulong ptr, @@ -125,9 +125,9 @@ void helper_bndstx32(CPUX86State *env, target_ulong bas= e, target_ulong ptr, uint32_t bte; =20 bte =3D lookup_bte32(env, base, ra); - cpu_stl_data_ra(env, bte, lb, ra); - cpu_stl_data_ra(env, bte + 4, ub, ra); - cpu_stl_data_ra(env, bte + 8, ptr, ra); + cpu_stl_le_data_ra(env, bte, lb, ra); + cpu_stl_le_data_ra(env, bte + 4, ub, ra); + cpu_stl_le_data_ra(env, bte + 8, ptr, ra); } =20 void helper_bnd_jmp(CPUX86State *env) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index 227336c4ef2..58aac720119 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -65,20 +65,20 @@ typedef struct StackAccess static void pushw(StackAccess *sa, uint16_t val) { sa->sp -=3D 2; - cpu_stw_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), + cpu_stw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), val, sa->mmu_index, sa->ra); } =20 static void pushl(StackAccess *sa, uint32_t val) { sa->sp -=3D 4; - cpu_stl_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), + cpu_stl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), val, sa->mmu_index, sa->ra); } =20 static uint16_t popw(StackAccess *sa) { - uint16_t ret =3D cpu_lduw_mmuidx_ra(sa->env, + uint16_t ret =3D cpu_lduw_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), sa->mmu_index, sa->ra); sa->sp +=3D 2; @@ -87,7 +87,7 @@ static uint16_t popw(StackAccess *sa) =20 static uint32_t popl(StackAccess *sa) { - uint32_t ret =3D cpu_ldl_mmuidx_ra(sa->env, + uint32_t ret =3D cpu_ldl_le_mmuidx_ra(sa->env, sa->ss_base + (sa->sp & sa->sp_mask), sa->mmu_index, sa->ra); sa->sp +=3D 4; @@ -905,12 +905,12 @@ static void do_interrupt_protected(CPUX86State *env, = int intno, int is_int, static void pushq(StackAccess *sa, uint64_t val) { sa->sp -=3D 8; - cpu_stq_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra); + cpu_stq_le_mmuidx_ra(sa->env, sa->sp, val, sa->mmu_index, sa->ra); } =20 static uint64_t popq(StackAccess *sa) { - uint64_t ret =3D cpu_ldq_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, sa-= >ra); + uint64_t ret =3D cpu_ldq_le_mmuidx_ra(sa->env, sa->sp, sa->mmu_index, = sa->ra); sa->sp +=3D 8; return ret; } @@ -1887,7 +1887,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, pushl(&sa, env->segs[R_SS].selector); pushl(&sa, env->regs[R_ESP]); for (i =3D param_count - 1; i >=3D 0; i--) { - val =3D cpu_ldl_data_ra(env, + val =3D cpu_ldl_le_data_ra(env, old_ssp + ((env->regs[R_ESP] + i= * 4) & old_sp_mask), GETPC()); pushl(&sa, val); @@ -1896,7 +1896,7 @@ void helper_lcall_protected(CPUX86State *env, int new= _cs, target_ulong new_eip, pushw(&sa, env->segs[R_SS].selector); pushw(&sa, env->regs[R_ESP]); for (i =3D param_count - 1; i >=3D 0; i--) { - val =3D cpu_lduw_data_ra(env, + val =3D cpu_lduw_le_data_ra(env, old_ssp + ((env->regs[R_ESP] + = i * 2) & old_sp_mask), GETPC()); pushw(&sa, val); diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/= excp_helper.c index f622b5d588e..d7ea77c8558 100644 --- a/target/i386/tcg/system/excp_helper.c +++ b/target/i386/tcg/system/excp_helper.c @@ -90,7 +90,7 @@ static inline uint32_t ptw_ldl(const PTETranslate *in, ui= nt64_t ra) if (likely(in->haddr)) { return ldl_p(in->haddr); } - return cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); + return cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra) @@ -98,7 +98,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, ui= nt64_t ra) if (likely(in->haddr)) { return ldq_p(in->haddr); } - return cpu_ldq_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); + return cpu_ldq_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, ra); } =20 /* @@ -116,9 +116,9 @@ static bool ptw_setl_slow(const PTETranslate *in, uint3= 2_t old, uint32_t new) cpu_exec_end(cpu); /* Does x86 really perform a rmw cycle on mmio for ptw? */ start_exclusive(); - cmp =3D cpu_ldl_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); + cmp =3D cpu_ldl_le_mmuidx_ra(in->env, in->gaddr, in->ptw_idx, 0); if (cmp =3D=3D old) { - cpu_stl_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); + cpu_stl_le_mmuidx_ra(in->env, in->gaddr, new, in->ptw_idx, 0); } end_exclusive(); cpu_exec_start(cpu); diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index 4b86796518f..3e236094d6f 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -30,13 +30,13 @@ static void svm_save_seg(CPUX86State *env, int mmu_idx, hwaddr addr, const SegmentCache *sc) { - cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), sc->selector, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), sc->base, mmu_idx, 0); - cpu_stl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + cpu_stl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), sc->limit, mmu_idx, 0); - cpu_stw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + cpu_stw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), ((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00), mmu_idx, 0); @@ -58,16 +58,16 @@ static void svm_load_seg(CPUX86State *env, int mmu_idx,= hwaddr addr, unsigned int flags; =20 sc->selector =3D - cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, selector), + cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, select= or), mmu_idx, 0); sc->base =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, base), mmu_idx, 0); sc->limit =3D - cpu_ldl_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), + cpu_ldl_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, limit), mmu_idx, 0); flags =3D - cpu_lduw_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib), + cpu_lduw_le_mmuidx_ra(env, addr + offsetof(struct vmcb_seg, attrib= ), mmu_idx, 0); sc->flags =3D ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12); =20 @@ -507,32 +507,35 @@ void helper_vmload(CPUX86State *env, int aflag) =20 #ifdef TARGET_X86_64 env->kernelgsbase =3D - cpu_ldq_mmuidx_ra(env, - addr + offsetof(struct vmcb, save.kernel_gs_base= ), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.kernel_gs_b= ase), + mmu_idx, 0); env->lstar =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + mmu_idx, 0); env->cstar =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + mmu_idx, 0); env->fmask =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask= ), + mmu_idx, 0); svm_canonicalization(env, &env->kernelgsbase); #endif env->star =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + mmu_idx, 0); env->sysenter_cs =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= cs), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_cs= ), + mmu_idx, 0); env->sysenter_esp =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= esp), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_es= p), + mmu_idx, 0); env->sysenter_eip =3D - cpu_ldq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_= eip), - mmu_idx, 0); + cpu_ldq_le_mmuidx_ra(env, + addr + offsetof(struct vmcb, save.sysenter_ei= p), + mmu_idx, 0); } =20 void helper_vmsave(CPUX86State *env, int aflag) @@ -567,22 +570,22 @@ void helper_vmsave(CPUX86State *env, int aflag) &env->ldt); =20 #ifdef TARGET_X86_64 - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_bas= e), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.kernel_gs_= base), env->kernelgsbase, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.lstar), env->lstar, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.cstar), env->cstar, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sfmask), env->fmask, mmu_idx, 0); #endif - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.star), env->star, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_cs), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_c= s), env->sysenter_cs, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_esp), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_e= sp), env->sysenter_esp, mmu_idx, 0); - cpu_stq_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_eip), + cpu_stq_le_mmuidx_ra(env, addr + offsetof(struct vmcb, save.sysenter_e= ip), env->sysenter_eip, mmu_idx, 0); } =20 --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Use the explicit little-endian variants. [*] RISC-V "V" Vector Extension v1.0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Daniel Henrique Barboza --- target/riscv/vector_helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 2de3358ee86..caa8dd9c125 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ } =20 GEN_VEXT_LD_ELEM(lde_b, uint8_t, H1, ldub) -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw) -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl) -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq) +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le) +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le) +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static inline QEMU_ALWAYS_INLINE \ @@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host) = \ } =20 GEN_VEXT_ST_ELEM(ste_b, uint8_t, H1, stb) -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw) -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl) -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq) +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le) +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le) +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le) =20 static inline QEMU_ALWAYS_INLINE void vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_t= lb, --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143508; cv=none; d=zohomail.com; s=zohoarc; b=PhjiyIGErTFGBlFdhZ+PhBRlQoIoMBo7s2JwT3/gLx9ILSF2knVO3EP9RWW9d/ppMZkomWLkPQasRJhsLI7ISULGz6eEmAJbp81XiPgKSVVnP3dj/m4J5tguiafhRNNtKqftAzUeTBfMm8zNrpJqDUbutK1MJxwgcjaIpWa4+ig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143508; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=NVumjk0F6Tq93V240FNbMOnFtVOEoBWTLGnL0WT9/nA=; b=AEOzbLIVJldN/XE1BmR3CeXHmrCAuG0/i9e4cILipkH0k4zjU1midNX+Z15cSc2SfIBghcjSqKBY0NQzIfajUeuhMRoSj/y0puFn77xNLBEVd3f4M+uM1aNb5V+uIO2YAYv/ooO3ralV7Ep25s//itGUkPLGxoysONNSj1ji4ZM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764143508035156.40074447802317; Tue, 25 Nov 2025 23:51:48 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOAJU-0002FE-6z; Wed, 26 Nov 2025 02:51:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOAIY-0000ik-Vr for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:50:47 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOAIV-0003Rv-Ka for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:50:46 -0500 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-47790b080e4so33488535e9.3 for ; Tue, 25 Nov 2025 23:50:43 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. [88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-479040cfe17sm37505415e9.5.2025.11.25.23.50.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 25 Nov 2025 23:50:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1764143442; x=1764748242; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NVumjk0F6Tq93V240FNbMOnFtVOEoBWTLGnL0WT9/nA=; b=KdBzWpISwyWZSFb8ew5Ot8utkLe7B28W7nI1VNlLjED09lhgVYShDGwaBX9IsOMVGh zGIqBd/EPC5YDRiV5wV9dU5nNXD3UcV4kGG/fVEZc8aP+86q0VN0yIqNNRDjbwxlzDSA CQi75QPtP3iQuseco8TlZQaGB6/uPXQqmUWwQQ4VBlbDDYjh7b5CvgdRTU5gq39BcHAf z06gQUR+bCvVbj6NXmA7NELTsq3kOwoKcanXBUGzr+mfR6BH87lHQ0Da30hl+XEPSu/f 8344sbJumfjJ7Xfur/YOxl471lynoOj6XNav+Di2gAZG8l/S6cWO3RnoDBEDu7TEDCjK ztTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1764143442; x=1764748242; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=NVumjk0F6Tq93V240FNbMOnFtVOEoBWTLGnL0WT9/nA=; b=lC9XCM6mx6Cxl0WrGiGlVtPuIwkVTVCFntwgy0Co5v2bGQLchvQ/UgdIafu2oSxphd yTVQvlxXsWIjdarD/K8sxUh2ACdClGbVXh7QXOrhpaqoN5JIFiij/fyloIo3HDKYl2pF hw0gTb9i+dWi9D3kUNiwgQyMlt8MrBekh7MFWe5/QDXDBf6Ue1LVkjTMbXud+dX1ZJ4p wFtBqfsJLUSAVl73DSHxg61SWIubDc5LSysNjvr2wVr9ftX/aQGUqKJMfUSSeZQb5kYr Suy5BYpfMJjL7/mYIW2EOSVjbOJfwsXK5hdUaCwHKAFCqhf4c0gk9xkVw9B2BSFz01cj F7cw== X-Gm-Message-State: AOJu0YzvMpJiM+KavxHETMGQNVGVVYUUPRUb+kY6EL/G+dWEbXrfBcXX jqH8cR7Garspr6xVVC2c3Q8eqkaa0k/a0u3aS9cdVR0IlXJDan3zLeeaEImL7RKuT/uINYGNBvj Vwx7Y0rICcQ== X-Gm-Gg: ASbGncvzWn0IxcetEFYQDhLMafl/+wKZaHxaJn2T94ag3SdjfctMBEOHI5bhwz63l2x Kg2MQ43Bxxf7ioTlfEHBNeVBuHB1op9s9FXSZhOHRCrMN0mdWkoXp862iSRR6b6UigOW8zQ9voF bbzEfShjFLR6Ok7SZHblsETJk7mmqHQgXKTshX+K3zNsDUDWoZj+LYb4k2t0O+0GYiApZrNi8/4 Bt0688qLGdDe3iWZOdjvPB6KZnD9AubhHVBRddB3UUebP0/9Zwr1hanPqYIIjv5t8Jnv/oKvi1Z 0x7HUXpgmSiaem3qBshHx6+UGyQwXLp/Lvwm1TWoAwtyLlBKB6GL9yblwJF8sgP1oBdjz1nr3ju tG+MsIimZaw6XEHxot8xz7SJsy8xyqbyUG1u9xyvGH5ykCSr2MNN2EsSB3C5J0yrA5wsJHIclf0 tRvSM74tLhIzHT4z0hXnOOMhQ70cNgexY+gQoqEBv4vygunMofahWjXSOwN66Q X-Google-Smtp-Source: AGHT+IHq5BuMvjhiLNMoLOizL7thaIziwm/kDXgDoW1syiZCU98ZLsDg+4utHaUdz/xqq/XULDJRrg== X-Received: by 2002:a05:600c:3511:b0:476:d494:41d2 with SMTP id 5b1f17b1804b1-477c112f7b1mr178290295e9.29.1764143441744; Tue, 25 Nov 2025 23:50:41 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato Subject: [PATCH-for-11.0 v2 05/12] target/rx: Use little-endian variant of cpu_ld/st_data*() Date: Wed, 26 Nov 2025 08:49:56 +0100 Message-ID: <20251126075003.4826-6-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251126075003.4826-1-philmd@linaro.org> References: <20251126075003.4826-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1764143509570019200 We only build the RX target using little endianness order, therefore the cpu_ld/st_data*() definitions expand to the little endian declarations. Use the explicit little-endian variants. Mechanical change running: $ tgt=3Drx; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/rx/helper.c | 14 +++++++------- target/rx/op_helper.c | 6 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/rx/helper.c b/target/rx/helper.c index e9a7aaf610d..83cd491eb4a 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -68,10 +68,10 @@ void rx_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); + cpu_stl_le_data(env, env->isp, save_psw); env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); - env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); + cpu_stl_le_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_le_data(env, env->intb + env->ack_irq * 4); env->psw_ipl =3D env->ack_ipl; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); qemu_set_irq(env->ack, env->ack_irq); @@ -82,14 +82,14 @@ void rx_cpu_do_interrupt(CPUState *cs) const char *expname =3D "unknown exception"; =20 env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); + cpu_stl_le_data(env, env->isp, save_psw); env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); + cpu_stl_le_data(env, env->isp, env->pc); =20 if (vec < 0x100) { - env->pc =3D cpu_ldl_data(env, 0xffffff80 + vec * 4); + env->pc =3D cpu_ldl_le_data(env, 0xffffff80 + vec * 4); } else { - env->pc =3D cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); + env->pc =3D cpu_ldl_le_data(env, env->intb + (vec & 0xff) * 4); } =20 if (vec =3D=3D 30) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index 2b190a4b2cf..ca3e9e85fc7 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -217,20 +217,20 @@ void helper_scmpu(CPURXState *env) static uint32_t (* const cpu_ldufn[])(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) =3D { - cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, + cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra, }; =20 static uint32_t (* const cpu_ldfn[])(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr) =3D { - cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, + cpu_ldub_data_ra, cpu_lduw_le_data_ra, cpu_ldl_le_data_ra, }; =20 static void (* const cpu_stfn[])(CPUArchState *env, abi_ptr ptr, uint32_t val, uintptr_t retaddr) =3D { - cpu_stb_data_ra, cpu_stw_data_ra, cpu_stl_data_ra, + cpu_stb_data_ra, cpu_stw_le_data_ra, cpu_stl_le_data_ra, }; =20 void helper_sstr(CPURXState *env, uint32_t sz) --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143595; cv=none; d=zohomail.com; s=zohoarc; b=WIP/J4lUoTAqtiMRJuS/VrxvkHs6K92EqJph9SOmB9wco7yjhHEUbcjWNiNVKJehojyDYSlpyHh8DN0DOrj3xr5qPL81MWQNveu1rBk9KaS14+a8VefHADKtlS6ZMC6XNFHYrjWfC8AGhr6Z3lC5okIOcVF86pmb8wJQqAMVG6I= ARC-Message-Signature: i=1; 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Use the explicit little-endian variants. Mechanical change running: $ tgt=3Dtricore; \ end=3Dle; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting spaces style manually to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/tricore/op_helper.c | 152 ++++++++++++++++++------------------- 1 file changed, 76 insertions(+), 76 deletions(-) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 2c8281a67e0..fde2c0f8383 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -2451,84 +2451,84 @@ static bool cdc_zero(uint32_t *psw) =20 static void save_context_upper(CPUTriCoreState *env, uint32_t ea) { - cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, psw_read(env)); - cpu_stl_data(env, ea+8, env->gpr_a[10]); - cpu_stl_data(env, ea+12, env->gpr_a[11]); - cpu_stl_data(env, ea+16, env->gpr_d[8]); - cpu_stl_data(env, ea+20, env->gpr_d[9]); - cpu_stl_data(env, ea+24, env->gpr_d[10]); - cpu_stl_data(env, ea+28, env->gpr_d[11]); - cpu_stl_data(env, ea+32, env->gpr_a[12]); - cpu_stl_data(env, ea+36, env->gpr_a[13]); - cpu_stl_data(env, ea+40, env->gpr_a[14]); - cpu_stl_data(env, ea+44, env->gpr_a[15]); - cpu_stl_data(env, ea+48, env->gpr_d[12]); - cpu_stl_data(env, ea+52, env->gpr_d[13]); - cpu_stl_data(env, ea+56, env->gpr_d[14]); - cpu_stl_data(env, ea+60, env->gpr_d[15]); + cpu_stl_le_data(env, ea, env->PCXI); + cpu_stl_le_data(env, ea + 4, psw_read(env)); + cpu_stl_le_data(env, ea + 8, env->gpr_a[10]); + cpu_stl_le_data(env, ea + 12, env->gpr_a[11]); + cpu_stl_le_data(env, ea + 16, env->gpr_d[8]); + cpu_stl_le_data(env, ea + 20, env->gpr_d[9]); + cpu_stl_le_data(env, ea + 24, env->gpr_d[10]); + cpu_stl_le_data(env, ea + 28, env->gpr_d[11]); + cpu_stl_le_data(env, ea + 32, env->gpr_a[12]); + cpu_stl_le_data(env, ea + 36, env->gpr_a[13]); + cpu_stl_le_data(env, ea + 40, env->gpr_a[14]); + cpu_stl_le_data(env, ea + 44, env->gpr_a[15]); + cpu_stl_le_data(env, ea + 48, env->gpr_d[12]); + cpu_stl_le_data(env, ea + 52, env->gpr_d[13]); + cpu_stl_le_data(env, ea + 56, env->gpr_d[14]); + cpu_stl_le_data(env, ea + 60, env->gpr_d[15]); } =20 static void save_context_lower(CPUTriCoreState *env, uint32_t ea) { - cpu_stl_data(env, ea, env->PCXI); - cpu_stl_data(env, ea+4, env->gpr_a[11]); - cpu_stl_data(env, ea+8, env->gpr_a[2]); - cpu_stl_data(env, ea+12, env->gpr_a[3]); - cpu_stl_data(env, ea+16, env->gpr_d[0]); - cpu_stl_data(env, ea+20, env->gpr_d[1]); - cpu_stl_data(env, ea+24, env->gpr_d[2]); - cpu_stl_data(env, ea+28, env->gpr_d[3]); - cpu_stl_data(env, ea+32, env->gpr_a[4]); - cpu_stl_data(env, ea+36, env->gpr_a[5]); - cpu_stl_data(env, ea+40, env->gpr_a[6]); - cpu_stl_data(env, ea+44, env->gpr_a[7]); - cpu_stl_data(env, ea+48, env->gpr_d[4]); - cpu_stl_data(env, ea+52, env->gpr_d[5]); - cpu_stl_data(env, ea+56, env->gpr_d[6]); - cpu_stl_data(env, ea+60, env->gpr_d[7]); + cpu_stl_le_data(env, ea, env->PCXI); + cpu_stl_le_data(env, ea + 4, env->gpr_a[11]); + cpu_stl_le_data(env, ea + 8, env->gpr_a[2]); + cpu_stl_le_data(env, ea + 12, env->gpr_a[3]); + cpu_stl_le_data(env, ea + 16, env->gpr_d[0]); + cpu_stl_le_data(env, ea + 20, env->gpr_d[1]); + cpu_stl_le_data(env, ea + 24, env->gpr_d[2]); + cpu_stl_le_data(env, ea + 28, env->gpr_d[3]); + cpu_stl_le_data(env, ea + 32, env->gpr_a[4]); + cpu_stl_le_data(env, ea + 36, env->gpr_a[5]); + cpu_stl_le_data(env, ea + 40, env->gpr_a[6]); + cpu_stl_le_data(env, ea + 44, env->gpr_a[7]); + cpu_stl_le_data(env, ea + 48, env->gpr_d[4]); + cpu_stl_le_data(env, ea + 52, env->gpr_d[5]); + cpu_stl_le_data(env, ea + 56, env->gpr_d[6]); + cpu_stl_le_data(env, ea + 60, env->gpr_d[7]); } =20 static void restore_context_upper(CPUTriCoreState *env, uint32_t ea, uint32_t *new_PCXI, uint32_t *new_PSW) { - *new_PCXI =3D cpu_ldl_data(env, ea); - *new_PSW =3D cpu_ldl_data(env, ea+4); - env->gpr_a[10] =3D cpu_ldl_data(env, ea+8); - env->gpr_a[11] =3D cpu_ldl_data(env, ea+12); - env->gpr_d[8] =3D cpu_ldl_data(env, ea+16); - env->gpr_d[9] =3D cpu_ldl_data(env, ea+20); - env->gpr_d[10] =3D cpu_ldl_data(env, ea+24); - env->gpr_d[11] =3D cpu_ldl_data(env, ea+28); - env->gpr_a[12] =3D cpu_ldl_data(env, ea+32); - env->gpr_a[13] =3D cpu_ldl_data(env, ea+36); - env->gpr_a[14] =3D cpu_ldl_data(env, ea+40); - env->gpr_a[15] =3D cpu_ldl_data(env, ea+44); - env->gpr_d[12] =3D cpu_ldl_data(env, ea+48); - env->gpr_d[13] =3D cpu_ldl_data(env, ea+52); - env->gpr_d[14] =3D cpu_ldl_data(env, ea+56); - env->gpr_d[15] =3D cpu_ldl_data(env, ea+60); + *new_PCXI =3D cpu_ldl_le_data(env, ea); + *new_PSW =3D cpu_ldl_le_data(env, ea + 4); + env->gpr_a[10] =3D cpu_ldl_le_data(env, ea + 8); + env->gpr_a[11] =3D cpu_ldl_le_data(env, ea + 12); + env->gpr_d[8] =3D cpu_ldl_le_data(env, ea + 16); + env->gpr_d[9] =3D cpu_ldl_le_data(env, ea + 20); + env->gpr_d[10] =3D cpu_ldl_le_data(env, ea + 24); + env->gpr_d[11] =3D cpu_ldl_le_data(env, ea + 28); + env->gpr_a[12] =3D cpu_ldl_le_data(env, ea + 32); + env->gpr_a[13] =3D cpu_ldl_le_data(env, ea + 36); + env->gpr_a[14] =3D cpu_ldl_le_data(env, ea + 40); + env->gpr_a[15] =3D cpu_ldl_le_data(env, ea + 44); + env->gpr_d[12] =3D cpu_ldl_le_data(env, ea + 48); + env->gpr_d[13] =3D cpu_ldl_le_data(env, ea + 52); + env->gpr_d[14] =3D cpu_ldl_le_data(env, ea + 56); + env->gpr_d[15] =3D cpu_ldl_le_data(env, ea + 60); } =20 static void restore_context_lower(CPUTriCoreState *env, uint32_t ea, uint32_t *ra, uint32_t *pcxi) { - *pcxi =3D cpu_ldl_data(env, ea); - *ra =3D cpu_ldl_data(env, ea+4); - env->gpr_a[2] =3D cpu_ldl_data(env, ea+8); - env->gpr_a[3] =3D cpu_ldl_data(env, ea+12); - env->gpr_d[0] =3D cpu_ldl_data(env, ea+16); - env->gpr_d[1] =3D cpu_ldl_data(env, ea+20); - env->gpr_d[2] =3D cpu_ldl_data(env, ea+24); - env->gpr_d[3] =3D cpu_ldl_data(env, ea+28); - env->gpr_a[4] =3D cpu_ldl_data(env, ea+32); - env->gpr_a[5] =3D cpu_ldl_data(env, ea+36); - env->gpr_a[6] =3D cpu_ldl_data(env, ea+40); - env->gpr_a[7] =3D cpu_ldl_data(env, ea+44); - env->gpr_d[4] =3D cpu_ldl_data(env, ea+48); - env->gpr_d[5] =3D cpu_ldl_data(env, ea+52); - env->gpr_d[6] =3D cpu_ldl_data(env, ea+56); - env->gpr_d[7] =3D cpu_ldl_data(env, ea+60); + *pcxi =3D cpu_ldl_le_data(env, ea); + *ra =3D cpu_ldl_le_data(env, ea + 4); + env->gpr_a[2] =3D cpu_ldl_le_data(env, ea + 8); + env->gpr_a[3] =3D cpu_ldl_le_data(env, ea + 12); + env->gpr_d[0] =3D cpu_ldl_le_data(env, ea + 16); + env->gpr_d[1] =3D cpu_ldl_le_data(env, ea + 20); + env->gpr_d[2] =3D cpu_ldl_le_data(env, ea + 24); + env->gpr_d[3] =3D cpu_ldl_le_data(env, ea + 28); + env->gpr_a[4] =3D cpu_ldl_le_data(env, ea + 32); + env->gpr_a[5] =3D cpu_ldl_le_data(env, ea + 36); + env->gpr_a[6] =3D cpu_ldl_le_data(env, ea + 40); + env->gpr_a[7] =3D cpu_ldl_le_data(env, ea + 44); + env->gpr_d[4] =3D cpu_ldl_le_data(env, ea + 48); + env->gpr_d[5] =3D cpu_ldl_le_data(env, ea + 52); + env->gpr_d[6] =3D cpu_ldl_le_data(env, ea + 56); + env->gpr_d[7] =3D cpu_ldl_le_data(env, ea + 60); } =20 void helper_call(CPUTriCoreState *env, uint32_t next_pc) @@ -2566,7 +2566,7 @@ void helper_call(CPUTriCoreState *env, uint32_t next_= pc) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2632,7 +2632,7 @@ void helper_ret(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * wo= rd); */ restore_context_upper(env, ea, &new_PCXI, &new_PSW); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* FCX[19: 0] =3D PCXI[19: 0]; */ env->FCX =3D (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff); /* PCXI =3D new_PCXI; */ @@ -2662,7 +2662,7 @@ void helper_bisr(CPUTriCoreState *env, uint32_t const= 9) ea =3D ((env->FCX & 0xf0000) << 12) + ((env->FCX & 0xffff) << 6); =20 /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, A[11], A[2], A[3], D[0], D[1], D[2], D[= 3], A[4] , A[5], A[6], A[7], D[4], D[5], D[6], D[7]}; */ save_context_lower(env, ea); @@ -2726,7 +2726,7 @@ void helper_rfe(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * word= ); */ restore_context_upper(env, ea, &new_PCXI, &new_PSW); /* M(EA, word) =3D FCX;*/ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* FCX[19: 0] =3D PCXI[19: 0]; */ env->FCX =3D (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff); /* PCXI =3D new_PCXI; */ @@ -2744,10 +2744,10 @@ void helper_rfm(CPUTriCoreState *env) icr_set_ccpn(env, pcxi_get_pcpn(env)); =20 /* {PCXI, PSW, A[10], A[11]} =3D M(DCX, 4 * word); */ - env->PCXI =3D cpu_ldl_data(env, env->DCX); - psw_write(env, cpu_ldl_data(env, env->DCX+4)); - env->gpr_a[10] =3D cpu_ldl_data(env, env->DCX+8); - env->gpr_a[11] =3D cpu_ldl_data(env, env->DCX+12); + env->PCXI =3D cpu_ldl_le_data(env, env->DCX); + psw_write(env, cpu_ldl_le_data(env, env->DCX+4)); + env->gpr_a[10] =3D cpu_ldl_le_data(env, env->DCX+8); + env->gpr_a[11] =3D cpu_ldl_le_data(env, env->DCX+12); =20 if (tricore_has_feature(env, TRICORE_FEATURE_131)) { env->DBGTCR =3D 0; @@ -2794,7 +2794,7 @@ void helper_svlcx(CPUTriCoreState *env) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2837,7 +2837,7 @@ void helper_svucx(CPUTriCoreState *env) ea =3D ((env->FCX & MASK_FCX_FCXS) << 12) + ((env->FCX & MASK_FCX_FCXO) << 6); /* new_FCX =3D M(EA, word); */ - new_FCX =3D cpu_ldl_data(env, ea); + new_FCX =3D cpu_ldl_le_data(env, ea); /* M(EA, 16 * word) =3D {PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D= [11], A[12], A[13], A[14], A[15], D[12], D[13], D[14], D[15]}; */ @@ -2887,9 +2887,9 @@ void helper_rslcx(CPUTriCoreState *env) A[13], A[14], A[15], D[12], D[13], D[14], D[15]} =3D M(EA, 16 * wo= rd); */ restore_context_lower(env, ea, &env->gpr_a[11], &new_PCXI); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); /* M(EA, word) =3D FCX; */ - cpu_stl_data(env, ea, env->FCX); + cpu_stl_le_data(env, ea, env->FCX); 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Dm68k; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Then adapting indentation in do_stack_frame() to pass checkpatch.pl. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/fpu_helper.c | 12 +++--- target/m68k/op_helper.c | 91 ++++++++++++++++++++-------------------- 2 files changed, 52 insertions(+), 51 deletions(-) diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c index 56012863c85..f49f841d489 100644 --- a/target/m68k/fpu_helper.c +++ b/target/m68k/fpu_helper.c @@ -510,8 +510,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32= _t addr, FPReg *fp, uint32_t high; uint64_t low; =20 - high =3D cpu_ldl_data_ra(env, addr, ra); - low =3D cpu_ldq_data_ra(env, addr + 4, ra); + high =3D cpu_ldl_be_data_ra(env, addr, ra); + low =3D cpu_ldq_be_data_ra(env, addr + 4, ra); =20 fp->l.upper =3D high >> 16; fp->l.lower =3D low; @@ -522,8 +522,8 @@ static int cpu_ld_floatx80_ra(CPUM68KState *env, uint32= _t addr, FPReg *fp, static int cpu_st_floatx80_ra(CPUM68KState *env, uint32_t addr, FPReg *fp, uintptr_t ra) { - cpu_stl_data_ra(env, addr, fp->l.upper << 16, ra); - cpu_stq_data_ra(env, addr + 4, fp->l.lower, ra); + cpu_stl_be_data_ra(env, addr, fp->l.upper << 16, ra); + cpu_stq_be_data_ra(env, addr + 4, fp->l.lower, ra); =20 return 12; } @@ -533,7 +533,7 @@ static int cpu_ld_float64_ra(CPUM68KState *env, uint32_= t addr, FPReg *fp, { uint64_t val; =20 - val =3D cpu_ldq_data_ra(env, addr, ra); + val =3D cpu_ldq_be_data_ra(env, addr, ra); fp->d =3D float64_to_floatx80(*(float64 *)&val, &env->fp_status); =20 return 8; @@ -545,7 +545,7 @@ static int cpu_st_float64_ra(CPUM68KState *env, uint32_= t addr, FPReg *fp, float64 val; =20 val =3D floatx80_to_float64(fp->d, &env->fp_status); - cpu_stq_data_ra(env, addr, *(uint64_t *)&val, ra); + cpu_stq_be_data_ra(env, addr, *(uint64_t *)&val, ra); =20 return 8; } diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index e9c20a8e032..7139a8445d4 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -32,8 +32,8 @@ static void cf_rte(CPUM68KState *env) uint32_t fmt; =20 sp =3D env->aregs[7]; - fmt =3D cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); - env->pc =3D cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); + fmt =3D cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); sp |=3D (fmt >> 28) & 3; env->aregs[7] =3D sp + 8; =20 @@ -48,13 +48,13 @@ static void m68k_rte(CPUM68KState *env) =20 sp =3D env->aregs[7]; throwaway: - sr =3D cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + sr =3D cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 2; - env->pc =3D cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 4; if (m68k_feature(env, M68K_FEATURE_EXCEPTION_FORMAT_VEC)) { /* all except 68000 */ - fmt =3D cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); + fmt =3D cpu_lduw_be_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); sp +=3D 2; switch (fmt >> 12) { case 0: @@ -250,12 +250,12 @@ static void cf_interrupt_all(CPUM68KState *env, int i= s_hw) /* ??? This could cause MMU faults. */ sp &=3D ~3; sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0); sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0); env->aregs[7] =3D sp; /* Jump to vector. */ - env->pc =3D cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, = 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_ID= X, 0); =20 do_plugin_vcpu_interrupt_cb(cs, retaddr); } @@ -270,24 +270,25 @@ static inline void do_stack_frame(CPUM68KState *env, = uint32_t *sp, switch (format) { case 4: *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0); *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); break; case 3: case 2: *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0); break; } *sp -=3D 2; - cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index = << 2), - MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, *sp, + (format << 12) + (cs->exception_index << 2), + MMU_KERNEL_IDX, 0); } *sp -=3D 4; - cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0); *sp -=3D 2; - cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0); } =20 static void m68k_interrupt_all(CPUM68KState *env, int is_hw) @@ -346,49 +347,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int= is_hw) env->mmu.fault =3D true; /* push data 3 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* push data 2 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* push data 1 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 1 / push data 0 */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 1 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 data */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 data */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); /* fault address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); /* write back 1 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 2 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* write back 3 status */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0); /* special status word */ sp -=3D 2; - cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0); + cpu_stw_be_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0); /* effective address */ sp -=3D 4; - cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); + cpu_stl_be_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0); =20 do_stack_frame(env, &sp, 7, oldsr, 0, env->pc); env->mmu.fault =3D false; @@ -436,7 +437,7 @@ static void m68k_interrupt_all(CPUM68KState *env, int i= s_hw) =20 env->aregs[7] =3D sp; /* Jump to vector. */ - env->pc =3D cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, = 0); + env->pc =3D cpu_ldl_be_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_ID= X, 0); =20 do_plugin_vcpu_interrupt_cb(cs, last_pc); } @@ -784,11 +785,11 @@ void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, = uint32_t a1, uint32_t a2) int16_t l1, l2; uintptr_t ra =3D GETPC(); =20 - l1 =3D cpu_lduw_data_ra(env, a1, ra); - l2 =3D cpu_lduw_data_ra(env, a2, ra); + l1 =3D cpu_lduw_be_data_ra(env, a1, ra); + l2 =3D cpu_lduw_be_data_ra(env, a2, ra); if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stw_data_ra(env, a1, u1, ra); - cpu_stw_data_ra(env, a2, u2, ra); + cpu_stw_be_data_ra(env, a1, u1, ra); + cpu_stw_be_data_ra(env, a2, u2, ra); } =20 if (c1 !=3D l1) { @@ -845,11 +846,11 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs= , uint32_t a1, uint32_t a2, } } else { /* We're executing in a serial context -- no need to be atomic. */ - l1 =3D cpu_ldl_data_ra(env, a1, ra); - l2 =3D cpu_ldl_data_ra(env, a2, ra); + l1 =3D cpu_ldl_be_data_ra(env, a1, ra); + l2 =3D cpu_ldl_be_data_ra(env, a2, ra); if (l1 =3D=3D c1 && l2 =3D=3D c2) { - cpu_stl_data_ra(env, a1, u1, ra); - cpu_stl_data_ra(env, a2, u2, ra); + cpu_stl_be_data_ra(env, a1, u1, ra); + cpu_stl_be_data_ra(env, a2, u2, ra); } } =20 @@ -951,12 +952,12 @@ static uint64_t bf_load(CPUM68KState *env, uint32_t a= ddr, int blen, case 0: return cpu_ldub_data_ra(env, addr, ra); case 1: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); case 2: case 3: - return cpu_ldl_data_ra(env, addr, ra); + return cpu_ldl_be_data_ra(env, addr, ra); case 4: - return cpu_ldq_data_ra(env, addr, ra); + return cpu_ldq_be_data_ra(env, addr, ra); default: g_assert_not_reached(); } @@ -970,14 +971,14 @@ static void bf_store(CPUM68KState *env, uint32_t addr= , int blen, cpu_stb_data_ra(env, addr, data, ra); break; case 1: - cpu_stw_data_ra(env, addr, data, ra); + cpu_stw_be_data_ra(env, addr, data, ra); break; case 2: case 3: - cpu_stl_data_ra(env, addr, data, ra); + cpu_stl_be_data_ra(env, addr, data, ra); break; case 4: - cpu_stq_data_ra(env, addr, data, ra); + cpu_stq_be_data_ra(env, addr, data, ra); break; default: g_assert_not_reached(); --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143517; cv=none; d=zohomail.com; s=zohoarc; b=QXsO9xFudWX7iLjDYVZf5aOaTrbdjJvizWzEQ5CYnJQaARl4CBixuPHPbugTd7kI8DzGO2+o94+eTwETFcL3/lOk2Tp6GIDc3gxn3t81kg3epFF3iw9jkGaoFfYGztP3PE6ItEhXoHxhFMiwBehcF0sPTdnroyUbJCPY5zUssxw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143517; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Ds390x; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- target/s390x/tcg/mem_helper.c | 48 +++++++++++++++++------------------ target/s390x/tcg/vec_helper.c | 8 +++--- 2 files changed, 28 insertions(+), 28 deletions(-) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 24675fc818d..482c3febf91 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -101,7 +101,7 @@ static inline uint64_t cpu_ldusize_data_ra(CPUS390XStat= e *env, uint64_t addr, case 1: return cpu_ldub_data_ra(env, addr, ra); case 2: - return cpu_lduw_data_ra(env, addr, ra); + return cpu_lduw_be_data_ra(env, addr, ra); default: abort(); } @@ -117,7 +117,7 @@ static inline void cpu_stsize_data_ra(CPUS390XState *en= v, uint64_t addr, cpu_stb_data_ra(env, addr, value, ra); break; case 2: - cpu_stw_data_ra(env, addr, value, ra); + cpu_stw_be_data_ra(env, addr, value, ra); break; default: abort(); @@ -865,7 +865,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uin= t32_t r2) env->cc_op =3D 2; return; } - v =3D cpu_lduw_data_ra(env, str + len, ra); + v =3D cpu_lduw_be_data_ra(env, str + len, ra); if (v =3D=3D c) { /* Character found. Set R1 to the location; R2 is unmodified.= */ env->cc_op =3D 1; @@ -1022,7 +1022,7 @@ void HELPER(lam)(CPUS390XState *env, uint32_t r1, uin= t64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - env->aregs[i] =3D cpu_ldl_data_ra(env, a2, ra); + env->aregs[i] =3D cpu_ldl_be_data_ra(env, a2, ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1042,7 +1042,7 @@ void HELPER(stam)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, a2, env->aregs[i], ra); + cpu_stl_be_data_ra(env, a2, env->aregs[i], ra); a2 +=3D 4; =20 if (i =3D=3D r3) { @@ -1363,7 +1363,7 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, =20 /* Process full words as available. */ for (len =3D 0; len + 4 <=3D max_len; len +=3D 4, src +=3D 4) { - cksm +=3D (uint32_t)cpu_ldl_data_ra(env, src, ra); + cksm +=3D (uint32_t)cpu_ldl_be_data_ra(env, src, ra); } =20 switch (max_len - len) { @@ -1372,11 +1372,11 @@ Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, len +=3D 1; break; case 2: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; len +=3D 2; break; case 3: - cksm +=3D cpu_lduw_data_ra(env, src, ra) << 16; + cksm +=3D cpu_lduw_be_data_ra(env, src, ra) << 16; cksm +=3D cpu_ldub_data_ra(env, src + 2, ra) << 8; len +=3D 3; break; @@ -1955,7 +1955,7 @@ void HELPER(lctlg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint64_t val =3D cpu_ldq_data_ra(env, src, ra); + uint64_t val =3D cpu_ldq_be_data_ra(env, src, ra); if (env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; } @@ -1992,7 +1992,7 @@ void HELPER(lctl)(CPUS390XState *env, uint32_t r1, ui= nt64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - uint32_t val =3D cpu_ldl_data_ra(env, src, ra); + uint32_t val =3D cpu_ldl_be_data_ra(env, src, ra); uint64_t val64 =3D deposit64(env->cregs[i], 0, 32, val); if ((uint32_t)env->cregs[i] !=3D val && i >=3D 9 && i <=3D 11) { PERchanged =3D true; @@ -2028,7 +2028,7 @@ void HELPER(stctg)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stq_data_ra(env, dest, env->cregs[i], ra); + cpu_stq_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint64_t); =20 if (i =3D=3D r3) { @@ -2048,7 +2048,7 @@ void HELPER(stctl)(CPUS390XState *env, uint32_t r1, u= int64_t a2, uint32_t r3) } =20 for (i =3D r1;; i =3D (i + 1) % 16) { - cpu_stl_data_ra(env, dest, env->cregs[i], ra); + cpu_stl_be_data_ra(env, dest, env->cregs[i], ra); dest +=3D sizeof(uint32_t); =20 if (i =3D=3D r3) { @@ -2065,7 +2065,7 @@ uint32_t HELPER(testblock)(CPUS390XState *env, uint64= _t real_addr) real_addr =3D wrap_address(env, real_addr) & TARGET_PAGE_MASK; =20 for (i =3D 0; i < TARGET_PAGE_SIZE; i +=3D 8) { - cpu_stq_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, real_addr + i, 0, MMU_REAL_IDX, ra); } =20 return 0; @@ -2324,11 +2324,11 @@ void HELPER(idte)(CPUS390XState *env, uint64_t r1, = uint64_t r2, uint32_t m4) for (i =3D 0; i < entries; i++) { /* addresses are not wrapped in 24/31bit mode but table index = is */ raddr =3D table + ((index + i) & 0x7ff) * sizeof(entry); - entry =3D cpu_ldq_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); + entry =3D cpu_ldq_be_mmuidx_ra(env, raddr, MMU_REAL_IDX, ra); if (!(entry & REGION_ENTRY_I)) { /* we are allowed to not store if already invalid */ entry |=3D REGION_ENTRY_I; - cpu_stq_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, raddr, entry, MMU_REAL_IDX, ra); } } } @@ -2355,9 +2355,9 @@ void HELPER(ipte)(CPUS390XState *env, uint64_t pto, u= int64_t vaddr, pte_addr +=3D VADDR_PAGE_TX(vaddr) * 8; =20 /* Mark the page table entry as invalid */ - pte =3D cpu_ldq_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); + pte =3D cpu_ldq_be_mmuidx_ra(env, pte_addr, MMU_REAL_IDX, ra); pte |=3D PAGE_ENTRY_I; - cpu_stq_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); + cpu_stq_be_mmuidx_ra(env, pte_addr, pte, MMU_REAL_IDX, ra); =20 /* XXX we exploit the fact that Linux passes the exact virtual address here - it's not obliged to! */ @@ -2695,7 +2695,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 0; } - s0 =3D cpu_lduw_data_ra(env, addr, ra); + s0 =3D cpu_lduw_be_data_ra(env, addr, ra); if ((s0 & 0xfc00) !=3D 0xd800) { /* one word character */ l =3D 2; @@ -2706,7 +2706,7 @@ static int decode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - s1 =3D cpu_lduw_data_ra(env, addr + 2, ra); + s1 =3D cpu_lduw_be_data_ra(env, addr + 2, ra); c =3D extract32(s0, 6, 4) + 1; c =3D (c << 6) | (s0 & 0x3f); c =3D (c << 10) | (s1 & 0x3ff); @@ -2730,7 +2730,7 @@ static int decode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 0; } - c =3D cpu_ldl_data_ra(env, addr, ra); + c =3D cpu_ldl_be_data_ra(env, addr, ra); if ((c >=3D 0xd800 && c <=3D 0xdbff) || c > 0x10ffff) { /* invalid unicode character */ return 2; @@ -2792,7 +2792,7 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 2) { return 1; } - cpu_stw_data_ra(env, addr, c, ra); + cpu_stw_be_data_ra(env, addr, c, ra); *olen =3D 2; } else { /* two word character */ @@ -2802,8 +2802,8 @@ static int encode_utf16(CPUS390XState *env, uint64_t = addr, uint64_t ilen, d1 =3D 0xdc00 | extract32(c, 0, 10); d0 =3D 0xd800 | extract32(c, 10, 6); d0 =3D deposit32(d0, 6, 4, extract32(c, 16, 5) - 1); - cpu_stw_data_ra(env, addr + 0, d0, ra); - cpu_stw_data_ra(env, addr + 2, d1, ra); + cpu_stw_be_data_ra(env, addr + 0, d0, ra); + cpu_stw_be_data_ra(env, addr + 2, d1, ra); *olen =3D 4; } =20 @@ -2816,7 +2816,7 @@ static int encode_utf32(CPUS390XState *env, uint64_t = addr, uint64_t ilen, if (ilen < 4) { return 1; } - cpu_stl_data_ra(env, addr, c, ra); + cpu_stl_be_data_ra(env, addr, c, ra); *olen =3D 4; return -1; } diff --git a/target/s390x/tcg/vec_helper.c b/target/s390x/tcg/vec_helper.c index 46ec4a947dd..304745c971b 100644 --- a/target/s390x/tcg/vec_helper.c +++ b/target/s390x/tcg/vec_helper.c @@ -45,9 +45,9 @@ void HELPER(vll)(CPUS390XState *env, void *v1, uint64_t a= ddr, uint64_t bytes) if (likely(bytes >=3D 16)) { uint64_t t0, t1; =20 - t0 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t0 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); addr =3D wrap_address(env, addr + 8); - t1 =3D cpu_ldq_data_ra(env, addr, GETPC()); + t1 =3D cpu_ldq_be_data_ra(env, addr, GETPC()); s390_vec_write_element64(v1, 0, t0); s390_vec_write_element64(v1, 1, t1); } else { @@ -195,9 +195,9 @@ void HELPER(vstl)(CPUS390XState *env, const void *v1, u= int64_t addr, probe_write_access(env, addr, MIN(bytes, 16), GETPC()); =20 if (likely(bytes >=3D 16)) { - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 0), GETP= C()); addr =3D wrap_address(env, addr + 8); - cpu_stq_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETPC()= ); + cpu_stq_be_data_ra(env, addr, s390_vec_read_element64(v1, 1), GETP= C()); } else { int i; =20 --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Use the explicit big-endian variants. Mechanical change running: $ tgt=3Dsparc; \ end=3Dbe; \ for op in data mmuidx_ra; do \ for ac in uw sw l q; do \ sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; for ac in w l q; do \ sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \ $(git grep -l cpu_ target/${tgt}/); \ done; done Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/sparc/ldst_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 2c63eb9e036..bd0257d313a 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1228,13 +1228,13 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_u= long addr, ret =3D cpu_ldub_data(env, addr); break; case 2: - ret =3D cpu_lduw_data(env, addr); + ret =3D cpu_lduw_be_data(env, addr); break; case 4: - ret =3D cpu_ldl_data(env, addr); + ret =3D cpu_ldl_be_data(env, addr); break; case 8: - ret =3D cpu_ldq_data(env, addr); + ret =3D cpu_ldq_be_data(env, addr); break; default: g_assert_not_reached(); --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143540; cv=none; d=zohomail.com; s=zohoarc; b=FpXckyrvdgVII3+dzalD9mlQDt3+ujx0swJMAHuL13GVTxuzI0m1A4UHUrkzqZOKgfMld0uYdnBkXcLLWdrruAQKduX3Okrm5gSRvah6CE1KbSBwflqFw30+t1vkO58ChsgSq+WneBYcXKpMh2mSwSZJrOcYSaq7mIZkCfT+inQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143540; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=yQ3G/f5z9MwEGa9QMBSOfQ0OhqIrmAfETxxhBlriST8=; b=Xzkb/9hZ9CgGXgUf/p7cWAOQ7Z7Q1A8qHioA9WDXspXbUo9wnI3ILXnN6PFRlXh3hyeS8kaoTUpFNBciBXFXJxrZyiWx+Pc4l+qEL1A7sY2i+HFjwVHBgdnYqyfAlSKgFV2A8QlmmPR95kJNnd0/gOR48tX4iVukZA9sf9gU52M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764143540659194.67373828051643; Tue, 25 Nov 2025 23:52:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOAJc-0003FL-AQ; Wed, 26 Nov 2025 02:51:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOAJ6-0001Ga-JB for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:26 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOAJ4-0003X4-9S for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:19 -0500 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-477563e28a3so3748205e9.1 for ; Tue, 25 Nov 2025 23:51:17 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/sh4/op_helper.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 557b1bf4972..63515cc5e6c 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -143,7 +143,11 @@ void helper_ocbi(CPUSH4State *env, uint32_t address) if ((a & ~0x1F) =3D=3D (address & ~0x1F)) { memory_content *next =3D (*current)->next; - cpu_stl_data(env, a, (*current)->value); + if (TARGET_BIG_ENDIAN) { + cpu_stl_be_data(env, a, (*current)->value); + } else { + cpu_stl_le_data(env, a, (*current)->value); + } =20 if (next =3D=3D NULL) { --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143630; cv=none; d=zohomail.com; s=zohoarc; b=BMAbsGrtBBUx540OeAk1at+HLJavR87UuSW8HoKvDOq8NkR6CA0bks5eXte1jSWw0FOrflv0gEbZldQsiawnJJ40OwlfuojBkNqQ303odzgUs59kjRGn2PzAVz40R3z70lcyGZkzJrKJKVNN61nqbYhBOGWL4BZYqzksNMSuPsc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143630; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HDoRFtIf4DtlaKu8FqeCDNwKdTIWIuyOpEl6R55IExI=; b=ZuGEZMbN+RqCNYzKSy6wmV1p4rrMzjugIrc1GJ+7lrUDaaFNJWksdvjkrkIYCje3kq/ewVYumhdauE+MwUM9O1orYy+guNh6Xu+OC8Ud1IhZeNjGbO2uz2+1Fut+ePErb7mxD+oQWKpaur6+rD0Xs7TLGhuOkR9R/82J+w38Img= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764143626588961.0826750757924; Tue, 25 Nov 2025 23:53:46 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOAKV-0004Gq-2F; Wed, 26 Nov 2025 02:52:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOAJH-0001X0-Sa for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:33 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOAJC-0003YF-1y for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:31 -0500 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-477619f8ae5so36035735e9.3 for ; Tue, 25 Nov 2025 23:51:24 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Per the "MIPS=C2=AE SIMD Architecture" (MD00926 rev 1.03): 3.1 Registers Layout MSA vectors are stored in memory starting from the 0th element at the lowest byte address. The byte order of each element follows the big- or little-endian convention of the system configuration. Use the explicit big-endian variants of cpu_ld/st_data*(). Running files in tests/tcg/mips/user/ase/msa shows: NLOC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms | NLOC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.22 ms | NLOC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLOC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLZC.B | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | NLZC.H | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | NLZC.W | PASS: 80 | FAIL: 0 | elapsed time: 0.21 ms | NLZC.D | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCNT.B | PASS: 80 | FAIL: 0 | elapsed time: 0.17 ms | PCNT.H | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | PCNT.W | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCNT.D | PASS: 80 | FAIL: 0 | elapsed time: 0.19 ms | BINSL.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSL.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | BINSR.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BINSR.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | BINSR.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | BINSR.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | BMNZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | BMZ.V | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | BSEL.V | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms | BCLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BCLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | BNEG.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BNEG.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | BNEG.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BNEG.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | BSET.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | BSET.D | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MADD_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.60 ms | MADD_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.83 ms | MADDR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | MADDR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUB_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUB_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUBR_Q.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBR_Q.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MUL_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MUL_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULR_Q.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULR_Q.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | FMAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms | FMAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMAX.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | FMAX.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.36 ms | FMIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | FMIN.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | FMIN.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADD_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADD_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ADDS_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | ADDS_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | ADDS_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.80 ms | ADDS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ADDV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ADDV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HADD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | HADD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | AVE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | AVER_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | AVER_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AVER_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CEQ.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CEQ.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CEQ.W | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | CEQ.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLE_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLE_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLE_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | CLT_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLT_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | CLT_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | CLT_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | CLT_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | DIV_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | DIV_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | DIV_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.39 ms | DIV_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | DIV_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DIV_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | DOTP_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DOTP_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | DOTP_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | DPADD_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | DPADD_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | DPADD_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPADD_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_S.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_S.W | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | DPSUB_S.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | DPSUB_U.H | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | DPSUB_U.W | PASS: 112 | FAIL: 0 | elapsed time: 0.59 ms | DPSUB_U.D | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MAX_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MAX_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MAX_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | MAX_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | MAX_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MAX_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MAX_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MIN_A.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_A.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.33 ms | MIN_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MIN_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MIN_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MOD_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MOD_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | MOD_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms | MOD_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | MOD_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MOD_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MADDV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MADDV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.63 ms | MADDV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MADDV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | MSUBV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | MSUBV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | MSUBV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.65 ms | MULV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MULV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | MULV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.44 ms | ASUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ASUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ASUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | HSUB_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | HSUB_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | HSUB_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBS_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBS_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | SUBS_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBS_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | SUBS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SUBSUS_U.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUS_U.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SUBSUU_S.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBSUU_S.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SUBV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVEV.B | PASS: 80 | FAIL: 0 | elapsed time: 0.35 ms | ILVEV.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | ILVEV.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | ILVEV.D | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | ILVOD.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVOD.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ILVL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | ILVR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | ILVR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | AND.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | NOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | OR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | XOR.V | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | MOVE.V | PASS: 80 | FAIL: 0 | elapsed time: 0.18 ms | PCKEV.B | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | PCKEV.H | PASS: 112 | FAIL: 0 | elapsed time: 0.56 ms | PCKEV.W | PASS: 112 | FAIL: 0 | elapsed time: 0.68 ms | PCKEV.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | PCKOD.B | PASS: 112 | FAIL: 0 | elapsed time: 0.61 ms | PCKOD.H | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | PCKOD.W | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | PCKOD.D | PASS: 112 | FAIL: 0 | elapsed time: 0.58 ms | VSHF.B | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | VSHF.H | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | VSHF.W | PASS: 112 | FAIL: 0 | elapsed time: 0.62 ms | VSHF.D | PASS: 112 | FAIL: 0 | elapsed time: 0.57 ms | SLL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.34 ms | SLL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SLL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SLL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.38 ms | SRA.B | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRA.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SRA.W | PASS: 80 | FAIL: 0 | elapsed time: 0.37 ms | SRA.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRAR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRAR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRAR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRAR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.H | PASS: 80 | FAIL: 0 | elapsed time: 0.32 ms | SRL.W | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRL.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRLR.B | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | SRLR.H | PASS: 80 | FAIL: 0 | elapsed time: 0.29 ms | SRLR.W | PASS: 80 | FAIL: 0 | elapsed time: 0.31 ms | SRLR.D | PASS: 80 | FAIL: 0 | elapsed time: 0.30 ms | Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/tcg/msa_helper.c | 51 ++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 20 deletions(-) diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index f554b3d10ee..d6ce17abf9a 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8231,8 +8231,8 @@ void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd, uint64_t d0, d1; =20 /* Load 8 bytes at a time. Vector element ordering makes this LE. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); pwd->d[0] =3D d0; pwd->d[1] =3D d1; } @@ -8248,9 +8248,9 @@ void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd, * Load 8 bytes at a time. Use little-endian load, then for * big-endian target, we must then swap the four halfwords. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { d0 =3D bswap16x4(d0); d1 =3D bswap16x4(d1); } @@ -8269,9 +8269,9 @@ void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd, * Load 8 bytes at a time. Use little-endian load, then for * big-endian target, we must then bswap the two words. */ - d0 =3D cpu_ldq_le_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_le_data_ra(env, addr + 8, ra); - if (mips_env_is_bigendian(env)) { + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { d0 =3D bswap32x2(d0); d1 =3D bswap32x2(d1); } @@ -8286,8 +8286,12 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd, uintptr_t ra =3D GETPC(); uint64_t d0, d1; =20 - d0 =3D cpu_ldq_data_ra(env, addr + 0, ra); - d1 =3D cpu_ldq_data_ra(env, addr + 8, ra); + d0 =3D cpu_ldq_be_data_ra(env, addr + 0, ra); + d1 =3D cpu_ldq_be_data_ra(env, addr + 8, ra); + if (!mips_env_is_bigendian(env)) { + d0 =3D bswap64(d0); + d1 =3D bswap64(d1); + } pwd->d[0] =3D d0; pwd->d[1] =3D d1; } @@ -8320,8 +8324,8 @@ void helper_msa_st_b(CPUMIPSState *env, uint32_t wd, ensure_writable_pages(env, addr, mmu_idx, ra); =20 /* Store 8 bytes at a time. Vector element ordering makes this LE. */ - cpu_stq_le_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_le_data_ra(env, addr + 8, pwd->d[1], ra); + cpu_stq_be_data_ra(env, addr + 0, pwd->d[0], ra); + cpu_stq_be_data_ra(env, addr + 8, pwd->d[1], ra); } =20 void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, @@ -8337,12 +8341,12 @@ void helper_msa_st_h(CPUMIPSState *env, uint32_t wd, /* Store 8 bytes at a time. See helper_msa_ld_h. */ d0 =3D pwd->d[0]; d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { + if (!mips_env_is_bigendian(env)) { d0 =3D bswap16x4(d0); d1 =3D bswap16x4(d1); } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, @@ -8358,12 +8362,12 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd, /* Store 8 bytes at a time. See helper_msa_ld_w. */ d0 =3D pwd->d[0]; d1 =3D pwd->d[1]; - if (mips_env_is_bigendian(env)) { + if (!mips_env_is_bigendian(env)) { d0 =3D bswap32x2(d0); d1 =3D bswap32x2(d1); } - cpu_stq_le_data_ra(env, addr + 0, d0, ra); - cpu_stq_le_data_ra(env, addr + 8, d1, ra); + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } =20 void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, @@ -8372,9 +8376,16 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); int mmu_idx =3D mips_env_mmu_index(env); uintptr_t ra =3D GETPC(); + uint64_t d0, d1; =20 ensure_writable_pages(env, addr, mmu_idx, GETPC()); =20 - cpu_stq_data_ra(env, addr + 0, pwd->d[0], ra); - cpu_stq_data_ra(env, addr + 8, pwd->d[1], ra); + d0 =3D pwd->d[0]; + d1 =3D pwd->d[1]; + if (!mips_env_is_bigendian(env)) { + d0 =3D bswap64(d0); + d1 =3D bswap64(d1); + } + cpu_stq_be_data_ra(env, addr + 0, d0, ra); + cpu_stq_be_data_ra(env, addr + 8, d1, ra); } --=20 2.51.0 From nobody Mon Feb 9 14:02:08 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1764143659; cv=none; d=zohomail.com; s=zohoarc; b=cwDjiNwGRReoVSSF0RHJ2IWIbHaCwWxnMxYpZI/7zfUuK0O5njqDxsphoeEtfSLOOgfn9S6uADR8uZ5lFLmshHsiaeWiYaqCHtWzask7M1mZF6/qvbEZRkU/FCp2dNcRIQkK74BqHvE85jwOWwSVfkNZQZzMAMkQQ7c9gkAKtH8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1764143659; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HqbvtytwZhlAGHOU7hmLAcqlvwP/xTJGGdaDHqryDAY=; b=DR2qdHFODEsknKoMBc1oLHEpB6G8fcvkIdsfrbwhHtTtBKPKoerYYUlRllDL2X0uoe8aV7i5Y0SwC9E/fCRfOVxaIZLwTTiGgv03IQQuDJPD0Tj3V/albe7ynRBsV+dqVgfdcKw1WLym/RA0SvdApl/BSrDRtL1fBJ1h7kq+8qk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1764143657720455.3377284171413; Tue, 25 Nov 2025 23:54:17 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vOAKc-0004ik-2V; Wed, 26 Nov 2025 02:52:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vOAJJ-0001XM-Aa for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:33 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1vOAJH-0003Yx-NV for qemu-devel@nongnu.org; Wed, 26 Nov 2025 02:51:33 -0500 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-42b32ff5d10so329955f8f.1 for ; Tue, 25 Nov 2025 23:51:31 -0800 (PST) Received: from localhost.localdomain (88-187-86-199.subs.proxad.net. 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Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- FIXME: Still some PPC/MIPS uses --- include/accel/tcg/cpu-ldst.h | 46 ------------------------------------ 1 file changed, 46 deletions(-) diff --git a/include/accel/tcg/cpu-ldst.h b/include/accel/tcg/cpu-ldst.h index 0de7f5eaa6b..12dd38599a6 100644 --- a/include/accel/tcg/cpu-ldst.h +++ b/include/accel/tcg/cpu-ldst.h @@ -428,52 +428,6 @@ cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint6= 4_t val) cpu_stq_le_data_ra(env, addr, val, 0); } =20 -#if TARGET_BIG_ENDIAN -# define cpu_lduw_data cpu_lduw_be_data -# define cpu_ldsw_data cpu_ldsw_be_data -# define cpu_ldl_data cpu_ldl_be_data -# define cpu_ldq_data cpu_ldq_be_data -# define cpu_lduw_data_ra cpu_lduw_be_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra -# define cpu_ldl_data_ra cpu_ldl_be_data_ra -# define cpu_ldq_data_ra cpu_ldq_be_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra -# define cpu_stw_data cpu_stw_be_data -# define cpu_stl_data cpu_stl_be_data -# define cpu_stq_data cpu_stq_be_data -# define cpu_stw_data_ra cpu_stw_be_data_ra -# define cpu_stl_data_ra cpu_stl_be_data_ra -# define cpu_stq_data_ra cpu_stq_be_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra -#else -# define cpu_lduw_data cpu_lduw_le_data -# define cpu_ldsw_data cpu_ldsw_le_data -# define cpu_ldl_data cpu_ldl_le_data -# define cpu_ldq_data cpu_ldq_le_data -# define cpu_lduw_data_ra cpu_lduw_le_data_ra -# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra -# define cpu_ldl_data_ra cpu_ldl_le_data_ra -# define cpu_ldq_data_ra cpu_ldq_le_data_ra -# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra -# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra -# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra -# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra -# define cpu_stw_data cpu_stw_le_data -# define cpu_stl_data cpu_stl_le_data -# define cpu_stq_data cpu_stq_le_data -# define cpu_stw_data_ra cpu_stw_le_data_ra -# define cpu_stl_data_ra cpu_stl_le_data_ra -# define cpu_stq_data_ra cpu_stq_le_data_ra -# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra -# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra -# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra -#endif - static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr) { CPUState *cs =3D env_cpu(env); --=20 2.51.0