From nobody Tue Feb 10 15:28:38 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763779383021562.8043508276415; Fri, 21 Nov 2025 18:43:03 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vMd7R-00050k-DH; Fri, 21 Nov 2025 21:12:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMcok-0004es-Kh; Fri, 21 Nov 2025 20:53:38 -0500 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMcmi-00062e-0m; Fri, 21 Nov 2025 20:53:34 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id C454416CA5F; Fri, 21 Nov 2025 21:44:24 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 7D778321C9B; Fri, 21 Nov 2025 21:44:33 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Ilya Leoshkevich , =?UTF-8?q?Thomas=20Wei=C3=9Fschuh?= , Heiko Carstens , Thomas Huth , Michael Tokarev Subject: [Stable-10.0.7 36/81] target/s390x: Use address generation for register branch targets Date: Fri, 21 Nov 2025 21:43:35 +0300 Message-ID: <20251121184424.1137669-36-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763779383251018900 From: Ilya Leoshkevich Indirect branches to addresses taken from registers go through address generation, e.g., for BRANCH ON CONDITION Principles of Operation says: In the RR format, the contents of general register R2 are used to generate the branch address QEMU uses r2_nz handler for the respective register operands. Currently it does not zero out extra bits in 24- and 31-bit addressing modes as required by address generation. The very frequently used s390x_tr_init_disas_context() function has a workaround for this, but the code for saving an old PSW during an interrupt does not. Add the missing masking to r2_nz. Enforce PSW validity by replacing the workaround with an assertion. Reported-by: Thomas Wei=C3=9Fschuh Reported-by: Heiko Carstens Link: https://lore.kernel.org/lkml/ab3131a2-c42a-47ff-bf03-e9f68ac053c0@t-8= ch.de/ Cc: qemu-stable@nongnu.org Signed-off-by: Ilya Leoshkevich Tested-by: Thomas Wei=C3=9Fschuh Message-ID: <20251016175954.41153-4-iii@linux.ibm.com> Signed-off-by: Thomas Huth (cherry picked from commit fc976a67ded4232cf0b9ae3c11fe051da01e4456) Signed-off-by: Michael Tokarev diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 00073c5560..6aa1f30d58 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5618,6 +5618,7 @@ static void in2_r2_nz(DisasContext *s, DisasOps *o) int r2 =3D get_field(s, r2); if (r2 !=3D 0) { o->in2 =3D load_reg(r2); + gen_addi_and_wrap_i64(s, o->in2, o->in2, 0); } } #define SPEC_in2_r2_nz 0 @@ -6384,10 +6385,12 @@ static void s390x_tr_init_disas_context(DisasContex= tBase *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); =20 - /* 31-bit mode */ - if (!(dc->base.tb->flags & FLAG_MASK_64)) { - dc->base.pc_first &=3D 0x7fffffff; - dc->base.pc_next =3D dc->base.pc_first; + if (dc->base.tb->flags & FLAG_MASK_32) { + if (!(dc->base.tb->flags & FLAG_MASK_64)) { + assert(!(dc->base.pc_first & ~((1ULL << 31) - 1))); + } + } else { + assert(!(dc->base.pc_first & ~((1ULL << 24) - 1))); } =20 dc->cc_op =3D CC_OP_DYNAMIC; --=20 2.47.3