From nobody Wed Feb 11 00:59:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763781258311844.0628214893391; Fri, 21 Nov 2025 19:14:18 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vMcuR-0000Hs-8z; Fri, 21 Nov 2025 20:59:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMbvP-0006rA-A5; Fri, 21 Nov 2025 19:56:27 -0500 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMbtM-000189-Nx; Fri, 21 Nov 2025 19:56:23 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 6E1FE16CA4C; Fri, 21 Nov 2025 21:44:22 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 2AD52321C88; Fri, 21 Nov 2025 21:44:31 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Peter Maydell , Helge Deller , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Michael Tokarev Subject: [Stable-10.0.7 17/81] target/hppa: Set FPCR exception flag bits for non-trapped exceptions Date: Fri, 21 Nov 2025 21:43:16 +0300 Message-ID: <20251121184424.1137669-17-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763781260571018900 From: Peter Maydell In commit ebd394948de4e8 ("target/hppa: Fix FPE exceptions") when we added the code for setting up the registers correctly on trapping FP exceptions, we accidentally broke the handling of the flag bits for non-trapping exceptions. In update_fr0_op() we incorrectly zero out the flag bits and the C bit, so any fp operation would clear previously set flag bits. We also stopped setting the flag bits when the fp operation raises an exception and the trap is not enabled. Adjust the code so that we set the Flag bits for every exception that happened and where the trap is not enabled. (This is the correct behaviour for the case where an instruction triggers two exceptions, one of which traps and one of which does not; that can only happen for inexact + underflow or inexact + overflow.) Cc: qemu-stable@nongnu.org Fixes: ebd394948de4e8 ("target/hppa: Fix FPE exceptions") Fixes: 6966e0ba1d4a9e ("target/hppa: Fix FPE exceptions") in 10.0.1 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3158 Signed-off-by: Peter Maydell Reviewed-by: Helge Deller Tested-by: Helge Deller Message-ID: <20251017085350.895681-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 (cherry picked from commit 1a8ffd6172f3d9ad8232189adb879a16ec416f89) Signed-off-by: Michael Tokarev diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c index 294ce0a970..9ffcda66b8 100644 --- a/target/hppa/fpu_helper.c +++ b/target/hppa/fpu_helper.c @@ -95,7 +95,8 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t ra) { uint32_t soft_exp =3D get_float_exception_flags(&env->fp_status); uint32_t hard_exp =3D 0; - uint32_t shadow =3D env->fr0_shadow & 0x3ffffff; + uint32_t shadow =3D env->fr0_shadow; + uint32_t to_flag =3D 0; uint32_t fr1 =3D 0; =20 if (likely(soft_exp =3D=3D 0)) { @@ -123,6 +124,10 @@ static void update_fr0_op(CPUHPPAState *env, uintptr_t= ra) fr1 |=3D hard_exp << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIF= T); } } + /* Set the Flag bits for every exception that was not enabled */ + to_flag =3D hard_exp & ~shadow; + shadow |=3D to_flag << (R_FPSR_FLAGS_SHIFT - R_FPSR_ENABLES_SHIFT); + env->fr0_shadow =3D shadow; env->fr[0] =3D (uint64_t)shadow << 32 | fr1; =20 --=20 2.47.3