From nobody Tue Feb 10 11:15:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763777390299730.3049057153551; Fri, 21 Nov 2025 18:09:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vMd03-0004ab-UL; Fri, 21 Nov 2025 21:05:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMcBO-0007L2-9S; Fri, 21 Nov 2025 20:12:58 -0500 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMcBC-0004z3-9U; Fri, 21 Nov 2025 20:12:54 -0500 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id A881B16CA46; Fri, 21 Nov 2025 21:44:21 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 3248D321C82; Fri, 21 Nov 2025 21:44:30 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Daniel Henrique Barboza , Alistair Francis , Michael Tokarev Subject: [Stable-10.0.7 11/81] target/riscv: fix riscv_cpu_sirq_pending() mask Date: Fri, 21 Nov 2025 21:43:10 +0300 Message-ID: <20251121184424.1137669-11-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.3 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763777399278018900 Content-Type: text/plain; charset="utf-8" From: Daniel Henrique Barboza We're filtering out (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) from S-mode pending interrupts without apparent reason. There's no special treatment for these ints as far as the spec goes, and this filtering is causing read_stopi() to miss those VS interrupts [1]. We shouldn't return delegated VS interrupts in S-mode though, so change the current mask with "~env->hideleg". Note that this is the same handling we're doing in riscv_cpu_mirq_pending() and env->mideleg. [1] https://gitlab.com/qemu-project/qemu/-/issues/2820 Closes: https://gitlab.com/qemu-project/qemu/-/issues/2820 Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Message-ID: <20251022124340.493358-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis Cc: qemu-stable@nongnu.org (cherry picked from commit 06e01941ffca3c246a9770f477e43118793fde59) Signed-off-by: Michael Tokarev diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 3233b66e7e..25619c556c 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -539,8 +539,7 @@ int riscv_cpu_mirq_pending(CPURISCVState *env) =20 int riscv_cpu_sirq_pending(CPURISCVState *env) { - uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & - ~(MIP_VSSIP | MIP_VSTIP | MIP_VSEIP); + uint64_t irqs =3D riscv_cpu_all_pending(env) & env->mideleg & ~env->hi= deleg; uint64_t irqs_f =3D env->mvip & env->mvien & ~env->mideleg & env->sie; =20 return riscv_cpu_pending_to_irq(env, IRQ_S_EXT, IPRIO_DEFAULT_S, --=20 2.47.3