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Thu, 20 Nov 2025 21:04:31 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang Subject: [PATCH v2 6/6] target/riscv: Fix pointer masking translation mode check bug Date: Fri, 21 Nov 2025 13:04:13 +0800 Message-ID: <20251121050413.3718427-7-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121050413.3718427-1-frank.chang@sifive.com> References: <20251121050413.3718427-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1763701523052018900 Content-Type: text/plain; charset="utf-8" From: Frank Chang When running with virtualization in VS/VU mode, or when executing the virtual-machine load/store instructions (HLV.* and HSV.*), the type of address that determines which pointer masking rules apply should be checked against vsatp rather than satp. As a result, sign extension also applies to the virtual-machine load/store instructions. Signed-off-by: Frank Chang Reviewed-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 19 +++++++++++++++---- target/riscv/internals.h | 4 +--- target/riscv/tcg/tcg-cpu.c | 4 ++-- 4 files changed, 19 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ba01b9f90a..c98f95179cc 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -845,7 +845,7 @@ static inline uint32_t vext_get_vlmax(uint32_t vlenb, u= int32_t vsew, =20 bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 -bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 958b05aaa32..54ff2881831 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -286,16 +286,27 @@ RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *en= v) #endif } =20 -bool riscv_cpu_virt_mem_enabled(CPURISCVState *env) +bool riscv_cpu_virt_mem_enabled(CPURISCVState *env, bool is_vm_ldst) { #ifndef CONFIG_USER_ONLY int satp_mode =3D 0; - int priv_mode =3D cpu_address_mode(env); + uint64_t satp; + int priv_mode; + bool virt =3D false; + + if (!is_vm_ldst) { + riscv_cpu_eff_priv(env, &priv_mode, &virt); + } else { + priv_mode =3D get_field(env->hstatus, HSTATUS_SPVP); + virt =3D true; + } + + satp =3D virt ? env->vsatp : env->satp; =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { - satp_mode =3D get_field(env->satp, SATP32_MODE); + satp_mode =3D get_field(satp, SATP32_MODE); } else { - satp_mode =3D get_field(env->satp, SATP64_MODE); + satp_mode =3D get_field(satp, SATP64_MODE); } =20 return ((satp_mode !=3D VM_1_10_MBARE) && (priv_mode !=3D PRV_M)); diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b17b661e2a8..38d438fbf93 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -200,9 +200,7 @@ static inline target_ulong adjust_addr_body(CPURISCVSta= te *env, return addr; } =20 - if (!is_virt_addr) { - signext =3D riscv_cpu_virt_mem_enabled(env); - } + signext =3D riscv_cpu_virt_mem_enabled(env, is_virt_addr); pmlen =3D riscv_pm_get_pmlen(pmm); addr =3D addr << pmlen; =20 diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 440626ddfad..2b4bcefa0c9 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -104,7 +104,7 @@ static TCGTBCPUState riscv_get_tb_cpu_state(CPUState *c= s) RISCVCPU *cpu =3D env_archcpu(env); RISCVExtStatus fs, vs; uint32_t flags =3D 0; - bool pm_signext =3D riscv_cpu_virt_mem_enabled(env); + bool pm_signext =3D riscv_cpu_virt_mem_enabled(env, false); =20 if (cpu->cfg.ext_zve32x) { /* @@ -255,7 +255,7 @@ static vaddr riscv_pointer_wrap(CPUState *cs, int mmu_i= dx, return result; } =20 - pm_signext =3D riscv_cpu_virt_mem_enabled(env); + pm_signext =3D riscv_cpu_virt_mem_enabled(env, false); if (pm_signext) { return sextract64(result, 0, 64 - pm_len); } --=20 2.43.0