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Thu, 20 Nov 2025 21:04:29 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang Subject: [PATCH v2 5/6] target/riscv: Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() Date: Fri, 21 Nov 2025 13:04:12 +0800 Message-ID: <20251121050413.3718427-6-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121050413.3718427-1-frank.chang@sifive.com> References: <20251121050413.3718427-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1763701532975018900 Content-Type: text/plain; charset="utf-8" From: Frank Chang Rename riscv_pm_get_virt_pmm() to riscv_pm_get_vm_ldst_pmm() to better reflect its actual usage. This function is used when checking the PMM field for virtual-machine load/store instructions (HLV.* and HSV.*), rather than for VS/VU modes. Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 2 +- target/riscv/cpu_helper.c | 2 +- target/riscv/internals.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ab285d7a6d1..9ba01b9f90a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -847,7 +847,7 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu); =20 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); -RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); +RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env); uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); =20 RISCVException riscv_csrr(CPURISCVState *env, int csrno, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index bf747834dcc..958b05aaa32 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -258,7 +258,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) #endif } =20 -RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env) +RISCVPmPmm riscv_pm_get_vm_ldst_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY int priv_mode; diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 9b3f01144d2..b17b661e2a8 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -190,7 +190,7 @@ static inline target_ulong adjust_addr_body(CPURISCVSta= te *env, =20 /* get pmm field depending on whether addr is */ if (is_virt_addr) { - pmm =3D riscv_pm_get_virt_pmm(env); + pmm =3D riscv_pm_get_vm_ldst_pmm(env); } else { pmm =3D riscv_pm_get_pmm(env); } --=20 2.43.0