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Thu, 20 Nov 2025 21:04:25 -0800 (PST) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs), Frank Chang Subject: [PATCH v2 3/6] target/riscv: Fix pointer masking PMM field selection logic Date: Fri, 21 Nov 2025 13:04:10 +0800 Message-ID: <20251121050413.3718427-4-frank.chang@sifive.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121050413.3718427-1-frank.chang@sifive.com> References: <20251121050413.3718427-1-frank.chang@sifive.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=frank.chang@sifive.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @sifive.com) X-ZM-MESSAGEID: 1763701518853018900 Content-Type: text/plain; charset="utf-8" From: Frank Chang mstatus.MPV only records the previous virtualization state, and does not affect pointer masking according to the Zjpm specification. This patch rewrites riscv_pm_get_pmm() to follow the architectural definition of Smmpm, Smnpm, and Ssnpm. The resulting PMM selection logic for each mode is summarized below: * mstatus.MXR =3D 1: pointer masking disabled * Smmpm + Smnpm + Ssnpm: M-mode: mseccfg.PMM S-mode: menvcfg.PMM U-mode: senvcfg.PMM VS-mode: henvcfg.PMM VU-mode: senvcfg.PMM * Smmpm + Smnpm (RVS implemented): M-mode: mseccfg.PMM S-mode: menvcfg.PMM U/VS/VU: disabled (Ssnpm not present) * Smmpm + Smnpm (RVS not implemented): M-mode: mseccfg.PMM U-mode: menvcfg.PMM S/VS/VU: disabled (no S-mode) * Smmpm only: M-mode: mseccfg.PMM Other existing modes: pointer masking disabled Signed-off-by: Frank Chang Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu_helper.c | 61 ++++++++++++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index fbab8177092..acfc6c10607 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -171,16 +171,49 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *en= v, bool virt) #endif } =20 +/* + * Returns the effective PMM field. + * + * @env: CPURISCVState + * + * The PMM field selection logic for each effective privilege mode + * is as follows: + * + * - mstatus.MXR =3D 1: disabled + * + * - Smmpm + Smnpm + Ssnpm: + * M-mode: mseccfg.PMM + * S-mode: menvcfg.PMM + * U-mode: senvcfg.PMM + * VS-mode: henvcfg.PMM + * VU-mode: senvcfg.PMM + * + * - Smmpm + Smnpm (RVS implemented): + * M-mode: mseccfg.PMM + * S-mode: menvcfg.PMM + * U/VS/VU: disabled (Ssnpm not present) + * + * - Smmpm + Smnpm (RVS not implemented): + * M-mode: mseccfg.PMM + * U-mode: menvcfg.PMM + * S/VS/VU: disabled (no S-mode) + * + * - Smmpm only: + * M-mode: mseccfg.PMM + * Other existing modes: disabled + */ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) { #ifndef CONFIG_USER_ONLY - int priv_mode =3D cpu_address_mode(env); + int priv_mode; + bool virt; =20 - if (get_field(env->mstatus, MSTATUS_MPRV) && - get_field(env->mstatus, MSTATUS_MXR)) { + if (get_field(env->mstatus, MSTATUS_MXR)) { return PMM_FIELD_DISABLED; } =20 + riscv_cpu_eff_priv(env, &priv_mode, &virt); + /* Get current PMM field */ switch (priv_mode) { case PRV_M: @@ -189,22 +222,30 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env) } break; case PRV_S: - if (riscv_cpu_cfg(env)->ext_smnpm) { - if (get_field(env->mstatus, MSTATUS_MPV)) { - return get_field(env->henvcfg, HENVCFG_PMM); - } else { + if (!virt) { + if (riscv_cpu_cfg(env)->ext_smnpm) { return get_field(env->menvcfg, MENVCFG_PMM); } + } else { + if (riscv_cpu_cfg(env)->ext_ssnpm) { + return get_field(env->henvcfg, HENVCFG_PMM); + } } break; case PRV_U: - if (riscv_has_ext(env, RVS)) { + if (!virt) { if (riscv_cpu_cfg(env)->ext_ssnpm) { return get_field(env->senvcfg, SENVCFG_PMM); } - } else { + if (riscv_cpu_cfg(env)->ext_smnpm) { - return get_field(env->menvcfg, MENVCFG_PMM); + if (!riscv_has_ext(env, RVS)) { + return get_field(env->menvcfg, MENVCFG_PMM); + } + } + } else { + if (riscv_cpu_cfg(env)->ext_ssnpm) { + return get_field(env->senvcfg, SENVCFG_PMM); } } break; --=20 2.43.0