From nobody Sat Feb 7 07:25:40 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1763701359; cv=none; d=zohomail.com; s=zohoarc; b=KoYVJP5eghy9kiW9s9G0FdFpDFCgSlhU4Yso8A/D1m4yxPjpw3tTPUNIxdGv48TS+y6sZIZO+E6lX/BqOpvTtLnaLLVE+Am6/5xvGSphv2rRyOJKHmQBZSh/hUyfkSPBK6TKnwLiaT3sRLyVCqLPNGgfR3iAt0MezbfZkV8JYww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763701359; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=abdNT8qqXtRxxA9pYwtciOJybzDRVEuUdvw1JE83T8o=; b=Glfl3E35+oqyCi+JV63EwWTaD/oe4TIfdJdFLwxIp0CQ9ZnrBBL7ochIbn6s9/3ZaGRysl60Wgck3TjApnaBCvz8zZKgpNAf6QCeE26pYLCc31x7M6eyC1lFTR1V6FCGkIF3+tv8bR3Sz9+RaC1txzj+EH6brdgBBjv7i5MCVNA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763701359875165.53975367335602; Thu, 20 Nov 2025 21:02:39 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vMJHL-0004Ii-FN; Fri, 21 Nov 2025 00:01:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMJGr-0003z1-Hk; Fri, 21 Nov 2025 00:01:25 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vMJGp-0006BY-S9; Fri, 21 Nov 2025 00:01:21 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 21 Nov 2025 13:01:08 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 21 Nov 2025 13:01:08 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v1 1/1] hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable MSI to support hotplug Date: Fri, 21 Nov 2025 13:01:08 +0800 Message-ID: <20251121050108.3407445-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251121050108.3407445-1-jamin_lin@aspeedtech.com> References: <20251121050108.3407445-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763701363326018900 Content-Type: text/plain; charset="utf-8" This patch updates the ASPEED PCIe Root Port capability layout and interrupt handling to match the hardware-defined capability structure as documented in the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet. The following capability offsets and fields are now aligned with the actual hardware implementation (validated using EVB config-space dumps via 'lspci -s -vvv'): - Added MSI capability at offset 0x50 and enabled 1-vector MSI support - Added PCI Express Capability structure at offset 0x80 - Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0 - Added AER capability at offset 0x100 - Implemented aer_vector() callback and MSI init/uninit hooks - Updated Root Port SSID to 0x1150 to reflect the platform default Enabling MSI is required for proper PCIe Hotplug event signaling. This chan= ge improves correctness and ensures QEMU Root Port behavior matches the behavi= or of ASPEED hardware and downstream kernel expectations. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Nabih Estefan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Nabih Estefan --- hw/pci-host/aspeed_pcie.c | 40 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/hw/pci-host/aspeed_pcie.c b/hw/pci-host/aspeed_pcie.c index f7593444fc..1fc2c61772 100644 --- a/hw/pci-host/aspeed_pcie.c +++ b/hw/pci-host/aspeed_pcie.c @@ -68,6 +68,38 @@ static const TypeInfo aspeed_pcie_root_device_info =3D { * PCIe Root Port */ =20 +#define ASPEED_PCIE_ROOT_PORT_MSI_OFFSET 0x50 +#define ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR 1 +#define ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET 0xC0 +#define ASPEED_PCIE_ROOT_PORT_EXP_OFFSET 0x80 +#define ASPEED_PCIE_ROOT_PORT_AER_OFFSET 0x100 + +static uint8_t aspeed_pcie_root_port_aer_vector(const PCIDevice *d) +{ + return 0; +} + +static int aspeed_pcie_root_port_interrupts_init(PCIDevice *d, Error **err= p) +{ + int rc; + + rc =3D msi_init(d, ASPEED_PCIE_ROOT_PORT_MSI_OFFSET, + ASPEED_PCIE_ROOT_PORT_MSI_NR_VECTOR, + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_64BIT, + PCI_MSI_FLAGS_MASKBIT & PCI_MSI_FLAGS_MASKBIT, + errp); + if (rc < 0) { + assert(rc =3D=3D -ENOTSUP); + } + + return rc; +} + +static void aspeed_pcie_root_port_interrupts_uninit(PCIDevice *d) +{ + msi_uninit(d); +} + static void aspeed_pcie_root_port_class_init(ObjectClass *klass, const void *data) { @@ -80,7 +112,13 @@ static void aspeed_pcie_root_port_class_init(ObjectClas= s *klass, k->device_id =3D 0x1150; dc->user_creatable =3D true; =20 - rpc->aer_offset =3D 0x100; + rpc->aer_vector =3D aspeed_pcie_root_port_aer_vector; + rpc->interrupts_init =3D aspeed_pcie_root_port_interrupts_init; + rpc->interrupts_uninit =3D aspeed_pcie_root_port_interrupts_uninit; + rpc->exp_offset =3D ASPEED_PCIE_ROOT_PORT_EXP_OFFSET; + rpc->aer_offset =3D ASPEED_PCIE_ROOT_PORT_AER_OFFSET; + rpc->ssvid_offset =3D ASPEED_PCIE_ROOT_PORT_SSVID_OFFSET; + rpc->ssid =3D 0x1150; } =20 static const TypeInfo aspeed_pcie_root_port_info =3D { --=20 2.43.0