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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(7416014)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2025 13:24:48.8229 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fb39021b-9938-4668-097f-08de28382e10 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000971E7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF2EB7CF87B Received-SPF: permerror client-ip=2a01:111:f403:c112::7; envelope-from=skolothumtho@nvidia.com; helo=CY3PR05CU001.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @Nvidia.com) X-ZM-MESSAGEID: 1763645123407018900 Accelerated SMMUv3 instances rely on the physical SMMUv3 for nested translation (Guest Stage-1, Host Stage-2). In this mode the guest=E2=80=99s Stage-1 tables are programmed directly into hardware, and QEMU should not attempt to walk them for translation since doing so is not reliably safe. For vfio-pci endpoints behind such a vSMMU, the only translation QEMU is responsible for is the MSI doorbell used during KVM MSI setup. Add a device property to carry the MSI doorbell GPA from the virt machine, and expose it through a new get_msi_direct_gpa PCIIOMMUOp. kvm_arch_fixup_msi_route() can then use this GPA directly instead of attempting a software walk of guest translation tables. This enables correct MSI routing with accelerated SMMUv3 while avoiding unsafe accesses to page tables. For meaningful use of vfio-pci devices with accelerated SMMUv3, both KVM and a kernel irqchip are required. Enforce this requirement when accel=3Don is selected. Signed-off-by: Shameer Kolothum Reviewed-by: Nicolin Chen --- hw/arm/smmuv3-accel.c | 10 ++++++++++ hw/arm/smmuv3.c | 2 ++ hw/arm/virt.c | 22 ++++++++++++++++++++++ include/hw/arm/smmuv3.h | 1 + 4 files changed, 35 insertions(+) diff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c index 65b577f49a..8f7c0cda05 100644 --- a/hw/arm/smmuv3-accel.c +++ b/hw/arm/smmuv3-accel.c @@ -392,6 +392,15 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bu= s, void *opaque, } } =20 +static uint64_t smmuv3_accel_get_msi_gpa(PCIBus *bus, void *opaque, int de= vfn) +{ + SMMUState *bs =3D opaque; + SMMUv3State *s =3D ARM_SMMUV3(bs); + + g_assert(s->msi_gpa); + return s->msi_gpa; +} + /* * Only allow PCIe bridges, pxb-pcie roots, and GPEX roots so vfio-pci * endpoints can sit downstream. Accelerated SMMUv3 requires a vfio-pci @@ -496,6 +505,7 @@ static const PCIIOMMUOps smmuv3_accel_ops =3D { .get_viommu_flags =3D smmuv3_accel_get_viommu_flags, .set_iommu_device =3D smmuv3_accel_set_iommu_device, .unset_iommu_device =3D smmuv3_accel_unset_iommu_device, + .get_msi_direct_gpa =3D smmuv3_accel_get_msi_gpa, }; =20 /* Based on SMUUv3 GPBA.ABORT configuration, attach a corresponding HWPT */ diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 42c60b1ec8..f02e3ee46c 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1998,6 +1998,8 @@ static const Property smmuv3_properties[] =3D { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), + /* GPA of MSI doorbell, for SMMUv3 accel use. */ + DEFINE_PROP_UINT64("msi-gpa", SMMUv3State, msi_gpa, 0), }; =20 static void smmuv3_instance_init(Object *obj) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 25fb2bab56..ea3231543a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -3052,6 +3052,14 @@ static void virt_machine_device_pre_plug_cb(HotplugH= andler *hotplug_dev, /* The new SMMUv3 device is specific to the PCI bus */ object_property_set_bool(OBJECT(dev), "smmu_per_bus", true, NU= LL); } + if (object_property_find(OBJECT(dev), "accel") && + object_property_get_bool(OBJECT(dev), "accel", &error_abort)) { + if (!kvm_enabled() || !kvm_irqchip_in_kernel()) { + error_setg(errp, "SMMUv3 accel=3Don requires KVM with " + "kernel-irqchip=3Don support"); + return; + } + } } } =20 @@ -3088,6 +3096,20 @@ static void virt_machine_device_plug_cb(HotplugHandl= er *hotplug_dev, } =20 create_smmuv3_dev_dtb(vms, dev, bus); + if (object_property_find(OBJECT(dev), "accel") && + object_property_get_bool(OBJECT(dev), "accel", &error_abor= t)) { + hwaddr db_start; + + if (vms->msi_controller =3D=3D VIRT_MSI_CTRL_ITS) { + /* GITS_TRANSLATER page + offset */ + db_start =3D base_memmap[VIRT_GIC_ITS].base + 0x10000 = + 0x40; + } else { + /* MSI_SETSPI_NS page + offset */ + db_start =3D base_memmap[VIRT_GIC_V2M].base + 0x40; + } + object_property_set_uint(OBJECT(dev), "msi-gpa", db_start, + &error_abort); + } } } =20 diff --git a/include/hw/arm/smmuv3.h b/include/hw/arm/smmuv3.h index e54ece2d38..5616a8a2be 100644 --- a/include/hw/arm/smmuv3.h +++ b/include/hw/arm/smmuv3.h @@ -67,6 +67,7 @@ struct SMMUv3State { /* SMMU has HW accelerator support for nested S1 + s2 */ bool accel; struct SMMUv3AccelState *s_accel; + uint64_t msi_gpa; }; =20 typedef enum { --=20 2.43.0