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a="65572540" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572540" X-CSE-ConnectionGUID: s1smdbIQRnmHh0L//EBfMw== X-CSE-MsgGUID: DTjhZafxT2OVzoeKuIGkHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296115" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Date: Thu, 20 Nov 2025 15:10:23 +0800 Message-Id: <20251120071030.961230-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621387496018900 Content-Type: text/plain; charset="utf-8" AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit introduced on Intel Diamond Rapids, which enumerates the support for EVEX VPDP* instructions for INT8/INT16 [*]. Although Intel AVX10.2 has already included new VPDP* INT8/INT16 VNNI instructions, a bit - AVX10_VNNI_INT - is still be separated. Relevant new instructions can be checked by either CPUID AVX10.2 OR AVX10_VNNI_INT (e.g., VPDPBSSD). Support CPUID 0x24.0x1 subleaf with AVX10_VNNI_INT enumeration for Guest. [*]: Intel Advanced Vector Extensions 10.2 Architecture Specification (rev 5.0). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721 --- target/i386/cpu.c | 29 ++++++++++++++++++++++++++++- target/i386/cpu.h | 4 ++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1985a6b3b835..0a6bb9ec21c5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1038,6 +1038,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_24_0_EBX_FEATURES 0 #define TCG_29_0_EBX_FEATURES 0 #define TCG_1E_1_EAX_FEATURES 0 +#define TCG_24_1_ECX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1385,6 +1386,18 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_29_0_EBX_FEATURES, }, + [FEAT_24_1_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [2] =3D "avx10-vnni-int", + }, + .cpuid =3D { + .eax =3D 0x24, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_ECX, + }, + .tcg_features =3D TCG_24_1_ECX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -2041,6 +2054,11 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, .to =3D { FEAT_29_0_EBX, ~0ull }, }, + + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + .to =3D { FEAT_24_1_ECX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -8457,8 +8475,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D 0; *ecx =3D 0; *edx =3D 0; - if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count = =3D=3D 0) { + + if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + break; + } + if (count =3D=3D 0) { + uint32_t unused; + x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, + &unused, &unused); *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; + } else if (count =3D=3D 1) { + *ecx =3D env->features[FEAT_24_1_ECX]; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index df57b41567eb..970a4d03a560 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -699,6 +699,7 @@ typedef enum FeatureWord { FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ FEAT_1E_1_EAX, /* CPUID[EAX=3D0x1E,ECX=3D1].EAX */ + FEAT_24_1_ECX, /* CPUID[EAX=3D0x24,ECX=3D0].ECX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1100,6 +1101,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); CPUID_24_0_EBX_AVX10_256 | \ CPUID_24_0_EBX_AVX10_512) =20 +/* AVX10_VNNI_INT instruction */ +#define CPUID_24_1_ECX_AVX10_VNNI_INT (1U << 2) + /* * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) * controls, and explicit Flags Suppression (NF) controls for select sets = of --=20 2.34.1