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Thu, 20 Nov 2025 01:48:29 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2025 22:48:19 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 19 Nov 2025 22:48:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763621305; x=1795157305; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=487ITGVr9i8c/gw4YoNyHsP0ApJoxPWCX3AhdoyG/F8=; b=e7MvUt0xXTfVW7iIoYUVh4qLOq+cNOgcKJyuOIOcqQQIoHVn5pBXVx1D gd8C7qiKM0Z2BAKC2Tx/MnpC/s+wyMlAjv6UMjgdALC8gYkxnNlLjLhvY bGtTNXrRElOnT2FChGRyW20rxu10QnGQcUynQzefg75iO6dUvkjPXnbvY CQsefVp2p/H4cfv/Qpij6ue+fZXF1G1lApfRfLCOvOsSAwWk3X6cipLZg cIrccufYWuQgblfc1KBWPQ1tGnBxhQZNZzZh/5Hk0IHdhWeourFutMFi0 DZbPBSbOJ25t/0j2ZcHDDPRRsn24CbzNUkswrnBi8GyqK7iZ7UkWCS8ks Q==; X-CSE-ConnectionGUID: K2BcrqNXR/2NJfSS19ljHQ== X-CSE-MsgGUID: pH1JjFnpR9OhxzhbISUqzA== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572528" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572528" X-CSE-ConnectionGUID: Q3YeRrSiSoiXgvEYsKThsg== X-CSE-MsgGUID: ZxhSNNFES9iWYFmf+CplDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296105" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 01/10] i386/cpu: Add support for MOVRS in CPUID enumeration Date: Thu, 20 Nov 2025 15:10:21 +0800 Message-Id: <20251120071030.961230-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621401441018900 Content-Type: text/plain; charset="utf-8" MOVRS is a new set of instructions introduced in the Intel platform Diamond Rapids, to load instructions that carry a read-shared hint. Functionally, MOVRS family is equivalent to existing load instructions, but its read-shared hint indicates the source memory location is likely to become read-shared by multiple processors, i.e., read in the future by at least one other processor before it is written (assuming it is ever written in the future). It could optimize the behavior of the caches, especially shared caches, for this data for future reads by multiple processors. Additionally, MOVRS family also includes a software prefetch instruction, PREFETCHRST2, that carries the same read-shared hint. [*] MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]). Add its enumeration support. [*]: Intel Architecture Instruction Set Extensions and Future Features (rev.059). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0c954202cea8..1aae9cba13af 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1266,7 +1266,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { NULL, "fred", "lkgs", "wrmsrns", NULL, "amx-fp16", NULL, "avx-ifma", NULL, NULL, "lam", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "movrs", }, .cpuid =3D { .eax =3D 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d15a89f8c72e..7b50c0c04f6e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1030,6 +1030,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_7_1_EAX_AVX_IFMA (1U << 23) /* Linear Address Masking */ #define CPUID_7_1_EAX_LAM (1U << 26) +/* MOVRS Instructions */ +#define CPUID_7_1_EAX_MOVRS (1U << 31) =20 /* The immediate form of MSR access instructions */ #define CPUID_7_1_ECX_MSR_IMM (1U << 5) --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 20 Nov 2025 01:48:31 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2025 22:48:21 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 19 Nov 2025 22:48:19 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763621307; x=1795157307; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eeDf9LhA0ENb0Ck4QYJNLODepqE4U4YnhvEQeAx5r/4=; b=c/NVLSNahUdXJrHf600+Ffw1VoXNrHzOTXvYZz36vToSjj92bHIwZVxw 1w6HLoTQQ/AiaGVObZX6jejuEMrw8KUeq25TXJi3tEXMtv//RmnMxLohs xEXnfdvlJGwQOg5mVOdua/QJ/Hn3ACwduRVTJ18TQQMbwVywObf7GR5/1 t6fGw7ucdVZfP22wbPfuFqJJeW/kU32YYVTB1rYv5vGh0HnXiKLWfKIMl a4/+r21f+fECPKHyXw3eFUKEQEK1HjrZskQSqZq0z/U0fmGyRypKGqKh5 iaoltzkqwyrmtV8tni1qkTsjOCH+aQSFy5nbzxIBsGeTjsVdmPBHO8mcN g==; X-CSE-ConnectionGUID: WM6j47jcTl+7YvQ58jY+/A== X-CSE-MsgGUID: Qx9Z/t/yRoGbaIblsy7Zew== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572531" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572531" X-CSE-ConnectionGUID: KKShmVRgRn6cwME4DDP9Kw== X-CSE-MsgGUID: dcf9iL9wRwiLkNuWDh5hdA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296111" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 02/10] i386/cpu: Add CPUID.0x1E.0x1 subleaf for AMX instructions Date: Thu, 20 Nov 2025 15:10:22 +0800 Message-Id: <20251120071030.961230-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621427558018900 Content-Type: text/plain; charset="utf-8" Intel Diamond Rapids adds new AMX instructions to support new formats and memory operations [*]. And it introduces the CPUID subleaf 0x1E.0x1 to centralize the discrete AMX feature bits within EAX. For new feature bits (CPUID 0x1E.0x1.EAX[bits 4,6-8]), it's straightforward to add their enurmeration support. In addition to the new features, CPUID 0x1E.0x1.EAX[bits 0-3] are mirrored positions of existing AMX feature bits distributing across the 0x7 leaves. It's not flexible to make these mirror bits have the same names as existing ones, because QEMU would try to set both original bit and mirror bit which would cause warning if host doesn't support 0x1E.0x1 subleaf. Thus, name these mirror bits with "*-mirror" suffix. [*]: Intel Architecture Instruction Set Extensions and Future Features (rev.059). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 25 +++++++++++++++++++++++++ target/i386/cpu.h | 18 ++++++++++++++++++ 2 files changed, 43 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1aae9cba13af..1985a6b3b835 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1037,6 +1037,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_SGX_12_1_EAX_FEATURES 0 #define TCG_24_0_EBX_FEATURES 0 #define TCG_29_0_EBX_FEATURES 0 +#define TCG_1E_1_EAX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1332,6 +1333,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_7_2_EDX_FEATURES, }, + [FEAT_1E_1_EAX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "amx-int8-mirror", "amx-bf16-mirror", "amx-complex-mirror", "a= mx-fp16-mirror", + "amx-fp8", NULL, "amx-tf32", "amx-avx512", + "amx-movrs", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 0x1e, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_EAX, + }, + .tcg_features =3D TCG_1E_1_EAX_FEATURES, + }, [FEAT_24_0_EBX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -8413,8 +8433,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } =20 if (count =3D=3D 0) { + uint32_t unused; + x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, + &unused, &unused); /* Highest numbered palette subleaf */ *ebx =3D INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + } else if (count =3D=3D 1) { + *eax =3D env->features[FEAT_1E_1_EAX]; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7b50c0c04f6e..df57b41567eb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -698,6 +698,7 @@ typedef enum FeatureWord { FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ + FEAT_1E_1_EAX, /* CPUID[EAX=3D0x1E,ECX=3D1].EAX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1071,6 +1072,23 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) =20 +/* AMX_INT8 instruction (mirror of CPUID_7_0_EDX_AMX_INT8) */ +#define CPUID_1E_1_EAX_AMX_INT8_MIRROR (1U << 0) +/* AMX_BF16 instruction (mirror of CPUID_7_0_EDX_AMX_BF16) */ +#define CPUID_1E_1_EAX_AMX_BF16_MIRROR (1U << 1) +/* AMX_COMPLEX instruction (mirror of CPUID_7_1_EDX_AMX_COMPLEX) */ +#define CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR (1U << 2) +/* AMX_FP16 instruction (mirror of CPUID_7_1_EAX_AMX_FP16) */ +#define CPUID_1E_1_EAX_AMX_FP16_MIRROR (1U << 3) +/* AMX_FP8 instruction */ +#define CPUID_1E_1_EAX_AMX_FP8 (1U << 4) +/* AMX_TF32 instruction */ +#define CPUID_1E_1_EAX_AMX_TF32 (1U << 6) +/* AMX_AVX512 instruction */ +#define CPUID_1E_1_EAX_AMX_AVX512 (1U << 7) +/* AMX_MOVRS instruction */ +#define CPUID_1E_1_EAX_AMX_MOVRS (1U << 8) + /* AVX10 128-bit vector support is present */ #define CPUID_24_0_EBX_AVX10_128 (1U << 16) /* AVX10 256-bit vector support is present */ --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 20 Nov 2025 01:48:31 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2025 22:48:23 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 19 Nov 2025 22:48:21 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763621310; x=1795157310; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RQNhI4yZShgqqS4KZ0kIDffcAHISvB9WS7Z0zPPCb20=; b=VrvLYgcHpoz/rw9JoUT9StRYSRvx8N1XpiAE095j1KRhaCljeauXy0kN fwjOKpqAQI1w0QTzoOVL8uVQRNL8XboICAntzMXT/X1i2iH+rUoacdzMA 3Ua+xGOeN+75dfVlASIgG92ji/Xs+4lXsq3hMCpDP+J8l6//xJi0mD7Ns JEo1ynke5nctyG8znT53ABIHoEowcH3j4WDE1AG+ZtDwimczM+sNulb6R YEcrA4qfto8MW/fynt7ayj29tCEaflLKgVQi1FfM2yqr8EqnTyv7dqxYT K/O78VqICVp1Ch4jQRe/bALPjETWxCTPJfLiitG+rLnNncFZ9Mml0DjbR A==; X-CSE-ConnectionGUID: BL3jgz7CQBGSidbWCAKiuw== X-CSE-MsgGUID: SEKfj5L7TCqwxRZdCg9PqA== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572540" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572540" X-CSE-ConnectionGUID: s1smdbIQRnmHh0L//EBfMw== X-CSE-MsgGUID: DTjhZafxT2OVzoeKuIGkHA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296115" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 03/10] i386/cpu: Add support for AVX10_VNNI_INT in CPUID enumeration Date: Thu, 20 Nov 2025 15:10:23 +0800 Message-Id: <20251120071030.961230-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621387496018900 Content-Type: text/plain; charset="utf-8" AVX10_VNNI_INT (0x24.0x1.ECX[bit 2]) is a discrete feature bit introduced on Intel Diamond Rapids, which enumerates the support for EVEX VPDP* instructions for INT8/INT16 [*]. Although Intel AVX10.2 has already included new VPDP* INT8/INT16 VNNI instructions, a bit - AVX10_VNNI_INT - is still be separated. Relevant new instructions can be checked by either CPUID AVX10.2 OR AVX10_VNNI_INT (e.g., VPDPBSSD). Support CPUID 0x24.0x1 subleaf with AVX10_VNNI_INT enumeration for Guest. [*]: Intel Advanced Vector Extensions 10.2 Architecture Specification (rev 5.0). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721 --- target/i386/cpu.c | 29 ++++++++++++++++++++++++++++- target/i386/cpu.h | 4 ++++ 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 1985a6b3b835..0a6bb9ec21c5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1038,6 +1038,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_24_0_EBX_FEATURES 0 #define TCG_29_0_EBX_FEATURES 0 #define TCG_1E_1_EAX_FEATURES 0 +#define TCG_24_1_ECX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1385,6 +1386,18 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_29_0_EBX_FEATURES, }, + [FEAT_24_1_ECX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + [2] =3D "avx10-vnni-int", + }, + .cpuid =3D { + .eax =3D 0x24, + .needs_ecx =3D true, .ecx =3D 1, + .reg =3D R_ECX, + }, + .tcg_features =3D TCG_24_1_ECX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -2041,6 +2054,11 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, .to =3D { FEAT_29_0_EBX, ~0ull }, }, + + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + .to =3D { FEAT_24_1_ECX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -8457,8 +8475,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, *ebx =3D 0; *ecx =3D 0; *edx =3D 0; - if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && count = =3D=3D 0) { + + if (!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10)) { + break; + } + if (count =3D=3D 0) { + uint32_t unused; + x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, + &unused, &unused); *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; + } else if (count =3D=3D 1) { + *ecx =3D env->features[FEAT_24_1_ECX]; } break; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index df57b41567eb..970a4d03a560 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -699,6 +699,7 @@ typedef enum FeatureWord { FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ FEAT_1E_1_EAX, /* CPUID[EAX=3D0x1E,ECX=3D1].EAX */ + FEAT_24_1_ECX, /* CPUID[EAX=3D0x24,ECX=3D0].ECX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1100,6 +1101,9 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); CPUID_24_0_EBX_AVX10_256 | \ CPUID_24_0_EBX_AVX10_512) =20 +/* AVX10_VNNI_INT instruction */ +#define CPUID_24_1_ECX_AVX10_VNNI_INT (1U << 2) + /* * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) * controls, and explicit Flags Suppression (NF) controls for select sets = of --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763621369; cv=none; d=zohomail.com; s=zohoarc; b=NjuU9JCotDGGc9ZQhtAkOZ1Db8qFGJZOrj2r4apC5uBKVxQCU3NdkFTwq4XziRdTiRt297L20XuiRl+JWWX5VO5QrWuDFidIVa7LiqN25OneY11shyagk5yMCnCGXDu/UmPtjMntxF3hyGcfxbMbASOzY76hjKAP/lLF7gRtnUI= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621371311018900 Content-Type: text/plain; charset="utf-8" Intel AVX10 Version 2 (Intel AVX10.2) includes a suite of new instructions delivering new AI features and performance, accelerated media processing, expanded Web Assembly, and Cryptography support, along with enhancements to existing legacy instructions for completeness and efficiency, and it is enumerated as version 2 in CPUID 0x24.0x0.EBX[bits 0-7] [*]. Considerring "Intel CPUs which support Intel AVX10.2 will include an enumeration for AVX10_VNNI_INT (CPUID.24H.01H:ECX.AVX10_VNNI_INT[2])" [*] and EVEX VPDP* instructions for INT8/INT16 (AVX10_VNNI_INT) are detected by either AVX10.2 OR AVX10_VNNI_INT, AVX10_VNNI_INT is part of AVX10.2, so any Intel AVX10.2 implementation lacking the AVX10_VNNI_INT enumeration should be considered buggy hardware. Therefore, it's necessary to set AVX10_VNNI_INT enumeration for Guest when the user specifies AVX10 version 2. For this, introduce AVX10 models to explicitly define the feature bits included in different AVX10 versions. [*]: Intel Advanced Vector Extensions 10.2 Architecture Specification (rev 5.0). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/856721 --- target/i386/cpu.c | 120 +++++++++++++++++++++++++++++++++++++++++++--- target/i386/cpu.h | 2 + 2 files changed, 115 insertions(+), 7 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0a6bb9ec21c5..f0ed575dce59 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2382,6 +2382,40 @@ x86_cpu_def_get_versions(const X86CPUDefinition *def) return def->versions ?: default_version_list; } =20 +/* CPUID 0x24.0x0 (EAX, EBX, ECX, EDX) and 0x24.0x1 (EAX, EBX, ECX, EDX) */ +#define AVX10_FEATURE_WORDS 8 + +typedef struct AVX10VersionDefinition { + const char *name; + /* AVX10 version */ + uint8_t version; + /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */ + uint8_t max_subleaf; + FeatureMask *features; +} AVX10VersionDefinition; + +static const AVX10VersionDefinition builtin_avx10_defs[] =3D { + { + .name =3D "avx10.1", + .version =3D 1, + .max_subleaf =3D 0, + .features =3D (FeatureMask[]) { + { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, + { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK }, + { /* end of list */ } + } + }, + { + .name =3D "avx10.2", + .version =3D 2, + .max_subleaf =3D 1, + .features =3D (FeatureMask[]) { + { FEAT_24_1_ECX, CPUID_24_1_ECX_AVX10_VNNI_INT }, + { /* end of list */ } + } + }, +}; + static const CPUCaches epyc_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, @@ -7242,6 +7276,65 @@ static void x86_cpuid_set_tsc_freq(Object *obj, Visi= tor *v, const char *name, cpu->env.tsc_khz =3D cpu->env.user_tsc_khz =3D value / 1000; } =20 +static void x86_cpuid_get_avx10_version(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + X86CPU *cpu =3D X86_CPU(obj); + uint8_t value; + + value =3D cpu->env.avx10_version; + visit_type_uint8(v, name, &value, errp); +} + +static bool x86_cpu_apply_avx10_features(X86CPU *cpu, uint8_t version, + Error **errp) +{ + const AVX10VersionDefinition *def; + CPUX86State *env =3D &cpu->env; + + if (!version) { + env->avx10_version =3D 0; + env->avx10_max_subleaf =3D 0; + return true; + } + + for (int i =3D 0; i < ARRAY_SIZE(builtin_avx10_defs); i++) { + FeatureMask *f; + + def =3D &builtin_avx10_defs[i]; + for (f =3D def->features; f && f->mask; f++) { + env->features[f->index] |=3D f->mask; + } + + if (def->version =3D=3D version) { + env->avx10_version =3D version; + env->avx10_max_subleaf =3D def->max_subleaf; + break; + } + } + + if (def->version < version) { + error_setg(errp, "avx10-version can be at most %d", def->version); + return false; + } + return true; +} + +static void x86_cpuid_set_avx10_version(Object *obj, Visitor *v, + const char *name, void *opaque, + Error **errp) +{ + X86CPU *cpu =3D X86_CPU(obj); + uint8_t value; + + if (!visit_type_uint8(v, name, &value, errp)) { + return; + } + + x86_cpu_apply_avx10_features(cpu, value, errp); +} + /* Generic getter for "feature-words" and "filtered-features" properties */ static void x86_cpu_get_feature_words(Object *obj, Visitor *v, const char *name, void *opaque, @@ -7932,8 +8025,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X8= 6CPUModel *model) */ object_property_set_str(OBJECT(cpu), "vendor", def->vendor, &error_abo= rt); =20 - object_property_set_uint(OBJECT(cpu), "avx10-version", def->avx10_vers= ion, - &error_abort); + if (def->avx10_version) { + object_property_set_uint(OBJECT(cpu), "avx10-version", + def->avx10_version, &error_abort); + } =20 x86_cpu_apply_version_props(cpu, model); =20 @@ -8480,9 +8575,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; } if (count =3D=3D 0) { - uint32_t unused; - x86_cpu_get_supported_cpuid(0x1E, 0, eax, &unused, - &unused, &unused); + *eax =3D env->avx10_max_subleaf; *ebx =3D env->features[FEAT_24_0_EBX] | env->avx10_version; } else if (count =3D=3D 1) { *ecx =3D env->features[FEAT_24_1_ECX]; @@ -9164,7 +9257,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->a= vx10_version) { uint32_t eax, ebx, ecx, edx; x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); - env->avx10_version =3D ebx & 0xff; + + if (!object_property_set_uint(OBJECT(cpu), "avx10-version", + ebx & 0xff, errp)) { + return; + } } } =20 @@ -9393,6 +9490,11 @@ static bool x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) warn_report("%s: avx10.%d. Adjust to avx10.%d", prefix, env->avx10_version, version); } + /* + * Discrete feature bits have been checked and filtered based = on + * host support. So it's safe to change version without revert= ing + * other feature bits. + */ env->avx10_version =3D version; have_filtered_features =3D true; } @@ -10229,7 +10331,6 @@ static const Property x86_cpu_properties[] =3D { DEFINE_PROP_UINT32("min-level", X86CPU, env.cpuid_min_level, 0), DEFINE_PROP_UINT32("min-xlevel", X86CPU, env.cpuid_min_xlevel, 0), DEFINE_PROP_UINT32("min-xlevel2", X86CPU, env.cpuid_min_xlevel2, 0), - DEFINE_PROP_UINT8("avx10-version", X86CPU, env.avx10_version, 0), DEFINE_PROP_UINT64("ucode-rev", X86CPU, ucode_rev, 0), DEFINE_PROP_BOOL("full-cpuid-auto-level", X86CPU, full_cpuid_auto_leve= l, true), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor), @@ -10371,6 +10472,11 @@ static void x86_cpu_common_class_init(ObjectClass = *oc, const void *data) x86_cpu_get_unavailable_features, NULL, NULL, NULL); =20 + object_class_property_add(oc, "avx10-version", "uint8", + x86_cpuid_get_avx10_version, + x86_cpuid_set_avx10_version, + NULL, NULL); + #if !defined(CONFIG_USER_ONLY) object_class_property_add(oc, "crash-information", "GuestPanicInformat= ion", x86_cpu_get_crash_info_qom, NULL, NULL, NULL= ); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 970a4d03a560..a0b8a59f6c98 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2185,6 +2185,8 @@ typedef struct CPUArchState { FeatureWordArray features; /* AVX10 version */ uint8_t avx10_version; + /* AVX10 (CPUID 0x24) maximum supported sub-leaf. */ + uint8_t avx10_max_subleaf; /* Features that were explicitly enabled/disabled */ FeatureWordArray user_features; uint32_t cpuid_model[12]; --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763621391; cv=none; d=zohomail.com; s=zohoarc; b=KXAiZsLBEWSp14J0iGuQcXh7Anz+pe8YrI2Oi3VsKZ4LbDO1evQnBT0v348P6IuYC84/6i5crc+dnN0GA5jS+dILWFK+k6UFGB6CXUDg3fGJ8odKybcT5euGTz4yNkJilxXhX4BUkmTdHLOQiLGUqPDqT6d2AXDJ0c8OnChTSuk= ARC-Message-Signature: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621393447018900 Content-Type: text/plain; charset="utf-8" Factor out a helper to get host avx10 version, to reduce duplicate codes. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f0ed575dce59..118ce43e4267 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7757,6 +7757,13 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Err= or **errp) =20 #endif /* !CONFIG_USER_ONLY */ =20 +static uint8_t x86_cpu_get_host_avx10_version(void) +{ + uint32_t eax, ebx, ecx, edx; + x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); + return ebx & 0xff; +} + uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w) { FeatureWordInfo *wi =3D &feature_word_info[w]; @@ -9255,11 +9262,10 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **e= rrp) } =20 if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) && !env->a= vx10_version) { - uint32_t eax, ebx, ecx, edx; - x86_cpu_get_supported_cpuid(0x24, 0, &eax, &ebx, &ecx, &edx); + uint8_t version =3D x86_cpu_get_host_avx10_version(); =20 if (!object_property_set_uint(OBJECT(cpu), "avx10-version", - ebx & 0xff, errp)) { + version, errp)) { return; } } @@ -9481,9 +9487,7 @@ static bool x86_cpu_filter_features(X86CPU *cpu, bool= verbose) have_filtered_features =3D x86_cpu_have_filtered_features(cpu); =20 if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_AVX10) { - x86_cpu_get_supported_cpuid(0x24, 0, - &eax_0, &ebx_0, &ecx_0, &edx_0); - uint8_t version =3D ebx_0 & 0xff; + uint8_t version =3D x86_cpu_get_host_avx10_version(); =20 if (version < env->avx10_version) { if (prefix) { --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763621446; cv=none; d=zohomail.com; s=zohoarc; b=E1wueKp1OqQqcQr6OpVnwPy2+ef5IUQ6no7c4iiOMKov92aPT/oWSNdE8Im2hGFN1xCgiP6Ln6i7/O5lGraFWk/LBssFGMg6uHNYyMBvmvaxurwt4AEC9/775XZu8Y6zx9Sx1hNPoavNpDl4pzgGa6SNC83+A27oFAj24X4aLOo= ARC-Message-Signature: i=1; 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bh=3EMUWkHSCA/tfmKappgbzqr0Ir4rokgyHvMpaedvWFs=; b=JrTI++X8HFePnrzUaoVk7MpwXuamt7/5fELTAe8vHLvEBwMuOzuh+J2K 7L5LDObS7fe7JmlAhJe7gqdVh+XnA72KVSrEFOxxl9d9wmuH7frtmh5pR 2DpdbvmbYgfBIQsZ9MM959QChwAbHKjw3kWKhTZmFnYGaiyL4oc009M8L xKvV48ZV8OG6LPFEiLZe1H2lnNH864vQgyJyIwBZmDY2QaaUua4utbUcB IapwVoBrugyXqDpnOkHQzRSEiDik0zBVg9yPwqtdf9SbbldPKX6Eoevoy UEtxpSnQAiBJneJHUMgLIJTN7nc12d30KGgSR7J6vQGWc95SifWXLX8KT A==; X-CSE-ConnectionGUID: ApjU5gZ9TyG8kv+r9c3VfQ== X-CSE-MsgGUID: 0qJsNSkzQduEcH3rwDux0w== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572553" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572553" X-CSE-ConnectionGUID: Q59W+5vXQommWYSKxiUHnQ== X-CSE-MsgGUID: ToipA4PaTV2jIbPGbBDDjg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296126" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 06/10] i386/cpu: Allow cache to be shared at thread level Date: Thu, 20 Nov 2025 15:10:26 +0800 Message-Id: <20251120071030.961230-7-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621447584018900 Content-Type: text/plain; charset="utf-8" In CPUID 0x4 leaf, it's possible to make the cache privated at thread level when there's no HT within the core. In this case, while cache per thread and cache per core are essentially identical, their topology information differs in CPUID 0x4. Diamond Rapids assigns the L1 i/d cache at the thread level. To allow accurate emulation of DMR cache topology, remove the cache-per-thread restriction in max_thread_ids_for_cache(), which enables CPUID 0x4 to support cache per thread topology. Given that after adding thread-level support, the topology offset information required by max_thread_ids_for_cache() can be sufficiently provided by apicid_offset_by_topo_level(), so it's straightforward to re-implement max_thread_ids_for_cache() based on apicid_offset_by_topo_level() to reduce redundant duplicate codes. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 53 ++++++++++++++--------------------------------- 1 file changed, 15 insertions(+), 38 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 118ce43e4267..c5f1f5d18d07 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -304,33 +304,30 @@ static void encode_cache_cpuid2(X86CPU *cpu, ((t) =3D=3D UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \ 0 /* Invalid value */) =20 -static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, - enum CpuTopologyLevel share_level) +static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, + enum CpuTopologyLevel topo_lev= el) { - uint32_t num_ids =3D 0; - - switch (share_level) { + switch (topo_level) { + case CPU_TOPOLOGY_LEVEL_THREAD: + return 0; case CPU_TOPOLOGY_LEVEL_CORE: - num_ids =3D 1 << apicid_core_offset(topo_info); - break; + return apicid_core_offset(topo_info); case CPU_TOPOLOGY_LEVEL_MODULE: - num_ids =3D 1 << apicid_module_offset(topo_info); - break; + return apicid_module_offset(topo_info); case CPU_TOPOLOGY_LEVEL_DIE: - num_ids =3D 1 << apicid_die_offset(topo_info); - break; + return apicid_die_offset(topo_info); case CPU_TOPOLOGY_LEVEL_SOCKET: - num_ids =3D 1 << apicid_pkg_offset(topo_info); - break; + return apicid_pkg_offset(topo_info); default: - /* - * Currently there is no use case for THREAD, so use - * assert directly to facilitate debugging. - */ g_assert_not_reached(); } + return 0; +} =20 - return num_ids - 1; +static uint32_t max_thread_ids_for_cache(X86CPUTopoInfo *topo_info, + enum CpuTopologyLevel share_level) +{ + return (1 << apicid_offset_by_topo_level(topo_info, share_level)) - 1; } =20 static uint32_t max_core_ids_in_package(X86CPUTopoInfo *topo_info) @@ -398,26 +395,6 @@ static uint32_t num_threads_by_topo_level(X86CPUTopoIn= fo *topo_info, return 0; } =20 -static uint32_t apicid_offset_by_topo_level(X86CPUTopoInfo *topo_info, - enum CpuTopologyLevel topo_lev= el) -{ - switch (topo_level) { - case CPU_TOPOLOGY_LEVEL_THREAD: - return 0; - case CPU_TOPOLOGY_LEVEL_CORE: - return apicid_core_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_MODULE: - return apicid_module_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_DIE: - return apicid_die_offset(topo_info); - case CPU_TOPOLOGY_LEVEL_SOCKET: - return apicid_pkg_offset(topo_info); - default: - g_assert_not_reached(); - } - return 0; -} - static uint32_t cpuid1f_topo_type(enum CpuTopologyLevel topo_level) { switch (topo_level) { --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 20 Nov 2025 01:48:36 -0500 Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Nov 2025 22:48:30 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa007.jf.intel.com with ESMTP; 19 Nov 2025 22:48:29 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763621313; x=1795157313; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=574zbqZFLl0H5Q58F1V7zuPmhB+LkfNx4Ps2RZbvteM=; b=DVwFZPZt4O/ACeje/edf1kSKgPLPqN3GOE+y/CVdq5PA4IIgAwOTFvwE DS0J8FAFMPplYh03gdfo6KMk8S2E6cMDmI2RKGS9EB8+aZZZtWJLhHIXy qv6e7Be6lfJtqJOGeCDx4y88vsT3dzcXsTVOc5slUNE2jnmr8+qva1UHn LeKSdHLKEGcaQC6sXfY/cJEJPhNz1eUUpm2vACTGPMxO1mvZXRSq96g3J qwVlpKgsSaIEvPr890LgKmcr+P6iuTVUeKOrkO1euOA2zrfwDmUhZWbsi 3uzqTUgnE8ZeCLEIrJJJqPoCWkHjQWLtufGhelIAiuP4xVKTwyOPbrktS Q==; X-CSE-ConnectionGUID: mM5FIMXvTgCU9LBI54ZEwg== X-CSE-MsgGUID: gpv9T+QCTnS5blIZH0mnRA== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572556" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572556" X-CSE-ConnectionGUID: YMm1LzpRTfuAUcq2JpCDbA== X-CSE-MsgGUID: 1UYw/PgGSp6RtqBaDb2amg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296130" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 07/10] i386/cpu: Add an option in X86CPUDefinition to control CPUID 0x1f Date: Thu, 20 Nov 2025 15:10:27 +0800 Message-Id: <20251120071030.961230-8-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621369757018901 Content-Type: text/plain; charset="utf-8" Many Intel CPUs enable CPUID 0x1f by default to encode CPU topology information. Add the "cpuid_0x1f" option to X86CPUDefinition to allow named CPU models to configure CPUID 0x1f from the start, thereby forcing 0x1f to be present for guest. With this option, there's no need to explicitly add v1 model to an unversioned CPU model for explicitly enabling the x-force-cpuid-0x1f property. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Note: this patch is also inclued in Zhaoxin's series: https://lore.kernel.org/qemu-devel/20251027102139.270662-2-ewanhai-oc@zhaox= in.com/ --- target/i386/cpu.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c5f1f5d18d07..143b3e9e0c21 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2313,6 +2313,12 @@ typedef struct X86CPUDefinition { int model; int stepping; uint8_t avx10_version; + /* + * Whether to present CPUID 0x1f by default. + * If true, encode CPU topology in 0x1f leaf even if there's no + * extended topology levels. + */ + bool cpuid_0x1f; FeatureWordArray features; const char *model_id; const CPUCaches *const cache_info; @@ -8014,6 +8020,10 @@ static void x86_cpu_load_model(X86CPU *cpu, const X8= 6CPUModel *model) def->avx10_version, &error_abort); } =20 + if (def->cpuid_0x1f) { + object_property_set_bool(OBJECT(cpu), "x-force-cpuid-0x1f", + def->cpuid_0x1f, &error_abort); + } x86_cpu_apply_version_props(cpu, model); =20 /* --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763621445; cv=none; d=zohomail.com; s=zohoarc; b=S4mukQTNTIqxWikpzG/cx/QzWTaKLh7BONY3LaYmrQC5wTFmj5O3V3MC7VjMqXkZMYKIHA2F8vf2OjRBIASJx2sdCS932s/xmZUKj99041lqfrklUL37kd7xT+9yrtaXZIUGIFFHPtQAxsSNnntUqf7s6tWh76MapxW71h8j1Sw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763621445; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=50Bz5YcS0Z1oAREU0/t262rGdfYBDHbT1wTKjEUTskQ=; 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a="65572559" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572559" X-CSE-ConnectionGUID: Gt2GvWXXRcGICMsbXLktxA== X-CSE-MsgGUID: Olm1z26kQ7utTiGDtLUlaA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296134" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 08/10] i386/cpu: Define dependency for VMX_VM_ENTRY_LOAD_IA32_FRED Date: Thu, 20 Nov 2025 15:10:28 +0800 Message-Id: <20251120071030.961230-9-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621447521018900 Content-Type: text/plain; charset="utf-8" VMX_VM_ENTRY_LOAD_IA32_FRED depends on FRED. Define this dependency relationship. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 4 ++++ target/i386/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 143b3e9e0c21..e891883fa72f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2036,6 +2036,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, .to =3D { FEAT_24_1_ECX, ~0ull }, }, + { + .from =3D { FEAT_7_1_EAX, CPUID_7_1_EAX_FRED }, + .to =3D { FEAT_VMX_ENTRY_CTLS, VMX_VM_ENTRY_LOAD_IA32_FRED = }, + }, }; =20 typedef struct X86RegisterInfo32 { diff --git a/target/i386/cpu.h b/target/i386/cpu.h index a0b8a59f6c98..2631bd25981a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1426,6 +1426,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000 #define VMX_VM_ENTRY_LOAD_CET 0x00100000 #define VMX_VM_ENTRY_LOAD_IA32_PKRS 0x00400000 +#define VMX_VM_ENTRY_LOAD_IA32_FRED 0x00800000 =20 /* Supported Hyper-V Enlightenments */ #define HYPERV_FEAT_RELAXED 0 --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="65572562" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572562" X-CSE-ConnectionGUID: dd8C0j4jQgOnJRq+d+nRkw== X-CSE-MsgGUID: 7Dqjx9JKTf6IusWRoDynqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296137" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu Subject: [PATCH 09/10] i386/cpu: Add CPU model for Diamond Rapids Date: Thu, 20 Nov 2025 15:10:29 +0800 Message-Id: <20251120071030.961230-10-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621435598018900 Content-Type: text/plain; charset="utf-8" According to table 1-2 in Intel Architecture Instruction Set Extensions and Future Features (rev 059), Diamond Rapids has the following new features which have already been supported for guest: * SM4 (EVEX) * Intel Advanced Vector Extensions 10 Version 2 (Intel AVX10.2) * MOVRS and the PREFETCHRST2 instruction * AMX-MOVRS, AMX-AVX512, AMX-FP8, AMX-TF32 * Intel Advanced Performance Extensions And FRED - Flexible Return and Event Delivery (FRED) and the LKGS instruction (introduced since Clearwater Forest & Diamond Rapids) - is included in Diamond Rapids CPU model. In addition, the following features are added into Diamond Rapids CPU model: * CET: Control-flow Enforcement Technology (introduced since Sapphire Rapids & Sierra Forest). Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- Reference link: https://cdrdv2.intel.com/v1/dl/getContent/865891 --- target/i386/cpu.c | 192 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 192 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e891883fa72f..e2d728d38d6f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5443,6 +5443,198 @@ static const X86CPUDefinition builtin_x86_defs[] = =3D { { /* end of list */ }, }, }, + { + .name =3D "DiamondRapids", + .level =3D 0x29, + .vendor =3D CPUID_VENDOR_INTEL, + .family =3D 0x13, /* family: 0xf, extended famil: 0x4 */ + .model =3D 0x1, /* model: 0x1, extended model: 0x0 */ + .stepping =3D 0, + .avx10_version =3D 2, /* avx10.2 */ + .cpuid_0x1f =3D true, + /* + * Please keep the ascending order so that we can have a clear vie= w of + * bit position of each feature. + * + * Missing: CPUID_EXT_DTES64, CPUID_EXT_MONITOR, CPUID_EXT_DSCPL, + * CPUID_EXT_VMX, CPUID_EXT_SMX, CPUID_EXT_EST, CPUID_EXT_TM2, + * CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_DCA, CPUID_EXT_OSXSAVE + */ + .features[FEAT_1_ECX] =3D + CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSSE3 | + CPUID_EXT_FMA | CPUID_EXT_CX16 | CPUID_EXT_PCID | CPUID_EXT_SS= E41 | + CPUID_EXT_SSE42 | CPUID_EXT_X2APIC | CPUID_EXT_MOVBE | + CPUID_EXT_POPCNT | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_AE= S | + CPUID_EXT_XSAVE | CPUID_EXT_AVX | CPUID_EXT_F16C | CPUID_EXT_R= DRAND, + /* Missing: CPUID_DTS, CPUID_ACPI, CPUID_HT, CPUID_TM, CPUID_PBE */ + .features[FEAT_1_EDX] =3D + CPUID_FP87 | CPUID_VME | CPUID_DE | CPUID_PSE | CPUID_TSC | + CPUID_MSR | CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | + CPUID_SEP | CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | + CPUID_PAT | CPUID_PSE36 | CPUID_CLFLUSH | CPUID_MMX | CPUID_FX= SR | + CPUID_SSE | CPUID_SSE2 | CPUID_SS, + .features[FEAT_6_EAX] =3D CPUID_6_EAX_ARAT, + /* + * Missing: CPUID_7_0_EBX_SGX, "cqm" Cache QoS Monitoring, + * "rdt_a" Resource Director Technology Allocation, + * CPUID_7_0_EBX_INTEL_PT, + */ + .features[FEAT_7_0_EBX] =3D + CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_TSC_ADJUST | + CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | + CPUID_7_0_EBX_FDP_EXCPTN_ONLY | CPUID_7_0_EBX_SMEP | + CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCI= D | + CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_ZERO_FCS_FDS | + CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ | + CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | + CPUID_7_0_EBX_AVX512IFMA | CPUID_7_0_EBX_CLFLUSHOPT | + CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_AVX512CD | + CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_AVX512BW | + CPUID_7_0_EBX_AVX512VL, + /* + * Missing: CPUID_7_0_ECX_OSPKE, CPUID_7_0_ECX_WAITPKG, TME, ENQCM= D, + * CPUID_7_0_ECX_SGX_LC, CPUID_7_0_ECX_PKS + */ + .features[FEAT_7_0_ECX] =3D + CPUID_7_0_ECX_AVX512_VBMI | CPUID_7_0_ECX_UMIP | + CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_AVX512_VBMI2 | + CPUID_7_0_ECX_CET_SHSTK | CPUID_7_0_ECX_GFNI | CPUID_7_0_ECX_V= AES | + CPUID_7_0_ECX_VPCLMULQDQ | CPUID_7_0_ECX_AVX512VNNI | + CPUID_7_0_ECX_AVX512BITALG | CPUID_7_0_ECX_AVX512_VPOPCNTDQ | + CPUID_7_0_ECX_LA57 | CPUID_7_0_ECX_RDPID | + CPUID_7_0_ECX_BUS_LOCK_DETECT | CPUID_7_0_ECX_CLDEMOTE | + CPUID_7_0_ECX_MOVDIRI | CPUID_7_0_ECX_MOVDIR64B, + /* + * Missing: SGX-KEYS, UINTR, PCONFIG, ARCH LBR, + * CPUID_7_0_EDX_CORE_CAPABILITY + */ + .features[FEAT_7_0_EDX] =3D + CPUID_7_0_EDX_FSRM | CPUID_7_0_EDX_MD_CLEAR | + CPUID_7_0_EDX_SERIALIZE | CPUID_7_0_EDX_TSX_LDTRK | + CPUID_7_0_EDX_CET_IBT | CPUID_7_0_EDX_AMX_BF16 | + CPUID_7_0_EDX_AVX512_FP16 | CPUID_7_0_EDX_AMX_TILE | + CPUID_7_0_EDX_AMX_INT8 | CPUID_7_0_EDX_SPEC_CTRL | + CPUID_7_0_EDX_STIBP | CPUID_7_0_EDX_FLUSH_L1D | + CPUID_7_0_EDX_ARCH_CAPABILITIES | CPUID_7_0_EDX_SPEC_CTRL_SSBD, + /* Missing: CPUID_7_1_EAX_LASS, ArchPerfmonExt (0x23 leaf), MSRLIS= T */ + .features[FEAT_7_1_EAX] =3D + CPUID_7_1_EAX_AVX_VNNI | CPUID_7_1_EAX_AVX512_BF16 | + CPUID_7_1_EAX_CMPCCXADD | CPUID_7_1_EAX_FZRM | + CPUID_7_1_EAX_FSRS | CPUID_7_1_EAX_FSRC | CPUID_7_1_EAX_FRED | + CPUID_7_1_EAX_LKGS | CPUID_7_1_EAX_WRMSRNS | + CPUID_7_1_EAX_AMX_FP16 | CPUID_7_1_EAX_AVX_IFMA | + CPUID_7_1_EAX_LAM | CPUID_7_1_EAX_MOVRS, + /* Missing: CET_SSS */ + .features[FEAT_7_1_EDX] =3D + CPUID_7_1_EDX_AVX_VNNI_INT8 | CPUID_7_1_EDX_AVX_NE_CONVERT | + CPUID_7_1_EDX_AMX_COMPLEX | CPUID_7_1_EDX_PREFETCHITI | + CPUID_7_1_EDX_AVX10 | CPUID_7_1_EDX_APX, + /* Missing: UC-lock disable */ + .features[FEAT_7_2_EDX] =3D + CPUID_7_2_EDX_PSFD | CPUID_7_2_EDX_IPRED_CTRL | + CPUID_7_2_EDX_RRSBA_CTRL | CPUID_7_2_EDX_DDPD_U | + CPUID_7_2_EDX_BHI_CTRL | CPUID_7_2_EDX_MCDT_NO, + .features[FEAT_XSAVE] =3D + CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC | + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES | CPUID_D_1_EAX_XFD, + .features[FEAT_1E_1_EAX] =3D + CPUID_1E_1_EAX_AMX_INT8_MIRROR | CPUID_1E_1_EAX_AMX_BF16_MIRRO= R | + CPUID_1E_1_EAX_AMX_COMPLEX_MIRROR | + CPUID_1E_1_EAX_AMX_FP16_MIRROR | CPUID_1E_1_EAX_AMX_FP8 | + CPUID_1E_1_EAX_AMX_TF32 | CPUID_1E_1_EAX_AMX_AVX512 | + CPUID_1E_1_EAX_AMX_MOVRS, + .features[FEAT_29_0_EBX] =3D CPUID_29_0_EBX_APX_NCI_NDD_NF, + /* + * Though this bit will be set by avx_version=3D2, it's better to + * explicitly enumerate this feature here. + */ + .features[FEAT_24_1_ECX] =3D CPUID_24_1_ECX_AVX10_VNNI_INT, + .features[FEAT_8000_0001_ECX] =3D + CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_3DNOWPREFETCH, + .features[FEAT_8000_0001_EDX] =3D + CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_PDPE1GB | + CPUID_EXT2_RDTSCP | CPUID_EXT2_LM, + .features[FEAT_8000_0008_EBX] =3D CPUID_8000_0008_EBX_WBNOINVD, + /* + * Missing: ARCH_CAP_RRSBA (KVM bit 19), ARCH_CAP_RFDS_CLEAR (KVM = bit + * 28), MCU_CONTROL (bit 9), MISC_PACKAGE_CTLS (bit 10), + * ENERGY_FILTERING_CTL (bit 11), DOITM (bit 12), MCU_ENUMERATION = (bit + * 16), RRSBA (bit 19), XAPIC_DISABLE_STATUS (bit 21), + * OVERCLOCKING_STATUS (bit 23). + */ + .features[FEAT_ARCH_CAPABILITIES] =3D + MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL | + MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO | + MSR_ARCH_CAP_PSCHANGE_MC_NO | MSR_ARCH_CAP_TAA_NO | + MSR_ARCH_CAP_SBDR_SSDP_NO | MSR_ARCH_CAP_FBSDP_NO | + MSR_ARCH_CAP_PSDP_NO | MSR_ARCH_CAP_BHI_NO | + MSR_ARCH_CAP_PBRSB_NO | MSR_ARCH_CAP_GDS_NO | + MSR_ARCH_CAP_RFDS_NO, + .features[FEAT_VMX_BASIC] =3D + MSR_VMX_BASIC_INS_OUTS | MSR_VMX_BASIC_TRUE_CTLS | + MSR_VMX_BASIC_NESTED_EXCEPTION, + .features[FEAT_VMX_ENTRY_CTLS] =3D + VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_IA32E_MODE | + VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_ENTRY_LOAD_IA32_PAT | VMX_VM_ENTRY_LOAD_IA32_EFER | + VMX_VM_ENTRY_LOAD_CET | VMX_VM_ENTRY_LOAD_IA32_FRED, + .features[FEAT_VMX_EPT_VPID_CAPS] =3D + MSR_VMX_EPT_EXECONLY | + MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_PAGE_WALK_LENGTH_= 5 | + MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB | + MSR_VMX_EPT_INVEPT | MSR_VMX_EPT_AD_BITS | + MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CON= TEXT | + MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | + MSR_VMX_EPT_INVVPID_ALL_CONTEXT | + MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS, + .features[FEAT_VMX_EXIT_CTLS] =3D + VMX_VM_EXIT_SAVE_DEBUG_CONTROLS | VMX_VM_EXIT_HOST_ADDR_SPACE_= SIZE, + VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL | + VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_IA32_PAT | + VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER | + VMX_VM_EXIT_LOAD_IA32_EFER | VMX_VM_EXIT_SAVE_VMX_PREEMPTION_T= IMER | + VMX_VM_EXIT_SAVE_CET | VMX_VM_EXIT_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_MISC] =3D + MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_ACTIVITY_HLT | + MSR_VMX_MISC_ACTIVITY_SHUTDOWN | MSR_VMX_MISC_ACTIVITY_WAIT_SI= PI | + MSR_VMX_MISC_VMWRITE_VMEXIT, + .features[FEAT_VMX_PINBASED_CTLS] =3D + VMX_PIN_BASED_EXT_INTR_MASK | VMX_PIN_BASED_NMI_EXITING | + VMX_PIN_BASED_VIRTUAL_NMIS | VMX_PIN_BASED_VMX_PREEMPTION_TIME= R | + VMX_PIN_BASED_POSTED_INTR, + .features[FEAT_VMX_PROCBASED_CTLS] =3D + VMX_CPU_BASED_VIRTUAL_INTR_PENDING | + VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING | + VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING | + VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING | + VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITI= NG | + VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITI= NG | + VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_VIRTUAL_NMI_PENDING | + VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING= | + VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_TRAP_FLAG= | + VMX_CPU_BASED_USE_MSR_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING | + VMX_CPU_BASED_PAUSE_EXITING | + VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS, + .features[FEAT_VMX_SECONDARY_CTLS] =3D + VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES | + VMX_SECONDARY_EXEC_ENABLE_EPT | VMX_SECONDARY_EXEC_DESC | + VMX_SECONDARY_EXEC_RDTSCP | + VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE | + VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_WBINVD_EXI= TING | + VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST | + VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT | + VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY | + VMX_SECONDARY_EXEC_RDRAND_EXITING | + VMX_SECONDARY_EXEC_ENABLE_INVPCID | + VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_V= MCS | + VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_= PML | + VMX_SECONDARY_EXEC_XSAVES | VMX_SECONDARY_EXEC_TSC_SCALING | + VMX_SECONDARY_EXEC_ENABLE_USER_WAIT_PAUSE, + .features[FEAT_VMX_VMFUNC] =3D MSR_VMX_VMFUNC_EPT_SWITCHING, + .xlevel =3D 0x80000008, + .model_id =3D "Intel Xeon Processor (DiamondRapids)", + }, { .name =3D "SierraForest", .level =3D 0x23, --=20 2.34.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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io7hQp3uSXyWrP5RNePaCQ== X-IronPort-AV: E=McAfee;i="6800,10657,11618"; a="65572564" X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="65572564" X-CSE-ConnectionGUID: EdNbSySyQlSlaXWbt20ezA== X-CSE-MsgGUID: 63/I8cepS5OLnv2FAf9njg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,317,1754982000"; d="scan'208";a="191296143" From: Zhao Liu To: Paolo Bonzini , =?UTF-8?q?Daniel=20P=20=2E=20Berrang=C3=A9?= Cc: qemu-devel@nongnu.org, Xudong Hao , Zhao Liu , Yu Chen Subject: [PATCH 10/10] dosc/cpu-models-x86: Add documentation for DiamondRapids Date: Thu, 20 Nov 2025 15:10:30 +0800 Message-Id: <20251120071030.961230-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251120071030.961230-1-zhao1.liu@intel.com> References: <20251120071030.961230-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.17; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763621417619018900 Content-Type: text/plain; charset="utf-8" Current DiamondRapids hasn't supported cache model. Instead, document its special CPU & cache topology to allow user emulate with "-smp" & "-machine smp-cache". Cc: Yu Chen Signed-off-by: Zhao Liu --- docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x8= 6.rst.inc index 6a770ca8351c..c4c8fc67a562 100644 --- a/docs/system/cpu-models-x86.rst.inc +++ b/docs/system/cpu-models-x86.rst.inc @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live mig= ration compatibility is required, use the newest CPU model that is compatible across all desired hosts. =20 +``DiamondRapids`` + Intel Xeon Processor. + + Diamond Rapids product has a topology which differs from previous Xeon + products. It does not support SMT, but instead features a dual core + module (DCM) architecture. It also has core building blocks (CBB - die + level in CPU topology). The cache hierarchy is organized as follows: + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per + CBB. This cache topology can be emulated for DiamondRapids CPU model + using the smp-cache configuration as shown below: + + Example: + + :: + + -machine smp-cache.0.cache=3Dl1d,smp-cache.0.topology=3Dthread= ,\ + smp-cache.1.cache=3Dl1i,smp-cache.1.topology=3Dthread= ,\ + smp-cache.2.cache=3Dl2,smp-cache.2.topology=3Dmodule,\ + smp-cache.3.cache=3Dl3,smp-cache.3.topology=3Ddie\ + ``ClearwaterForest`` Intel Xeon Processor (ClearwaterForest, 2025) =20 --=20 2.34.1