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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482179; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mgVxzz5OS1LoXUR03jmz8qhB1FTWcW/VwHPGDd3+MG0=; b=N5aFEDuAMBvAbdySQw0Aglvow+6SLAONBkC207c3RbfclR5pfgO//4v17SecnmtBpwHDxI 8IXv+K/xQOrj0jJV7y72rdlIkFgAs9bQ68kJ2gqv/z0HNloe4Tjoic/dZHPzemDDnB+W/E CQG4Qlz23LNEfMhyGdnszQzK3v+/7Y0= X-MC-Unique: PAOybZ_TNz6ux7snaZjr4A-1 X-Mimecast-MFC-AGG-ID: PAOybZ_TNz6ux7snaZjr4A_1763482175 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 1/8] target/arm/machine: Improve traces on register mismatch during migration Date: Tue, 18 Nov 2025 17:07:31 +0100 Message-ID: <20251118160920.554809-2-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Currently when the number of KVM registers exposed by the source is larger than the one exposed on the destination, the migration fails with: "failed to load cpu:cpreg_vmstate_array_len" This gives no information about which registers are causing the trouble. This patch rework the target/arm/machine code so that it becomes able to handle an input stream with a larger set of registers than the destination and print useful information about which registers are causing the trouble. The migration outcome is unchanged: - unexpected registers still will fail the migration - missing ones are printed but will not fail the migration, as done today. The input stream can contain MAX_CPREG_VMSTATE_ANOMALIES(10) extra registers compared to what exists on the target. If there are more registers we will still hit the previous "load cpu:cpreg_vmstate_array_len" error. At most, MAX_CPREG_VMSTATE_ANOMALIES missing registers and MAX_CPREG_VMSTATE_ANOMALIES unexpected registers are printed. Example: qemu-system-aarch64: kvm_arm_cpu_post_load Missing register in input stream= : 0 0x6030000000160003 fw feat reg 3 qemu-system-aarch64: kvm_arm_cpu_post_load Unexpected register in input str= eam: 0 0x603000000013c103 op0:3 op1:0 crn:2 crm:0 op2:3 qemu-system-aarch64: kvm_arm_cpu_post_load Unexpected register in input str= eam: 1 0x603000000013c512 op0:3 op1:0 crn:10 crm:2 op2:2 qemu-system-aarch64: kvm_arm_cpu_post_load Unexpected register in input str= eam: 2 0x603000000013c513 op0:3 op1:0 crn:10 crm:2 op2:3 qemu-system-aarch64: error while loading state for instance 0x0 of device '= cpu' qemu-system-aarch64: load of migration failed: Operation not permitted With TCG there no user friendly formatting of the faulting register indexes as with KVM. However the 2 added trace points help to identify the culprint indexes. Signed-off-by: Eric Auger Reviewed-by: Cornelia Huck --- v1 -> v2: - fixed some type in the commit msg --- target/arm/cpu.h | 6 +++++ target/arm/kvm.c | 23 ++++++++++++++++ target/arm/machine.c | 58 ++++++++++++++++++++++++++++++++++++----- target/arm/trace-events | 7 +++++ 4 files changed, 88 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 39f2b2e54d..077b0cce5b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -938,6 +938,12 @@ struct ArchCPU { uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; =20 + #define MAX_CPREG_VMSTATE_ANOMALIES 10 + uint64_t cpreg_vmstate_missing_indexes[MAX_CPREG_VMSTATE_ANOMALIES]; + int32_t cpreg_vmstate_missing_indexes_array_len; + uint64_t cpreg_vmstate_unexpected_indexes[MAX_CPREG_VMSTATE_ANOMALIES]; + int32_t cpreg_vmstate_unexpected_indexes_array_len; + DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; DynamicGDBFeatureInfo dyn_smereg_feature; diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 0d57081e69..58c6075a9e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -1023,6 +1023,29 @@ void kvm_arm_cpu_pre_save(ARMCPU *cpu) =20 bool kvm_arm_cpu_post_load(ARMCPU *cpu) { + int i; + + for (i =3D 0; i < cpu->cpreg_vmstate_missing_indexes_array_len; i++) { + gchar *name; + + name =3D kvm_print_register_name(cpu->cpreg_vmstate_missing_indexe= s[i]); + trace_kvm_arm_cpu_post_load_missing_reg(name); + g_free(name); + } + + for (i =3D 0; i < cpu->cpreg_vmstate_unexpected_indexes_array_len; i++= ) { + gchar *name; + + name =3D kvm_print_register_name(cpu->cpreg_vmstate_unexpected_ind= exes[i]); + error_report("%s Unexpected register in input stream: %i 0x%"PRIx6= 4" %s", + __func__, i, cpu->cpreg_vmstate_unexpected_indexes[i]= , name); + g_free(name); + } + /* Fail the migration if we detect unexpected registers */ + if (cpu->cpreg_vmstate_unexpected_indexes_array_len) { + return false; + } + if (!write_list_to_kvmstate(cpu, KVM_PUT_FULL_STATE)) { return false; } diff --git a/target/arm/machine.c b/target/arm/machine.c index 0befdb0b28..f06a920aba 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -10,6 +10,7 @@ #include "migration/vmstate.h" #include "target/arm/gtimer.h" #include "hw/arm/machines-qom.h" +#include "trace.h" =20 static bool vfp_needed(void *opaque) { @@ -990,7 +991,13 @@ static int cpu_pre_load(void *opaque) { ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; + int arraylen =3D cpu->cpreg_vmstate_array_len + MAX_CPREG_VMSTATE_ANOM= ALIES; =20 + cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, + arraylen); + cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, + arraylen); + cpu->cpreg_vmstate_array_len =3D arraylen; /* * In an inbound migration where on the source FPSCR/FPSR/FPCR are 0, * there will be no fpcr_fpsr subsection so we won't call vfp_set_fpcr= () @@ -1023,7 +1030,7 @@ static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; - int i, v; + int i =3D 0, j =3D 0, k =3D 0, v =3D 0; =20 /* * Handle migration compatibility from old QEMU which didn't @@ -1051,27 +1058,66 @@ static int cpu_post_load(void *opaque, int version_= id) * entries with the right slots in our own values array. */ =20 - for (i =3D 0, v =3D 0; i < cpu->cpreg_array_len - && v < cpu->cpreg_vmstate_array_len; i++) { + trace_cpu_post_load_len(cpu->cpreg_array_len, cpu->cpreg_vmstate_array= _len); + for (; i < cpu->cpreg_array_len && v < cpu->cpreg_vmstate_array_len;) { + trace_cpu_post_load(i, v , cpu->cpreg_indexes[i]); if (cpu->cpreg_vmstate_indexes[v] > cpu->cpreg_indexes[i]) { /* register in our list but not incoming : skip it */ + trace_cpu_post_load_missing(i, cpu->cpreg_indexes[i], v); + if (j < MAX_CPREG_VMSTATE_ANOMALIES) { + cpu->cpreg_vmstate_missing_indexes[j++] =3D cpu->cpreg_ind= exes[i]; + } + i++; continue; } if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { - /* register in their list but not ours: fail migration */ - return -1; + /* register in their list but not ours: those will fail migrat= ion */ + trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_indexes[v= ], i); + if (k < MAX_CPREG_VMSTATE_ANOMALIES) { + cpu->cpreg_vmstate_unexpected_indexes[k++] =3D + cpu->cpreg_vmstate_indexes[v]; + } + v++; + continue; } /* matching register, copy the value over */ cpu->cpreg_values[i] =3D cpu->cpreg_vmstate_values[v]; v++; + i++; } + /* + * if we have reached the end of the incoming array but there are + * still regs in cpreg, continue parsing the regs which are missing + * in the input stream + */ + for ( ; i < cpu->cpreg_array_len; i++) { + if (j < MAX_CPREG_VMSTATE_ANOMALIES) { + trace_cpu_post_load_missing(i, cpu->cpreg_indexes[i], v); + cpu->cpreg_vmstate_missing_indexes[j++] =3D cpu->cpreg_indexes= [i]; + } + } + /* + * if we have reached the end of the cpreg array but there are + * still regs in the input stream, continue parsing the vmstate array + */ + for ( ; v < cpu->cpreg_vmstate_array_len; v++) { + if (k < MAX_CPREG_VMSTATE_ANOMALIES) { + trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_indexes[v= ], i); + cpu->cpreg_vmstate_unexpected_indexes[k++] =3D + cpu->cpreg_vmstate_indexes[v]; + } + } + + cpu->cpreg_vmstate_missing_indexes_array_len =3D j; + cpu->cpreg_vmstate_unexpected_indexes_array_len =3D k; =20 if (kvm_enabled()) { if (!kvm_arm_cpu_post_load(cpu)) { return -1; } } else { - if (!write_list_to_cpustate(cpu)) { + if (cpu->cpreg_vmstate_unexpected_indexes_array_len || + !write_list_to_cpustate(cpu)) { return -1; } } diff --git a/target/arm/trace-events b/target/arm/trace-events index 676d29fe51..0a5ed3e69d 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -13,6 +13,7 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" =20 # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 +kvm_arm_cpu_post_load_missing_reg(char *name) "Missing register in input s= tream: %s" =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 @@ -26,3 +27,9 @@ arm_powerctl_reset_cpu(uint64_t mp_aff) "cpu %" PRIu64 =20 # tcg/psci.c and hvf/hvf.c arm_psci_call(uint64_t x0, uint64_t x1, uint64_t x2, uint64_t x3, uint32_t= cpuid) "PSCI Call x0=3D0x%016"PRIx64" x1=3D0x%016"PRIx64" x2=3D0x%016"PRIx= 64" x3=3D0x%016"PRIx64" cpuid=3D0x%x" + +# machine.c +cpu_post_load_len(int cpreg_array_len, int cpreg_vmstate_array_len) "cpreg= _array_len=3D%d cpreg_vmstate_array_len=3D%d" +cpu_post_load(int i, int v, uint64_t regidx) "i=3D%d v=3D%d regidx=3D0x%"P= RIx64 +cpu_post_load_missing(int i, uint64_t regidx, int v) "missing register in = input stream: i=3D%d index=3D0x%"PRIx64" (v=3D%d)" +cpu_post_load_unexpected(int v, uint64_t regidx, int i) "unexpected regist= er in input stream: v=3D%d index=3D0x%"PRIx64" (i=3D%d)" --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482186; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vCXFBOVAeisHEx3+fOj5JbWs4YJB8n7CVHoFfGsSQp8=; b=AYnkcHx1z+gbLMbQR6dungH7kd2TbQtVKKiSBEmiuqOeH4ePAleD2uX5YtTQMt+FBWRH0N CdWp6/jWXV2rbwrxgYcrqwDzGj0CGZCryOqk9ic02R3zka1x1+NTJT7dig80XzdZXfsIa7 3GGcWpMhboaRADkQfBPvPlpsCvHJj6M= X-MC-Unique: aV09ZANiM9-52Edrkl-8Xg-1 X-Mimecast-MFC-AGG-ID: aV09ZANiM9-52Edrkl-8Xg_1763482180 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 2/8] target/arm/cpu: Allow registers to be hidden Date: Tue, 18 Nov 2025 17:07:32 +0100 Message-ID: <20251118160920.554809-3-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1763482287808153000 More recent kernels sometimes expose new registers in an unconditionnal manner. This situation breaks backward migration as qemu notices there are more registers in the input stream than supported on the destination host. This leads to a "failed to load cpu:cpreg_vmstate_array_len" error. A good example is the introduction of KVM_REG_ARM_VENDOR_HYP_BMAP_2 pseudo FW register in v6.16 by commit C0000e58c74e (=E2=80=9CKVM: arm64: Introduce KVM_REG_ARM_VENDOR_HYP_BMAP_2=E2=80=9D). Trying to do backward migration from a host kernel that features the commit to a destination host that doesn't, fail with above error. Currently QEMU is not using that feature so ignoring this latter is not a problem. An easy way to fix the migration issue is to teach qemu we don't care about that register and we can simply ignore it when syncing its state during migration. This patch introduces an array of such hidden registers. Soon it will be settable through an array property. If hidden, the register is moved out of the array of cpreg which is built in kvm_arm_init_cpreg_list(). That way their state won't be synced. Signed-off-by: Eric Auger --- v1 -> v2: - Move the property in a separate patch - improve the commit msg - change the trace point to just print info in kvm_arm_init_cpreg_list() - improve comment in cpu.h (Connie) --- target/arm/cpu.h | 23 +++++++++++++++++++++++ target/arm/kvm.c | 12 +++++++++++- target/arm/trace-events | 2 ++ 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 077b0cce5b..0a283940be 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1044,6 +1044,18 @@ struct ArchCPU { /* KVM steal time */ OnOffAuto kvm_steal_time; =20 + /* + * Register indexes that must be hidden. Although normally + * supported (defined in TCG description or exposed by KVM) they are + * willingly hidden for migration sake. This may be used to allow + * backward migration to older versions that do implement a specific + * feature. With KVM acceleration the indexes are the ones described + * in linux/Documentation/virt/kvm/api.rst. With TCG, this is the TCG + * sysreg index. + */ + uint64_t *hidden_regs; + uint32_t nr_hidden_regs; + /* Uniprocessor system with MP extensions */ bool mp_is_up; =20 @@ -1184,6 +1196,17 @@ struct ARMCPUClass { ResettablePhases parent_phases; }; =20 +static inline bool +arm_cpu_hidden_reg(ARMCPU *cpu, uint64_t regidx) +{ + for (int i =3D 0; i < cpu->nr_hidden_regs; i++) { + if (cpu->hidden_regs[i] =3D=3D regidx) { + return true; + } + } + return false; +} + /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 58c6075a9e..575a668f49 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -788,7 +788,10 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu) qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); =20 for (i =3D 0, arraylen =3D 0; i < rlp->n; i++) { - if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { + uint64_t regidx =3D rlp->reg[i]; + + if (!kvm_arm_reg_syncs_via_cpreg_list(regidx) || + arm_cpu_hidden_reg(cpu, regidx)) { continue; } switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { @@ -804,6 +807,8 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu) arraylen++; } =20 + trace_kvm_arm_init_cpreg_list_arraylen(arraylen); + cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, @@ -815,9 +820,14 @@ static int kvm_arm_init_cpreg_list(ARMCPU *cpu) =20 for (i =3D 0, arraylen =3D 0; i < rlp->n; i++) { uint64_t regidx =3D rlp->reg[i]; + if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { continue; } + if (arm_cpu_hidden_reg(cpu, regidx)) { + trace_kvm_arm_init_cpreg_list_skip_hidden_reg(rlp->reg[i]); + continue; + } cpu->cpreg_indexes[arraylen] =3D regidx; arraylen++; } diff --git a/target/arm/trace-events b/target/arm/trace-events index 0a5ed3e69d..20f4b4f2cd 100644 --- a/target/arm/trace-events +++ b/target/arm/trace-events @@ -14,6 +14,8 @@ arm_gt_update_irq(int timer, int irqstate) "gt_update_irq= : timer %d irqstate %d" # kvm.c kvm_arm_fixup_msi_route(uint64_t iova, uint64_t gpa) "MSI iova =3D 0x%"PRI= x64" is translated into 0x%"PRIx64 kvm_arm_cpu_post_load_missing_reg(char *name) "Missing register in input s= tream: %s" +kvm_arm_init_cpreg_list_arraylen(uint32_t arraylen) "arraylen=3D%d" +kvm_arm_init_cpreg_list_skip_hidden_reg(uint64_t regidx) "hidden 0x%"PRIx6= 4" is skipped" =20 # cpu.c arm_cpu_reset(uint64_t mp_aff) "cpu %" PRIu64 --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 18 Nov 2025 11:09:58 -0500 Received: from mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-62-fi9U1NvaMeixhNlE16WEEw-1; Tue, 18 Nov 2025 11:09:48 -0500 Received: from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-06.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id AA262180123A; Tue, 18 Nov 2025 16:09:46 +0000 (UTC) Received: from laptop.redhat.com (unknown [10.44.32.16]) by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 29EB119560B0; Tue, 18 Nov 2025 16:09:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=A8cNc/bfB7vtY9DBzhrSE1weO86Qsd8+duLQHCf7npg=; b=h4v9b/chXXMiav+qa69mQjCoIpzQa1O4NznG5SnAy6Lhon2g4yUMApCaYrYmBiG22a4xL1 LS/kBW2CwFnl9BMBjJTYKmvhu7/2pMjyG4aiA039RMjoqSxgzPQzMsgcDJDFP40Hu61RFU M1jIi9XCPz0GlU5HPcEAa+pXKIXuidU= X-MC-Unique: fi9U1NvaMeixhNlE16WEEw-1 X-Mimecast-MFC-AGG-ID: fi9U1NvaMeixhNlE16WEEw_1763482186 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 3/8] target/arm/machine: Allow extra regs in the incoming stream Date: Tue, 18 Nov 2025 17:07:33 +0100 Message-ID: <20251118160920.554809-4-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1763482287816153000 Newer kernels may revoke exposure of KVM regs to userspace. This can happen when one notices that some registers were unconditionnally exposed whether they shall be conditionnally exposed for example. An example of such situation is: TCR2_EL1, PIRE0_EL1, PIR_EL1. Associated kernel commits were: 0fcb4eea5345=C2=A0 KVM: arm64: Hide TCR2_EL1 from userspace when disabled f= or guests a68cddbe47ef=C2=A0 KVM: arm64: Hide S1PIE registers from userspace when dis= abled for guests Those commits were actual fixes but the cons is that is breaks forward migration on some HW. Indeed when migrating from an old kernel that does not feature those commits to a more recent one, destination qemu detects there are more KVM regs in the input migration stream than exposed by the destination host and the migration fails with: "failed to load cpu:cpreg_vmstate_array_len" This patchs adds the capability to define an array of register indexes that may exist in the migration incoming stream but may be not exposed by KVM on the destination. We provision for extra space in cpreg_vmstate_* arrays during the preload phase to allow the state to be saved without overflow, in case the registers only are in the inbound data. On postload we make sure to ignore them when analyzing potential mismatch between registers. The actual cpreg array is never altered meaning those registers are never accessed nor saved. The array will be populated with a dedicated array property. Signed-off-by: Eric Auger --- v1 -> v2: - get rid of the enforced/fake terminology - remove the useless array of fake regs. Only the number of missing regs is needed RFC -> v1: - improve comment in target/arm/cpu.h (Connie) --- target/arm/cpu.h | 22 ++++++++++++++++++++++ target/arm/machine.c | 27 ++++++++++++++++++--------- 2 files changed, 40 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0a283940be..82fc21dcc5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1056,6 +1056,15 @@ struct ArchCPU { uint64_t *hidden_regs; uint32_t nr_hidden_regs; =20 + /* + * Registers that are likely to be part of the migration + * incoming stream but not exposed on destination. If + * their indexes are stored in this array, it is OK to + * ignore those registers in the inbound data. + */ + uint64_t *mig_safe_missing_regs; + uint32_t nr_mig_safe_missing_regs; + /* Uniprocessor system with MP extensions */ bool mp_is_up; =20 @@ -1207,6 +1216,19 @@ arm_cpu_hidden_reg(ARMCPU *cpu, uint64_t regidx) return false; } =20 + +static inline bool +arm_cpu_safe_missing_reg(ARMCPU *cpu, uint64_t regidx) +{ + for (int i =3D 0; i < cpu->nr_mig_safe_missing_regs; i++) { + if (regidx =3D=3D cpu->mig_safe_missing_regs[i]) { + return true; + } + } + return false; +} + + /* Callback functions for the generic timer's timers. */ void arm_gt_ptimer_cb(void *opaque); void arm_gt_vtimer_cb(void *opaque); diff --git a/target/arm/machine.c b/target/arm/machine.c index f06a920aba..f420879134 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -991,7 +991,8 @@ static int cpu_pre_load(void *opaque) { ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; - int arraylen =3D cpu->cpreg_vmstate_array_len + MAX_CPREG_VMSTATE_ANOM= ALIES; + int arraylen =3D cpu->cpreg_vmstate_array_len + + cpu->nr_mig_safe_missing_regs + MAX_CPREG_VMSTATE_ANOMA= LIES; =20 cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, arraylen); @@ -1058,6 +1059,10 @@ static int cpu_post_load(void *opaque, int version_i= d) * entries with the right slots in our own values array. */ =20 + /* + * at this point cpu->cpreg_vmstate_array_len was migrated with the + * actual length saved on source + */ trace_cpu_post_load_len(cpu->cpreg_array_len, cpu->cpreg_vmstate_array= _len); for (; i < cpu->cpreg_array_len && v < cpu->cpreg_vmstate_array_len;) { trace_cpu_post_load(i, v , cpu->cpreg_indexes[i]); @@ -1072,10 +1077,12 @@ static int cpu_post_load(void *opaque, int version_= id) } if (cpu->cpreg_vmstate_indexes[v] < cpu->cpreg_indexes[i]) { /* register in their list but not ours: those will fail migrat= ion */ - trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_indexes[v= ], i); - if (k < MAX_CPREG_VMSTATE_ANOMALIES) { - cpu->cpreg_vmstate_unexpected_indexes[k++] =3D - cpu->cpreg_vmstate_indexes[v]; + if (!arm_cpu_safe_missing_reg(cpu, cpu->cpreg_vmstate_indexes[= v])) { + trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_index= es[v], i); + if (k < MAX_CPREG_VMSTATE_ANOMALIES) { + cpu->cpreg_vmstate_unexpected_indexes[k++] =3D + cpu->cpreg_vmstate_indexes[v]; + } } v++; continue; @@ -1101,10 +1108,12 @@ static int cpu_post_load(void *opaque, int version_= id) * still regs in the input stream, continue parsing the vmstate array */ for ( ; v < cpu->cpreg_vmstate_array_len; v++) { - if (k < MAX_CPREG_VMSTATE_ANOMALIES) { - trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_indexes[v= ], i); - cpu->cpreg_vmstate_unexpected_indexes[k++] =3D - cpu->cpreg_vmstate_indexes[v]; + if (!arm_cpu_safe_missing_reg(cpu, cpu->cpreg_vmstate_indexes[v]))= { + if (k < MAX_CPREG_VMSTATE_ANOMALIES) { + trace_cpu_post_load_unexpected(v, cpu->cpreg_vmstate_index= es[v], i); + cpu->cpreg_vmstate_unexpected_indexes[k++] =3D + cpu->cpreg_vmstate_indexes[v]; + } } } =20 --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5/Uf9keun9lkTCpTNNCatFfIp+NGVe3IvQeSguqm2zc=; b=CoOxdwRM4WrHLREFVgPBKSFYHF2WkCqOAIQW0BH5O+7dRcmZlQxU4POS70Rrex8MOq40T/ P0mHCjBn1P1aHWdNyLrTwO70ROOSKTSnGCJ8wOlqigbMGw3/UqxOfoZ9/9tm9gkNkKl+gI NZURITQelx6EKPvZBzw76o+eUtNQAzE= X-MC-Unique: jM-UYl8-OUux24zBxwqMlA-1 X-Mimecast-MFC-AGG-ID: jM-UYl8-OUux24zBxwqMlA_1763482192 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 4/8] target/arm/helper: Skip hidden registers Date: Tue, 18 Nov 2025 17:07:34 +0100 Message-ID: <20251118160920.554809-5-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" In case a cpreg is hidden, skip it when initialing the cpreg list. Signed-off-by: Eric Auger --- target/arm/helper.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 27ebc6f29b..7e34b4803d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -236,8 +236,11 @@ static void add_cpreg_to_list(gpointer key, gpointer v= alue, gpointer opaque) uint32_t regidx =3D (uintptr_t)key; const ARMCPRegInfo *ri =3D value; =20 + if (arm_cpu_hidden_reg(cpu, regidx)) { + return; + } if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { - cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); + cpu->cpreg_indexes[cpu->cpreg_array_len] =3D kvm_regidx; /* The value array need not be initialized at this point */ cpu->cpreg_array_len++; } @@ -247,6 +250,11 @@ static void count_cpreg(gpointer key, gpointer value, = gpointer opaque) { ARMCPU *cpu =3D opaque; const ARMCPRegInfo *ri =3D value; + uint32_t regidx =3D (uintptr_t)key; + + if (arm_cpu_hidden_reg(cpu, regidx)) { + return; + } =20 if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_ALIAS))) { cpu->cpreg_array_len++; --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1763482311; cv=none; d=zohomail.com; s=zohoarc; b=bZtvYd/5cNaGgFP9TVbUIhHBBSf319YhPabZQRknBZ8E6agqIS8AYPYc7T7twvC8GbEpRFX3tV+5Qvra64P7M362V7fgJ234ACN2OjLliu9JXp3r4gZKMdLYZUtXswbI+1G+fo0kcnnbp92JNWuLdcdD3iF/A/4DkHdlXzyh2hs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763482311; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Tue, 18 Nov 2025 16:09:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482207; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4wxPKyVn84RDzo2oJCOuNEsO22mNJnKBpxKqACiX87M=; b=KTpJOu319BY6sW34v37bJSUM2kIMVf0NoXCl9nb3/DYOZIA6t5kzOelPUpq3tK6dqpVUgL pQpFKdjMJYmnL1QyTQe4bee3mVsctlb6iYAmaMUhmkttgPzk1y+1vQLwEWKqxHk3YqdwXt 6k5P9k/VYvskXJQlhNOBKEAjDlkskmQ= X-MC-Unique: Ca041t6_MS6WY8qBQS6Dow-1 X-Mimecast-MFC-AGG-ID: Ca041t6_MS6WY8qBQS6Dow_1763482197 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 5/8] kvm-all: Add the capability to blacklist some KVM regs Date: Tue, 18 Nov 2025 17:07:35 +0100 Message-ID: <20251118160920.554809-6-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" On ARM we want to be able to blacklist registers that are exposed by KVM. To mitigate some mitigation failures that occur when a new register is exposed and does not exist on the destination, some registers are tagged "hidden" and their state won't be saved. As the state is not saved and they are expected not to be used, we want to enforce they aren't. So let's check this. The new CPUClass hide_reg() callback is optional and will be implemented on ARM in a subsequent patch. Signed-off-by: Eric Auger --- include/hw/core/cpu.h | 2 ++ accel/kvm/kvm-all.c | 12 ++++++++++++ 2 files changed, 14 insertions(+) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9615051774..5390e3e3d1 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -142,6 +142,7 @@ struct SysemuCPUOps; * the caller will not g_free() it. * @disas_set_info: Setup architecture specific components of disassembly = info * @adjust_watchpoint_address: Perform a target-specific adjustment to an + * @hide_reg: Check if a register must be hidden (optional) * address before attempting to match it against watchpoints. * @deprecation_note: If this CPUClass is deprecated, this field provides * related information. @@ -167,6 +168,7 @@ struct CPUClass { int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); + bool (*hide_reg)(CPUState *cpu, uint64_t regidex); =20 const char *gdb_core_xml_file; const char * (*gdb_arch_name)(CPUState *cpu); diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index f9254ae654..d047d49c0f 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -3784,9 +3784,15 @@ bool kvm_device_supported(int vmfd, uint64_t type) =20 int kvm_set_one_reg(CPUState *cs, uint64_t id, void *source) { + CPUClass *cc =3D CPU_GET_CLASS(cs); struct kvm_one_reg reg; int r; =20 + if (cc->hide_reg && cc->hide_reg(cs, id)) { + error_report("%s reg 0x%"PRIx64" is hidden and shall never been ac= cessed", + __func__, id); + g_assert_not_reached(); + } reg.id =3D id; reg.addr =3D (uintptr_t) source; r =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); @@ -3798,9 +3804,15 @@ int kvm_set_one_reg(CPUState *cs, uint64_t id, void = *source) =20 int kvm_get_one_reg(CPUState *cs, uint64_t id, void *target) { + CPUClass *cc =3D CPU_GET_CLASS(cs); struct kvm_one_reg reg; int r; =20 + if (cc->hide_reg && cc->hide_reg(cs, id)) { + error_report("%s reg 0x%"PRIx64" is hidden and shall never been ac= cessed", + __func__, id); + g_assert_not_reached(); + } reg.id =3D id; reg.addr =3D (uintptr_t) target; r =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1763482361; cv=none; d=zohomail.com; s=zohoarc; b=CBbDrXmIbgb4B9KtMWy1ajzvSA5faazGjOojjNVDZG6w80W9F6BM8kQffra+QbFkM4KXfz/vyq+cO5+E+Zq2k32TZsz/no441a60itZjcYXA23yj9Nqb3Ocn6jftKEOIsc9WYz26e36ip7SxfWA2QKVWzzYvo1eGivZkyGutLsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763482361; h=Content-Transfer-Encoding:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To:Cc; 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Tue, 18 Nov 2025 16:09:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482207; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jrhYgBOnGc28O2y4URJbCutKLWk9LAmfiQECGfDqX50=; b=dJm8Q4POxIXVE9Ypx8Q/d549TP7ufzRPhIS6DPeDmv3+JuygGakmjecnNRHv7GuJxzPdLZ K6FF9D0cDmabwOgjHhtJ2QCC/DEqEZzSNCASX3Qf2aAYBO4Q9LXXqYvAJj6cfEu7GJ3Crl o9ayX8+pJnAK4p8s/mW/p14g2bXxPIs= X-MC-Unique: 2YV5ktQjN6iSXsHghbEiwg-1 X-Mimecast-MFC-AGG-ID: 2YV5ktQjN6iSXsHghbEiwg_1763482203 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 6/8] target/arm/cpu: Implement hide_reg callback() Date: Tue, 18 Nov 2025 17:07:36 +0100 Message-ID: <20251118160920.554809-7-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Check if the register is hidden. Signed-off-by: Eric Auger --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 39292fb9bc..066746d76f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2369,6 +2369,11 @@ static const TCGCPUOps arm_tcg_ops =3D { }; #endif /* CONFIG_TCG */ =20 +static inline bool arm_cpu_hide_reg(CPUState *s, uint64_t regidx) +{ + return arm_cpu_hidden_reg(ARM_CPU(s), regidx); +} + static void arm_cpu_class_init(ObjectClass *oc, const void *data) { ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); @@ -2397,6 +2402,7 @@ static void arm_cpu_class_init(ObjectClass *oc, const= void *data) cc->gdb_get_core_xml_file =3D arm_gdb_get_core_xml_file; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D arm_disas_set_info; + cc->hide_reg =3D arm_cpu_hide_reg; =20 #ifdef CONFIG_TCG cc->tcg_ops =3D &arm_tcg_ops; --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1763482214; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oe9X9vrtzuAvfuKIbXQg7zoSn4VcD4HMrEpnSfOuFKg=; b=aaUDFUSkPaVAhVJa0DfZ3Q7rdRyNgqpAWQT5/UpoFnHp+hkqWfWRtxjpa0jsTkc71J1S1q F4nNjJjqxU7FsPLWlcsUZtIETe3gMecfJ9JCzDZ49cOx/A7cgihq6FyggbbYhblTwG6uVL mtz+/HDtU2t0BJOeoxxGYOZ08sn7Ux8= X-MC-Unique: E3JPMRIzOsevxW9EbuKpBA-1 X-Mimecast-MFC-AGG-ID: E3JPMRIzOsevxW9EbuKpBA_1763482208 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 7/8] target/arm/cpu: Expose x-mig-hidden-regs and x-mig-safe-missing-regs properties Date: Tue, 18 Nov 2025 17:07:37 +0100 Message-ID: <20251118160920.554809-8-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Allows to set both array properties along with arm cpus. Their "x-" prefix reminds that those shall be used carefully for distro specific use cases to garantee cross kernel migration. This will allow to define such compat machine props like: static GlobalProperty arm_virt_kernel_compat_10_1[] =3D { /* KVM_REG_ARM_VENDOR_HYP_BMAP_2 */ { TYPE_ARM_CPU, "x-mig-hidden-regs", "0x6030000000160003" }, { TYPE_ARM_CPU, "x-mig-safe-missing-regs", /* TCR_EL1, PIRE0_EL1, PIR_EL1 */ "0x603000000013c103, 0x603000000013c512, 0x603000000013c513" }, } The first one means KVM_REG_ARM_VENDOR_HYP_BMAP_2 shall always been hidden for machine types older than 10.1. The second one means that along with 10.1 machine type we may receive in the incoming migration stream, 3 registers that are unknown on destination. Obvioulsy, using the reg index as defined in linux/Documentation/virt/kvm/api.rst is not user friendly. However those options, prefixed with "x-" are supposed to be used rarely by people who know the details. Signed-off-by: Eric Auger --- target/arm/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 066746d76f..c41774cb4c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2248,6 +2248,11 @@ static const Property arm_cpu_properties[] =3D { DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false= ), DEFINE_PROP_BOOL("backcompat-pauth-default-use-qarma5", ARMCPU, backcompat_pauth_default_use_qarma5, false), + DEFINE_PROP_ARRAY("x-mig-hidden-regs", ARMCPU, + nr_hidden_regs, hidden_regs, qdev_prop_uint64, uint6= 4_t), + DEFINE_PROP_ARRAY("x-mig-safe-missing-regs", ARMCPU, + nr_mig_safe_missing_regs, mig_safe_missing_regs, + qdev_prop_uint64, uint64_t), }; =20 static const gchar *arm_gdb_arch_name(CPUState *cs) --=20 2.51.1 From nobody Thu Nov 20 12:28:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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b=RtApJ5VB4CiRVUq26MYOqpkHyvhQ27BKwwcaCHd2aUADdCB8dbaQlK2TRS3IKMGZmmg2K8 w2WIF6SXGYZgEXKDsfH7NgAFMBb1CkuUsHdU8QbHejnWRCnI6RC1Q/fMOpxwkaUqDXN68g W/Z9rkstKjFKtMtaM8+vbUD8/Y6Yu2Q= X-MC-Unique: ilYYCJvhOja6pwZ3WzFF1g-1 X-Mimecast-MFC-AGG-ID: ilYYCJvhOja6pwZ3WzFF1g_1763482213 From: Eric Auger To: eric.auger.pro@gmail.com, eric.auger@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, peter.maydell@linaro.org, cohuck@redhat.com, maz@kernel.org, oliver.upton@linux.dev, sebott@redhat.com, gshan@redhat.com, ddutile@redhat.com, peterx@redhat.com, philmd@linaro.org, pbonzini@redhat.com Subject: [PATCH v2 8/8] hw/arm/virt: [DO NOT UPSTREAM] Enforce compatibility with older kernels Date: Tue, 18 Nov 2025 17:07:38 +0100 Message-ID: <20251118160920.554809-9-eric.auger@redhat.com> In-Reply-To: <20251118160920.554809-1-eric.auger@redhat.com> References: <20251118160920.554809-1-eric.auger@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.0 on 10.30.177.12 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" This is an example on how to use the new CPU options. This catters to distributions who want machines to be migratable (forward and backward) accross different host kernel versions in case KVM registers exposed to qemu vary accross kernels. This patch is not meant to be upstreamed as it is really kernel dependent. The goal is to illustrate how this would be used. In this example, For 10_1 machines types and older we apply the following host kernel related compats: 1) Make sure the KVM_REG_ARM_VENDOR_HYP_BMAP_2 exposed from v6.15 onwards is ignored/hidden. 2) Make sure TCR_EL1, PIRE0_EL1, PIR_EL1 are always seen by qemu although not exposed by KVM. They were unconditionnally exposed before v6.13 while from v6.13 they are only exposed if supported by the guest. This will allow 10_1 machines types and older machines to migrate forward and backward from old downstream kernels that do not feature those changes to newer kernels (>=3D v6.15). Signed-off-by: Eric Auger --- hw/arm/virt.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 25fb2bab56..fd8cff7a6f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -99,6 +99,23 @@ static GlobalProperty arm_virt_compat[] =3D { }; static const size_t arm_virt_compat_len =3D G_N_ELEMENTS(arm_virt_compat); =20 +/* + * if a 10_1 machine type or older is used: + * 1) make sure TCR_EL1, PIRE0_EL1, PIR_EL1 are enforced, even if they are= not + * exposed by the kernel + * 2) hide KVM_REG_ARM_VENDOR_HYP_BMAP_2 + */ +static GlobalProperty arm_virt_kernel_compat_10_1[] =3D { + /* KVM_REG_ARM_VENDOR_HYP_BMAP_2 */ + { TYPE_ARM_CPU, "x-mig-hidden-regs", "0x6030000000160003" }, + /* TCR_EL1, PIRE0_EL1, PIR_EL1 */ + { TYPE_ARM_CPU, "x-mig-safe-missing-regs", + "0x603000000013c103, 0x603000000013c512, 0x603000000013c513" }, +}; +static const size_t arm_virt_kernel_compat_10_1_len =3D + G_N_ELEMENTS(arm_virt_kernel_compat_10_1); + + /* * This cannot be called from the virt_machine_class_init() because * TYPE_VIRT_MACHINE is abstract and mc->compat_props g_ptr_array_new() @@ -3543,6 +3560,8 @@ static void virt_machine_10_1_options(MachineClass *m= c) virt_machine_10_2_options(mc); mc->smbios_memory_device_size =3D 2047 * TiB; compat_props_add(mc->compat_props, hw_compat_10_1, hw_compat_10_1_len); + compat_props_add(mc->compat_props, + arm_virt_kernel_compat_10_1, arm_virt_kernel_compat_1= 0_1_len); } DEFINE_VIRT_MACHINE(10, 1) =20 --=20 2.51.1