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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH 1/5] i386/cpu: Add APX EGPRs into xsave area Date: Tue, 18 Nov 2025 14:58:13 +0800 Message-Id: <20251118065817.835017-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118065817.835017-1-zhao1.liu@intel.com> References: <20251118065817.835017-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763447820507158500 Content-Type: text/plain; charset="utf-8" From: Zide Chen APX feature bit is in CPUID_7_1_EDX[21], and APX has EGPR component with index 19 in xstate area, EGPR component has 16 64bit regs. Add EGRP component into xstate area. Note, APX re-uses the 128-byte XSAVE area that had been previously allocated by MPX which has been deprecated on Intel processors, so check whether APX and MPX are set at the same for Guest, if this case happens, mask off them both to avoid conflict for xsave area. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/cpu.c | 25 +++++++++++++++++++++++++ target/i386/cpu.h | 17 +++++++++++++++-- 2 files changed, 40 insertions(+), 2 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 84adfaf99dc8..16bc4b18266c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2111,6 +2111,12 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { { FEAT_7_0_EDX, CPUID_7_0_EDX_AMX_TILE }, }, }, + [XSTATE_APX_BIT] =3D { + .size =3D sizeof(XSaveAPX), + .features =3D { + { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, + }, + }, }; =20 uint32_t xsave_area_size(uint64_t mask, bool compacted) @@ -9116,6 +9122,25 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) env->features[FEAT_KVM] =3D 0; } =20 + /* + * Since Intel MPX had been previously deprecated, APX re-purposes the + * 128-byte XSAVE area that had been previously allocated by MPX (state + * component indices 3 and 4, making up a 128-byte area located at an + * offset of 960 bytes into an un-compacted XSAVE buffer), as a single + * state component housing 128-bytes of storage for EGPRs (8-bytes * 16 + * registers). + * + * Check the conflict between MPX and APX before initializing xsave + * components. + */ + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_MPX) && + (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX)) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_MPX, + "this feature is conflict with APX"); + mark_unavailable_features(cpu, FEAT_7_1_EDX, CPUID_7_1_EDX_APX, + "this feature is conflict with MPX"); + } + x86_cpu_enable_xsave_components(cpu); =20 /* CPUID[EAX=3D7,ECX=3D0].EBX always increased level automatically: */ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d8bdf342f98d..bc7e16d6e6c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -604,6 +604,7 @@ typedef enum X86Seg { #define XSTATE_ARCH_LBR_BIT 15 #define XSTATE_XTILE_CFG_BIT 17 #define XSTATE_XTILE_DATA_BIT 18 +#define XSTATE_APX_BIT 19 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -620,6 +621,7 @@ typedef enum X86Seg { #define XSTATE_ARCH_LBR_MASK (1ULL << XSTATE_ARCH_LBR_BIT) #define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) #define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) +#define XSTATE_APX_MASK (1ULL << XSTATE_APX_BIT) =20 #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) =20 @@ -639,7 +641,8 @@ typedef enum X86Seg { XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ XSTATE_ZMM_Hi256_MASK | \ XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK |= \ - XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA= _MASK) + XSTATE_XTILE_CFG_MASK | \ + XSTATE_XTILE_DATA_MASK | XSTATE_APX_MASK) =20 /* CPUID feature bits available in XSS */ #define CPUID_XSTATE_XSS_MASK (XSTATE_ARCH_LBR_MASK | XSTATE_CET_U_MASK = | \ @@ -1042,6 +1045,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *c= pu, FeatureWord w); #define CPUID_7_1_EDX_PREFETCHITI (1U << 14) /* Support for Advanced Vector Extensions 10 */ #define CPUID_7_1_EDX_AVX10 (1U << 19) +/* Support for Advanced Performance Extensions */ +#define CPUID_7_1_EDX_APX (1U << 21) =20 /* Indicate bit 7 of the IA32_SPEC_CTRL MSR is supported */ #define CPUID_7_2_EDX_PSFD (1U << 0) @@ -1684,6 +1689,8 @@ typedef struct { =20 #define ARCH_LBR_NR_ENTRIES 32 =20 +#define EGPR_NUM 16 + /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish * that APIC ID hasn't been set yet */ @@ -1794,6 +1801,11 @@ typedef struct XSaveXTILEDATA { uint8_t xtiledata[8][1024]; } XSaveXTILEDATA; =20 +/* Ext. save area 19: APX state */ +typedef struct XSaveAPX { + uint64_t egprs[EGPR_NUM]; +} XSaveAPX; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1806,6 +1818,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveCETS) !=3D 0x18); QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); +QEMU_BUILD_BUG_ON(sizeof(XSaveAPX) !=3D 0x80); =20 typedef struct ExtSaveArea { uint32_t offset, size; @@ -1820,7 +1833,7 @@ typedef struct ExtSaveArea { const FeatureMask features[2]; } ExtSaveArea; =20 -#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) +#define XSAVE_STATE_AREA_COUNT (XSTATE_APX_BIT + 1) =20 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; =20 --=20 2.34.1 From nobody Thu Nov 20 12:28:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763447861; cv=none; d=zohomail.com; s=zohoarc; b=bLFLTe5lBaHceRE1N9SUIWUnOGgEkjUvJo6zSmtegihvFX6261E4dLlBdBczV9JmHJEqRCIfPjt7T4t3fCGtuzOAHf7z5JAwANQnsxSfOs+HA9sJDdx4RKMOTIHQleVW9ipZmRkvV9RdkDbfTDATluSZwr+fOTAIqWEqvN9eIAI= ARC-Message-Signature: i=1; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH 2/5] i386/cpu: Cache EGPRs in CPUX86State Date: Tue, 18 Nov 2025 14:58:14 +0800 Message-Id: <20251118065817.835017-3-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118065817.835017-1-zhao1.liu@intel.com> References: <20251118065817.835017-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763447863601153000 Content-Type: text/plain; charset="utf-8" From: Zide Chen Cache EGPR[16] in CPUX86State to store APX's EGPR value. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/cpu.h | 1 + target/i386/xsave_helper.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index bc7e16d6e6c1..48d4d7fcbb9c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1969,6 +1969,7 @@ typedef struct CPUArchState { #ifdef TARGET_X86_64 uint8_t xtilecfg[64]; uint8_t xtiledata[8192]; + uint64_t egprs[EGPR_NUM]; #endif =20 /* sysenter registers */ diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index 996e9f3bfef5..2e9265045520 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -140,6 +140,13 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, u= int32_t buflen) =20 memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); } + + e =3D &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset && buflen) { + XSaveAPX *apx =3D buf + e->offset; + + memcpy(apx, &env->egprs, sizeof(env->egprs)); + } #endif } =20 @@ -275,5 +282,12 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void = *buf, uint32_t buflen) =20 memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); } + + e =3D &x86_ext_save_areas[XSTATE_APX_BIT]; + if (e->size && e->offset) { + const XSaveAPX *apx =3D buf + e->offset; + + memcpy(&env->egprs, apx, sizeof(env->egprs)); + } #endif } --=20 2.34.1 From nobody Thu Nov 20 12:28:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763447816; cv=none; d=zohomail.com; s=zohoarc; b=RKVcJpGFRhRifT5X12+gjmPyfYGMQBY/mzFNg8KuLc1MYbHIgF5lDG3EtLeA6r7NbMbmjMFLfuNW7UjLf6XX8QiC4D2NpNeTqzHKSpHidu0tW23rhfk1NMVoT6z1bgakJcqS90U0/dmGaFWuZpNSFxzFH/gBVurOzQMpCWC87p4= ARC-Message-Signature: i=1; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH 3/5] i386/cpu: Add APX migration support Date: Tue, 18 Nov 2025 14:58:15 +0800 Message-Id: <20251118065817.835017-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118065817.835017-1-zhao1.liu@intel.com> References: <20251118065817.835017-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763447818745158500 Content-Type: text/plain; charset="utf-8" From: Zide Chen Add a VMStateDescription to migrate APX EGPRs. Tested-by: Xudong Hao Signed-off-by: Zide Chen Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- target/i386/machine.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/i386/machine.c b/target/i386/machine.c index 265388f1fd36..84faa2f8f8d3 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1744,6 +1744,27 @@ static const VMStateDescription vmstate_cet =3D { }, }; =20 +#ifdef TARGET_X86_64 +static bool apx_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX); +} + +static const VMStateDescription vmstate_apx =3D { + .name =3D "cpu/apx", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D apx_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.egprs, X86CPU, EGPR_NUM), + VMSTATE_END_OF_LIST() + } +}; +#endif + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1895,6 +1916,9 @@ const VMStateDescription vmstate_x86_cpu =3D { &vmstate_triple_fault, &vmstate_pl0_ssp, &vmstate_cet, +#ifdef TARGET_X86_64 + &vmstate_apx, +#endif NULL } }; --=20 2.34.1 From nobody Thu Nov 20 12:28:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763447817; cv=none; d=zohomail.com; s=zohoarc; b=HZkj8e2y3pfYHbNvCD7qgxKnH9t6aWpWJiFeny8+/zM7FLkIWQiRTzltkegau/CWQEFgcXk7cWVfJKlY3tlPuMAaEjazQkzEuB1nq7SkYUJTByyIglO8LkeKxYq95J6OiICpxboVSUIaRbEPqOazdVNoE84ByrfliI6PICL0xRs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1763447817; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7Dc20aQmzRALVzVVI+3kLm3fEU7Eo4QRvvRphQShRko=; b=kj6/KsKZ8t0RTlc0OjbrZqWOUaoOVvoICq/X6zASdHbslThu+2MDj/GnIWfGJh4MbmlJKJ5cMReJ2a8xYjnZBZDenhciN0xRu4g4cxKJZdRPPU3DvMKVuCeG0i6iUSkGKaR2w6vWnE2hrn5AMqX9SVVlXSBPs08CWtFyPyAJMFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763447817022708.2284261666742; Mon, 17 Nov 2025 22:36:57 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vLFKE-0005nH-Oe; Tue, 18 Nov 2025 01:36:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vLFK4-0005kk-UH for qemu-devel@nongnu.org; Tue, 18 Nov 2025 01:36:18 -0500 Received: from mgamail.intel.com ([198.175.65.10]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vLFK0-0007C4-Rt for qemu-devel@nongnu.org; Tue, 18 Nov 2025 01:36:15 -0500 Received: from orviesa010.jf.intel.com ([10.64.159.150]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 17 Nov 2025 22:36:10 -0800 Received: from liuzhao-optiplex-7080.sh.intel.com ([10.239.160.39]) by orviesa010.jf.intel.com with ESMTP; 17 Nov 2025 22:36:07 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1763447773; x=1794983773; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=sn4U0kc9clqQdeDxROZ7oSldH0IdJFL7RRusR6V5UrU=; b=WOuex/egCedfYezvtQeV4yvmnCGiU5uOJNf4UZ7OfN6LT3dLV7ACHYBD OhNICTTIIyrZJywFlUY75SvP3lbAd5A9yUo/c4wRtMyf9yDsgsdyXrvBS +I8bYA+0Dxhca1DCOOiFs0Bl6Jdinj5dL9QVhe+exQJ5dKs0R18Tga1W1 3vp3//58XcjO0MEWmw5iBsYSscdCB640eMyDY4oQ7sy+qlocm6pKPJbTD cfYnDPw37OCW32jN6WZQwhAywMGQ650Dydn0i/574/Hv4Kxxh9XH660BY 8GbCWSAz1UEcP5zDxSXRyPh/jKOq9ns5cCCkcGOmSXx2NC1KR3YZAJZmR A==; X-CSE-ConnectionGUID: O4X8OD2eRqWXgG1Xyox6AQ== X-CSE-MsgGUID: bGkuQpXwQRuVo6sNf/GVMA== X-IronPort-AV: E=McAfee;i="6800,10657,11616"; a="82850973" X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="82850973" X-CSE-ConnectionGUID: widJFpnoR/Cc4abkrCeMSg== X-CSE-MsgGUID: jzXAZNucQui8I7qJiDTEBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,314,1754982000"; d="scan'208";a="189962691" From: Zhao Liu To: Paolo Bonzini Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, "Chang S . Bae" , Zide Chen , Xudong Hao , Zhao Liu , Peter Fang Subject: [PATCH 4/5] i386/cpu: Support APX CPUIDs Date: Tue, 18 Nov 2025 14:58:16 +0800 Message-Id: <20251118065817.835017-5-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118065817.835017-1-zhao1.liu@intel.com> References: <20251118065817.835017-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763447819279153000 Content-Type: text/plain; charset="utf-8" APX is enumerated by CPUID.(EAX=3D0x7, ECX=3D1).EDX[21]. And this feature bit also indicates the existence of dedicated CPUID leaf 0x29, called the Intel APX Advanced Performance Extensions Leaf. This new CPUID leaf now is populated with enumerations for a select set of Intel APX sub-features. CPUID.(EAX=3D0x29, ECX=3D0) - EAX * Maximum Subleaf CPUID.(EAX=3D0x29, ECX=3D0).EAX[31:0] =3D 0 - EBX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).EBX[31:1] =3D 0 * APX_NCI_NDD_NF CPUID.(EAX=3D0x29, ECX=3D0).EBX[0:0] =3D 1, which enumerates the presence of New Conditional Instructions (NCIs), explicit New Data Destination (NDD) controls, and explicit Flags Suppression (NF) controls for select sets of EVEX-encoded Intel APX instructions (present in EVEX map=3D4, and EVEX map=3D2 0x0F38). - ECX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).ECX[31:0] =3D 0 - EDX * Reserved CPUID.(EAX=3D0x29, ECX=3D0).EDX[31:0] =3D 0 Note, APX_NCI_NDD_NF is documented as always enabled for Intel processors since APX spec (revision v7.0). Now any Intel processor that enumerates support for APX_F (CPUID.(EAX=3D0x7, ECX=3D1).EDX[21]) will also enumerate support for APX_NCI_NDD_NF. Tested-by: Xudong Hao Co-developed-by: Zide Chen Signed-off-by: Zide Chen Co-developed-by: Peter Fang Signed-off-by: Peter Fang Signed-off-by: Zhao Liu --- target/i386/cpu.c | 40 +++++++++++++++++++++++++++++++++++++++- target/i386/cpu.h | 8 ++++++++ 2 files changed, 47 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 16bc4b18266c..9cc553a86442 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1036,6 +1036,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t ven= dor1, #define TCG_SGX_12_0_EBX_FEATURES 0 #define TCG_SGX_12_1_EAX_FEATURES 0 #define TCG_24_0_EBX_FEATURES 0 +#define TCG_29_0_EBX_FEATURES 0 =20 #if defined CONFIG_USER_ONLY #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \ @@ -1301,7 +1302,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "amx-complex", NULL, "avx-vnni-int16", NULL, NULL, NULL, "prefetchiti", NULL, NULL, NULL, NULL, "avx10", - NULL, NULL, NULL, NULL, + NULL, "apx", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, @@ -1345,6 +1346,25 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D= { }, .tcg_features =3D TCG_24_0_EBX_FEATURES, }, + [FEAT_29_0_EBX] =3D { + .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + "apx-nci-ndd-nf", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, + .cpuid =3D { + .eax =3D 0x29, + .needs_ecx =3D true, .ecx =3D 0, + .reg =3D R_EBX, + }, + .tcg_features =3D TCG_29_0_EBX_FEATURES, + }, [FEAT_8000_0007_EDX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1996,6 +2016,10 @@ static FeatureDep feature_dependencies[] =3D { .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_AVX10 }, .to =3D { FEAT_24_0_EBX, ~0ull }, }, + { + .from =3D { FEAT_7_1_EDX, CPUID_7_1_EDX_APX }, + .to =3D { FEAT_29_0_EBX, ~0ull }, + }, }; =20 typedef struct X86RegisterInfo32 { @@ -8411,6 +8435,15 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x29: + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if ((env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) && count =3D= =3D 0) { + *ebx =3D env->features[FEAT_29_0_EBX]; + } + break; case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff @@ -9190,6 +9223,11 @@ void x86_cpu_expand_features(X86CPU *cpu, Error **er= rp) x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x24); } =20 + /* Advanced Performance Extensions (APX) requires CPUID[0x29] */ + if (env->features[FEAT_7_1_EDX] & CPUID_7_1_EDX_APX) { + x86_cpu_adjust_level(cpu, &env->cpuid_min_level, 0x29); + } + /* SVM requires CPUID[0x8000000A] */ if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) { x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A); diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 48d4d7fcbb9c..d15a89f8c72e 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -697,6 +697,7 @@ typedef enum FeatureWord { FEAT_7_1_EDX, /* CPUID[EAX=3D7,ECX=3D1].EDX */ FEAT_7_2_EDX, /* CPUID[EAX=3D7,ECX=3D2].EDX */ FEAT_24_0_EBX, /* CPUID[EAX=3D0x24,ECX=3D0].EBX */ + FEAT_29_0_EBX, /* CPUID[EAX=3D0x29,ECX=3D0].EBX */ FEATURE_WORDS, } FeatureWord; =20 @@ -1079,6 +1080,13 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *= cpu, FeatureWord w); CPUID_24_0_EBX_AVX10_256 | \ CPUID_24_0_EBX_AVX10_512) =20 +/* + * New Conditional Instructions (NCIs), explicit New Data Destination (NDD) + * controls, and explicit Flags Suppression (NF) controls for select sets = of + * EVEX-encoded Intel APX instructions + */ +#define CPUID_29_0_EBX_APX_NCI_NDD_NF (1U << 0) + /* RAS Features */ #define CPUID_8000_0007_EBX_OVERFLOW_RECOV (1U << 0) #define CPUID_8000_0007_EBX_SUCCOR (1U << 1) --=20 2.34.1 From nobody Thu Nov 20 12:28:16 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1763447844; cv=none; d=zohomail.com; s=zohoarc; b=jXccpjpLWQS+NA8Ln7sHD6HTd7iAG+jDwhhs/p1DMz633aoTlgtWyGIRoQrd5FJF/72HmSTkRefdfUSSyB9SylV1UO6NeSXrjtbu44lwdvb4SYYa97peAJPJuHSDdHd+WQFiVGD37ZUnOr4HtwDTzGTQavA6RIFA4ZYzrK2yVa4= ARC-Message-Signature: i=1; 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Bae" , Zide Chen , Xudong Hao , Zhao Liu Subject: [PATCH 5/5] i386/cpu: Mark apx xstate as migratable Date: Tue, 18 Nov 2025 14:58:17 +0800 Message-Id: <20251118065817.835017-6-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118065817.835017-1-zhao1.liu@intel.com> References: <20251118065817.835017-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=198.175.65.10; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763447846503158500 Content-Type: text/plain; charset="utf-8" Apx xstate is user xstate. The related registers are cached in X86CPUState. And there's a vmsd "vmstate_apx" to migrate these registers. Thus, it's safe to mark it as migratable. Tested-by: Xudong Hao Signed-off-by: Zhao Liu --- target/i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 9cc553a86442..f703b1478d71 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1544,7 +1544,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .migratable_flags =3D XSTATE_FP_MASK | XSTATE_SSE_MASK | XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK | XSTATE_ZMM_Hi256_MASK | XSTATE_Hi16_ZMM_M= ASK | - XSTATE_PKRU_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_M= ASK, + XSTATE_PKRU_MASK | XSTATE_XTILE_CFG_MASK | XSTATE_XTILE_DATA_M= ASK | + XSTATE_APX_MASK, }, [FEAT_XSAVE_XCR0_HI] =3D { .type =3D CPUID_FEATURE_WORD, --=20 2.34.1