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a="68053745" X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="68053745" X-CSE-ConnectionGUID: uSrAk/myTAuRrbqhnqyNbg== X-CSE-MsgGUID: dL83uZetQhGlRy+SVpzJBw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="221537149" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v4 03/23] i386/cpu: Reorganize arch lbr structure definitions Date: Tue, 18 Nov 2025 11:42:11 +0800 Message-Id: <20251118034231.704240-4-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118034231.704240-1-zhao1.liu@intel.com> References: <20251118034231.704240-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763436128176153000 Content-Type: text/plain; charset="utf-8" - Move ARCH_LBR_NR_ENTRIES macro and LBREntry definition before XSAVE areas definitions. - Reorder XSavesArchLBR (area 15) between XSavePKRU (area 9) and XSaveXTILECFG (area 17), and reorder the related QEMU_BUILD_BUG_ON check to keep the same ordering. This makes xsave structures to be organized together and makes them clearer. Tested-by: Farrah Chen Reviewed-by: Zide Chen Reviewed-by: Xiaoyao Li Signed-off-by: Zhao Liu --- target/i386/cpu.h | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index c95b772719ce..a183394eca7f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1652,6 +1652,14 @@ typedef struct { =20 #define NB_OPMASK_REGS 8 =20 +typedef struct { + uint64_t from; + uint64_t to; + uint64_t info; +} LBREntry; + +#define ARCH_LBR_NR_ENTRIES 32 + /* CPU can't have 0xFFFFFFFF APIC ID, use that value to distinguish * that APIC ID hasn't been set yet */ @@ -1729,24 +1737,6 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 -/* Ext. save area 17: AMX XTILECFG state */ -typedef struct XSaveXTILECFG { - uint8_t xtilecfg[64]; -} XSaveXTILECFG; - -/* Ext. save area 18: AMX XTILEDATA state */ -typedef struct XSaveXTILEDATA { - uint8_t xtiledata[8][1024]; -} XSaveXTILEDATA; - -typedef struct { - uint64_t from; - uint64_t to; - uint64_t info; -} LBREntry; - -#define ARCH_LBR_NR_ENTRIES 32 - /* Ext. save area 15: Arch LBR state */ typedef struct XSaveArchLBR { uint64_t lbr_ctl; @@ -1757,6 +1747,16 @@ typedef struct XSaveArchLBR { LBREntry lbr_records[ARCH_LBR_NR_ENTRIES]; } XSaveArchLBR; =20 +/* Ext. save area 17: AMX XTILECFG state */ +typedef struct XSaveXTILECFG { + uint8_t xtilecfg[64]; +} XSaveXTILECFG; + +/* Ext. save area 18: AMX XTILEDATA state */ +typedef struct XSaveXTILEDATA { + uint8_t xtiledata[8][1024]; +} XSaveXTILEDATA; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1764,9 +1764,9 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); -QEMU_BUILD_BUG_ON(sizeof(XSaveArchLBR) !=3D 0x328); =20 typedef struct ExtSaveArea { uint32_t feature, bits; --=20 2.34.1