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a="68053725" X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="68053725" X-CSE-ConnectionGUID: jryimD4CS16MurwiigIJLg== X-CSE-MsgGUID: P4zwZAEkRfKOyfaRWxrCAA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="221537132" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v4 01/23] i386/cpu: Clean up indent style of x86_ext_save_areas[] Date: Tue, 18 Nov 2025 11:42:09 +0800 Message-Id: <20251118034231.704240-2-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118034231.704240-1-zhao1.liu@intel.com> References: <20251118034231.704240-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763436135259158500 Content-Type: text/plain; charset="utf-8" The indentation style in `x86_ext_save_areas[]` is extremely inconsistent. Clean it up to ensure a uniform style. Tested-by: Farrah Chen Reviewed-by: Xiaoyao Li Signed-off-by: Zhao Liu --- target/i386/cpu.c | 58 +++++++++++++++++++++++++++-------------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 641777578637..c598f09f3d50 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -2028,38 +2028,46 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COU= NT] =3D { .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_XSAVE, .size =3D sizeof(X86LegacyXSaveArea) + sizeof(X86XSaveHeader), }, - [XSTATE_YMM_BIT] =3D - { .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_AVX, - .size =3D sizeof(XSaveAVX) }, - [XSTATE_BNDREGS_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .size =3D sizeof(XSaveBNDREG) }, - [XSTATE_BNDCSR_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, - .size =3D sizeof(XSaveBNDCSR) }, - [XSTATE_OPMASK_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveOpmask) }, - [XSTATE_ZMM_Hi256_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveZMM_Hi256) }, - [XSTATE_Hi16_ZMM_BIT] =3D - { .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, - .size =3D sizeof(XSaveHi16_ZMM) }, - [XSTATE_PKRU_BIT] =3D - { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, - .size =3D sizeof(XSavePKRU) }, + [XSTATE_YMM_BIT] =3D { + .feature =3D FEAT_1_ECX, .bits =3D CPUID_EXT_AVX, + .size =3D sizeof(XSaveAVX), + }, + [XSTATE_BNDREGS_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, + .size =3D sizeof(XSaveBNDREG), + }, + [XSTATE_BNDCSR_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_MPX, + .size =3D sizeof(XSaveBNDCSR), + }, + [XSTATE_OPMASK_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveOpmask), + }, + [XSTATE_ZMM_Hi256_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveZMM_Hi256), + }, + [XSTATE_Hi16_ZMM_BIT] =3D { + .feature =3D FEAT_7_0_EBX, .bits =3D CPUID_7_0_EBX_AVX512F, + .size =3D sizeof(XSaveHi16_ZMM), + }, + [XSTATE_PKRU_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, + .size =3D sizeof(XSavePKRU), + }, [XSTATE_ARCH_LBR_BIT] =3D { - .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, - .offset =3D 0 /*supervisor mode component, offset =3D 0 */, - .size =3D sizeof(XSavesArchLBR) }, + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_ARCH_LBR, + .offset =3D 0 /*supervisor mode component, offset =3D 0 */, + .size =3D sizeof(XSavesArchLBR), + }, [XSTATE_XTILE_CFG_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, .size =3D sizeof(XSaveXTILECFG), }, [XSTATE_XTILE_DATA_BIT] =3D { .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, - .size =3D sizeof(XSaveXTILEDATA) + .size =3D sizeof(XSaveXTILEDATA), }, }; =20 --=20 2.34.1