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a="68053886" X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="68053886" X-CSE-ConnectionGUID: z3MWa+37RL2HVBKD4nv5tA== X-CSE-MsgGUID: cwPmblDqQneNRq0+Oxn7fQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="221537295" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu , Yang Weijiang Subject: [PATCH v4 15/23] i386/kvm: Add save/restore support for CET MSRs Date: Tue, 18 Nov 2025 11:42:23 +0800 Message-Id: <20251118034231.704240-16-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118034231.704240-1-zhao1.liu@intel.com> References: <20251118034231.704240-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763436116156153000 Content-Type: text/plain; charset="utf-8" From: Yang Weijiang CET (architectural) MSRs include: MSR_IA32_U_CET - user mode CET control bits. MSR_IA32_S_CET - supervisor mode CET control bits. MSR_IA32_PL{0,1,2,3}_SSP - linear addresses of SSPs for user/kernel modes. MSR_IA32_INT_SSP_TAB - linear address of interrupt SSP table Since FRED also needs to save/restore MSR_IA32_PL0_SSP, to avoid duplicate operations, make FRED only save/restore MSR_IA32_PL0_SSP when CET-SHSTK is not enumerated. And considerring MSR_IA32_SSP_TBL_ADDR is only presented on 64 bit processor, wrap it with TARGET_X86_64 macro. For other MSRs, add save/restore support directly. Tested-by: Farrah Chen Suggested-by: Xin Li (Intel) Signed-off-by: Yang Weijiang Co-developed-by: Chao Gao Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v3: - Make FRED only save/restore MSR_IA32_PL0_SSP when CET-SHSTK isn't enumerated. - Wrap MSR_IA32_INT_SSP_TAB with TARGET_X86_64 since it's a x86_64-specific MSR. Changes Since v2: - Rename MSR_IA32_SSP_TBL_ADDR to MSR_IA32_INT_SSP_TAB. - Rename X86CPUState.ssp_table_addr to X86CPUState.int_ssp_table. - Drop X86CPUStete.guest_ssp since it is not used in current commit. - Do not check CET-S & CET-U xtates when get/set MSTs since CET is XSAVE-managed feature but is not XSAVE-enabled. --- target/i386/cpu.h | 26 ++++++++++--- target/i386/kvm/kvm.c | 91 ++++++++++++++++++++++++++++++++++++------- 2 files changed, 98 insertions(+), 19 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 0432af1769d2..661b798da4d0 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -543,7 +543,7 @@ typedef enum X86Seg { #define MSR_IA32_XFD 0x000001c4 #define MSR_IA32_XFD_ERR 0x000001c5 =20 -/* FRED MSRs */ +/* FRED MSRs (MSR_IA32_FRED_SSP0 is defined as MSR_IA32_PL0_SSP in CET MSR= s) */ #define MSR_IA32_FRED_RSP0 0x000001cc /* Stack level 0 = regular stack pointer */ #define MSR_IA32_FRED_RSP1 0x000001cd /* Stack level 1 = regular stack pointer */ #define MSR_IA32_FRED_RSP2 0x000001ce /* Stack level 2 = regular stack pointer */ @@ -554,9 +554,6 @@ typedef enum X86Seg { #define MSR_IA32_FRED_SSP3 0x000001d3 /* Stack level 3 = shadow stack pointer in ring 0 */ #define MSR_IA32_FRED_CONFIG 0x000001d4 /* FRED Entrypoin= t and interrupt stack level */ =20 -/* FRED and CET MSR */ -#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow = stack pointer (aka MSR_IA32_FRED_SSP0 for FRED) */ - #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -583,6 +580,15 @@ typedef enum X86Seg { #define MSR_APIC_START 0x00000800 #define MSR_APIC_END 0x000008ff =20 +/* CET MSRs */ +#define MSR_IA32_U_CET 0x000006a0 /* user mode cet = */ +#define MSR_IA32_S_CET 0x000006a2 /* kernel mode ce= t */ +#define MSR_IA32_PL0_SSP 0x000006a4 /* ring-0 shadow = stack pointer */ +#define MSR_IA32_PL1_SSP 0x000006a5 /* ring-1 shadow = stack pointer */ +#define MSR_IA32_PL2_SSP 0x000006a6 /* ring-2 shadow = stack pointer */ +#define MSR_IA32_PL3_SSP 0x000006a7 /* ring-3 shadow = stack pointer */ +#define MSR_IA32_INT_SSP_TAB 0x000006a8 /* exception shad= ow stack table */ + #define XSTATE_FP_BIT 0 #define XSTATE_SSE_BIT 1 #define XSTATE_YMM_BIT 2 @@ -1976,8 +1982,16 @@ typedef struct CPUArchState { uint64_t fred_config; #endif =20 - /* MSR used for both FRED and CET (SHSTK) */ - uint64_t pl0_ssp; + /* CET MSRs */ + uint64_t u_cet; + uint64_t s_cet; + uint64_t pl0_ssp; /* also used for FRED */ + uint64_t pl1_ssp; + uint64_t pl2_ssp; + uint64_t pl3_ssp; +#ifdef TARGET_X86_64 + uint64_t int_ssp_table; +#endif =20 uint64_t tsc_adjust; uint64_t tsc_deadline; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 00fead0827ed..4eb58ca19d79 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -4008,11 +4008,14 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState le= vel) kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, env->fred_ssp2); kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, env->fred_ssp3); kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, env->fred_config); - /* - * Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if - * CET shadow stack is not supported. - */ - kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + + if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + /* + * Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if + * CET shadow stack is not supported. + */ + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + } } } #endif @@ -4266,6 +4269,26 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState lev= el) } } =20 + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK || + env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, env->u_cet); + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, env->s_cet); + + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, env->pl0_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, env->pl1_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, env->pl2_ssp); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, env->pl3_ssp); + +#ifdef TARGET_X86_64 + if (lm_capable_kernel) { + kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB, + env->int_ssp_table); + } +#endif + } + } + return kvm_buf_set_msrs(cpu); } =20 @@ -4500,11 +4523,14 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP2, 0); kvm_msr_entry_add(cpu, MSR_IA32_FRED_SSP3, 0); kvm_msr_entry_add(cpu, MSR_IA32_FRED_CONFIG, 0); - /* - * Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if - * CET shadow stack is not supported. - */ - kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + + if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK)) { + /* + * Aka MSR_IA32_FRED_SSP0. This MSR is accessible even if + * CET shadow stack is not supported. + */ + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + } } } #endif @@ -4662,6 +4688,25 @@ static int kvm_get_msrs(X86CPU *cpu) } } =20 + if (env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_CET_SHSTK || + env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_CET_IBT) { + kvm_msr_entry_add(cpu, MSR_IA32_U_CET, 0); + kvm_msr_entry_add(cpu, MSR_IA32_S_CET, 0); + + if (env->features[FEAT_7_0_EDX] & CPUID_7_0_ECX_CET_SHSTK) { + kvm_msr_entry_add(cpu, MSR_IA32_PL0_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL1_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL2_SSP, 0); + kvm_msr_entry_add(cpu, MSR_IA32_PL3_SSP, 0); + +#ifdef TARGET_X86_64 + if (lm_capable_kernel) { + kvm_msr_entry_add(cpu, MSR_IA32_INT_SSP_TAB, 0); + } +#endif + } + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -4756,9 +4801,6 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_FRED_CONFIG: env->fred_config =3D msrs[i].data; break; - case MSR_IA32_PL0_SSP: /* aka MSR_IA32_FRED_SSP0 */ - env->pl0_ssp =3D msrs[i].data; - break; #endif case MSR_IA32_TSC: env->tsc =3D msrs[i].data; @@ -5012,6 +5054,29 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_ARCH_LBR_INFO_0 ... MSR_ARCH_LBR_INFO_0 + 31: env->lbr_records[index - MSR_ARCH_LBR_INFO_0].info =3D msrs[i]= .data; break; + case MSR_IA32_U_CET: + env->u_cet =3D msrs[i].data; + break; + case MSR_IA32_S_CET: + env->s_cet =3D msrs[i].data; + break; + case MSR_IA32_PL0_SSP: /* aka MSR_IA32_FRED_SSP0 */ + env->pl0_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL1_SSP: + env->pl1_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL2_SSP: + env->pl2_ssp =3D msrs[i].data; + break; + case MSR_IA32_PL3_SSP: + env->pl3_ssp =3D msrs[i].data; + break; +#ifdef TARGET_X86_64 + case MSR_IA32_INT_SSP_TAB: + env->int_ssp_table =3D msrs[i].data; + break; +#endif case MSR_K7_HWCR: env->msr_hwcr =3D msrs[i].data; break; --=20 2.34.1