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a="68053822" X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="68053822" X-CSE-ConnectionGUID: jt3zLP1qQDOpCq+K7ZLdlg== X-CSE-MsgGUID: xkS3xGu6QFSU7K/EdFT2kw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,313,1754982000"; d="scan'208";a="221537198" From: Zhao Liu To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org, Chao Gao , Xin Li , John Allen , Babu Moger , Mathias Krause , Dapeng Mi , Zide Chen , Xiaoyao Li , Chenyi Qiang , Farrah Chen , Zhao Liu Subject: [PATCH v4 10/23] i386/cpu: Fix supervisor xstate initialization Date: Tue, 18 Nov 2025 11:42:18 +0800 Message-Id: <20251118034231.704240-11-zhao1.liu@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251118034231.704240-1-zhao1.liu@intel.com> References: <20251118034231.704240-1-zhao1.liu@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.13; envelope-from=zhao1.liu@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763436099673153000 Content-Type: text/plain; charset="utf-8" From: Chao Gao Arch lbr is a supervisor xstate, but its area is not covered in x86_cpu_init_xsave(). Fix it by checking supported xss bitmap. In addition, drop the (uint64_t) type casts for supported_xcr0 since x86_cpu_get_supported_feature_word() returns uint64_t so that the cast is not needed. Then ensure line length is within 90 characters. Tested-by: Farrah Chen Reviewed-by: Xiaoyao Li Signed-off-by: Chao Gao Co-developed-by: Zhao Liu Signed-off-by: Zhao Liu --- Changes Since v3: - Fix shift for CXRO high 32 bits. --- target/i386/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 62769db3ebb7..859cb889a37c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -9711,20 +9711,23 @@ static void x86_cpu_post_initfn(Object *obj) static void x86_cpu_init_xsave(void) { static bool first =3D true; - uint64_t supported_xcr0; + uint64_t supported_xcr0, supported_xss; int i; =20 if (first) { first =3D false; =20 supported_xcr0 =3D - ((uint64_t) x86_cpu_get_supported_feature_word(NULL, FEAT_XSAV= E_XCR0_HI) << 32) | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_HI) <= < 32 | x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XCR0_LO); + supported_xss =3D + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_HI) <<= 32 | + x86_cpu_get_supported_feature_word(NULL, FEAT_XSAVE_XSS_LO); =20 for (i =3D XSTATE_SSE_BIT + 1; i < XSAVE_STATE_AREA_COUNT; i++) { ExtSaveArea *esa =3D &x86_ext_save_areas[i]; =20 - if (!(supported_xcr0 & (1 << i))) { + if (!((supported_xcr0 | supported_xss) & (1 << i))) { esa->size =3D 0; } } --=20 2.34.1