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a="76045990" X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="76045990" X-CSE-ConnectionGUID: BHqnnqOcQsWI2kdEUJYcLw== X-CSE-MsgGUID: syPRiUC0SJaYP5+Xoag2/g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="190070930" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v8 11/23] intel_iommu_accel: Stick to system MR for IOMMUFD backed host device when x-flts=on Date: Mon, 17 Nov 2025 04:37:14 -0500 Message-ID: <20251117093729.1121324-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251117093729.1121324-1-zhenzhong.duan@intel.com> References: <20251117093729.1121324-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763372452850158500 Content-Type: text/plain; charset="utf-8" When guest enables scalable mode and setup first stage page table, we don't want to use IOMMU MR but rather continue using the system MR for IOMMUFD backed host device. Then default HWPT in VFIO contains GPA->HPA mappings which could be reused as nesting parent HWPT to construct nested HWPT in vIOMMU. Move vtd_as_key into intel_iommu_internal.h as it's also used by accel code. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu_accel.h | 6 ++++++ hw/i386/intel_iommu_internal.h | 11 +++++++++++ hw/i386/intel_iommu.c | 28 +++++++++++++++------------- hw/i386/intel_iommu_accel.c | 18 ++++++++++++++++++ 4 files changed, 50 insertions(+), 13 deletions(-) diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h index 7ebf137a1a..dbe6ee6982 100644 --- a/hw/i386/intel_iommu_accel.h +++ b/hw/i386/intel_iommu_accel.h @@ -15,6 +15,7 @@ #ifdef CONFIG_VTD_ACCEL bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, Error **errp); +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as); #else static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod, @@ -24,5 +25,10 @@ static inline bool vtd_check_hiod_accel(IntelIOMMUState = *s, "host IOMMU is incompatible with guest first stage translat= ion"); return false; } + +static inline VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *a= s) +{ + return NULL; +} #endif #endif diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 02522f64e0..d8dad18304 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -685,4 +685,15 @@ typedef struct VTDHostIOMMUDevice { uint8_t devfn; HostIOMMUDevice *hiod; } VTDHostIOMMUDevice; + +/* + * PCI bus number (or SID) is not reliable since the device is usaully + * initialized before guest can configure the PCI bridge + * (SECONDARY_BUS_NUMBER). + */ +struct vtd_as_key { + PCIBus *bus; + uint8_t devfn; + uint32_t pasid; +}; #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4ebf56a74f..29e0281af8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -56,17 +56,6 @@ #define VTD_PE_GET_SS_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) =20 -/* - * PCI bus number (or SID) is not reliable since the device is usaully - * initialized before guest can configure the PCI bridge - * (SECONDARY_BUS_NUMBER). - */ -struct vtd_as_key { - PCIBus *bus; - uint8_t devfn; - uint32_t pasid; -}; - /* bus/devfn is PCI device's real BDF not the aliased one */ struct vtd_hiod_key { PCIBus *bus; @@ -1731,12 +1720,25 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) /* Return whether the device is using IOMMU translation. */ static bool vtd_switch_address_space(VTDAddressSpace *as) { + IntelIOMMUState *s; bool use_iommu, pt; =20 assert(as); =20 - use_iommu =3D as->iommu_state->dmar_enabled && !vtd_as_pt_enabled(as); - pt =3D as->iommu_state->dmar_enabled && vtd_as_pt_enabled(as); + s =3D as->iommu_state; + use_iommu =3D s->dmar_enabled && !vtd_as_pt_enabled(as); + pt =3D s->dmar_enabled && vtd_as_pt_enabled(as); + + /* + * When guest enables scalable mode and sets up first stage page table, + * we stick to system MR for IOMMUFD backed host device. Then its + * default hwpt contains GPA->HPA mappings which is used directly if + * PGTT=3DPT and used as nesting parent if PGTT=3DFST. Otherwise fall = back + * to original processing. + */ + if (s->root_scalable && s->fsts && vtd_find_hiod_iommufd(as)) { + use_iommu =3D false; + } =20 trace_vtd_switch_address_space(pci_bus_num(as->bus), VTD_PCI_SLOT(as->devfn), diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c index ead6c42879..ebfc503d64 100644 --- a/hw/i386/intel_iommu_accel.c +++ b/hw/i386/intel_iommu_accel.c @@ -50,3 +50,21 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOM= MUDevice *vtd_hiod, "host IOMMU is incompatible with guest first stage translat= ion"); return false; } + +VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as) +{ + IntelIOMMUState *s =3D as->iommu_state; + struct vtd_as_key key =3D { + .bus =3D as->bus, + .devfn =3D as->devfn, + }; + VTDHostIOMMUDevice *vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu= _dev, + &key); + + if (vtd_hiod && vtd_hiod->hiod && + object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + return vtd_hiod; + } + return NULL; +} --=20 2.47.1