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a="76045973" X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="76045973" X-CSE-ConnectionGUID: gpnI5MW7Qfq23IiSFKV1xw== X-CSE-MsgGUID: 6zSpBM+nS0ioAHlo+/vyZg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,311,1754982000"; d="scan'208";a="190070917" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, skolothumtho@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v8 09/23] intel_iommu_accel: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Mon, 17 Nov 2025 04:37:12 -0500 Message-ID: <20251117093729.1121324-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20251117093729.1121324-1-zhenzhong.duan@intel.com> References: <20251117093729.1121324-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1763372475683153000 When vIOMMU is configured x-flts=3Don in scalable mode, first stage page ta= ble is passed to host to construct nested page table for passthrough devices. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest first stage page table could be used = by host. For instance, vIOMMU supports first stage 1GB large page mapping, but host = does not, then this IOMMUFD backed device should fail. Even of the checks pass, for now we willingly reject the association because all the bits are not there yet, it will be relaxed in the end of this serie= s. Note vIOMMU has exposed IOMMU_HWPT_ALLOC_NEST_PARENT flag to force VFIO cor= e to create nesting parent HWPT, if host doesn't support nested translation, the creation will fail. So no need to check nested capability here. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- MAINTAINERS | 1 + hw/i386/intel_iommu_accel.h | 28 +++++++++++++++++++++++++ hw/i386/intel_iommu.c | 5 ++--- hw/i386/intel_iommu_accel.c | 42 +++++++++++++++++++++++++++++++++++++ hw/i386/Kconfig | 5 +++++ hw/i386/meson.build | 1 + 6 files changed, 79 insertions(+), 3 deletions(-) create mode 100644 hw/i386/intel_iommu_accel.h create mode 100644 hw/i386/intel_iommu_accel.c diff --git a/MAINTAINERS b/MAINTAINERS index f4a30c126b..bc1d2b6261 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3929,6 +3929,7 @@ R: Cl=C3=A9ment Mathieu--Drif S: Supported F: hw/i386/intel_iommu.c F: hw/i386/intel_iommu_internal.h +F: hw/i386/intel_iommu_accel.* F: include/hw/i386/intel_iommu.h F: tests/functional/x86_64/test_intel_iommu.py F: tests/qtest/intel-iommu-test.c diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h new file mode 100644 index 0000000000..c5274e342c --- /dev/null +++ b/hw/i386/intel_iommu_accel.h @@ -0,0 +1,28 @@ +/* + * Intel IOMMU acceleration with nested translation + * + * Copyright (C) 2025 Intel Corporation. + * + * Authors: Zhenzhong Duan + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_I386_INTEL_IOMMU_ACCEL_H +#define HW_I386_INTEL_IOMMU_ACCEL_H +#include CONFIG_DEVICES + +#ifdef CONFIG_VTD_ACCEL +bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, + Error **errp); +#else +static inline bool vtd_check_hiod_accel(IntelIOMMUState *s, + HostIOMMUDevice *hiod, + Error **errp) +{ + error_setg(errp, + "host IOMMU is incompatible with guest first stage translat= ion"); + return false; +} +#endif +#endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 3095d78321..d3c8a75878 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -26,6 +26,7 @@ #include "hw/sysbus.h" #include "hw/iommu.h" #include "intel_iommu_internal.h" +#include "intel_iommu_accel.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" @@ -4596,9 +4597,7 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, return true; } =20 - error_setg(errp, - "host device is uncompatible with first stage translation"); - return false; + return vtd_check_hiod_accel(s, hiod, errp); } =20 static bool vtd_dev_set_iommu_device(PCIBus *bus, void *opaque, int devfn, diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c new file mode 100644 index 0000000000..6846c6ec4d --- /dev/null +++ b/hw/i386/intel_iommu_accel.c @@ -0,0 +1,42 @@ +/* + * Intel IOMMU acceleration with nested translation + * + * Copyright (C) 2025 Intel Corporation. + * + * Authors: Zhenzhong Duan + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "system/iommufd.h" +#include "intel_iommu_internal.h" +#include "intel_iommu_accel.h" + +bool vtd_check_hiod_accel(IntelIOMMUState *s, HostIOMMUDevice *hiod, + Error **errp) +{ + struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; + struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + if (caps->type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", + caps->type); + return false; + } + + if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) { + error_setg(errp, + "First stage 1GB large page is unsupported by host IOMM= U"); + return false; + } + + error_setg(errp, + "host IOMMU is incompatible with guest first stage translat= ion"); + return false; +} diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 6a0ab54bea..12473acaa7 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -150,8 +150,13 @@ config X86_IOMMU =20 config VTD bool + imply VTD_ACCEL select X86_IOMMU =20 +config VTD_ACCEL + bool + depends on VTD && IOMMUFD + config AMD_IOMMU bool select X86_IOMMU diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 436b3ce52d..63ae57baa5 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -21,6 +21,7 @@ i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c'= )) i386_ss.add(when: 'CONFIG_VMMOUSE', if_true: files('vmmouse.c')) i386_ss.add(when: 'CONFIG_VMPORT', if_true: files('vmport.c')) i386_ss.add(when: 'CONFIG_VTD', if_true: files('intel_iommu.c')) +i386_ss.add(when: 'CONFIG_VTD_ACCEL', if_true: files('intel_iommu_accel.c'= )) i386_ss.add(when: 'CONFIG_SGX', if_true: files('sgx-epc.c','sgx.c'), if_false: files('sgx-stub.c')) =20 --=20 2.47.1