From nobody Mon Dec 15 02:04:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1763189648147641.6640957462184; Fri, 14 Nov 2025 22:54:08 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vKA8z-0006Uo-Rm; Sat, 15 Nov 2025 01:52:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vKA8w-0006TV-VT for qemu-devel@nongnu.org; Sat, 15 Nov 2025 01:52:19 -0500 Received: from inva021.nxp.com ([92.121.34.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vKA8t-0008Kz-D7 for qemu-devel@nongnu.org; Sat, 15 Nov 2025 01:52:18 -0500 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id DDB78202BCF; Sat, 15 Nov 2025 07:52:13 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id A9A552013C7; Sat, 15 Nov 2025 07:52:13 +0100 (CET) Received: from lsv031015.swis.in-blr01.nxp.com (lsv031015.swis.in-blr01.nxp.com [10.12.177.77]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id D10841800091; Sat, 15 Nov 2025 14:52:12 +0800 (+08) From: Gaurav Sharma To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peter.maydell@linaro.org, Gaurav Sharma Subject: [PATCHv2 03/13] hw/arm/fsl-imx8mm: Implemented support for SNVS Date: Sat, 15 Nov 2025 12:20:49 +0530 Message-Id: <20251115065059.1884980-4-gaurav.sharma_7@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251115065059.1884980-1-gaurav.sharma_7@nxp.com> References: <20251115065059.1884980-1-gaurav.sharma_7@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=92.121.34.21; envelope-from=gaurav.sharma_7@nxp.com; helo=inva021.nxp.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1763189649198158500 Content-Type: text/plain; charset="utf-8" SNVS contains an RTC which allows Linux to deal correctly with time Signed-off-by: Gaurav Sharma --- docs/system/arm/imx8mm-evk.rst | 1 + hw/arm/fsl-imx8mm.c | 10 ++++++++++ include/hw/arm/fsl-imx8mm.h | 2 ++ 3 files changed, 13 insertions(+) diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst index 5b1267adce..cc285068dc 100644 --- a/docs/system/arm/imx8mm-evk.rst +++ b/docs/system/arm/imx8mm-evk.rst @@ -12,6 +12,7 @@ The ``imx8mm-evk`` machine implements the following devic= es: * Up to 4 Cortex-A53 cores * Generic Interrupt Controller (GICv3) * 4 UARTs + * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 Boot options diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index 5425dc8a53..4ca5dd0af1 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -170,6 +170,8 @@ static void fsl_imx8mm_init(Object *obj) =20 object_initialize_child(obj, "analog", &s->analog, TYPE_IMX8MM_ANALOG); =20 + object_initialize_child(obj, "snvs", &s->snvs, TYPE_IMX7_SNVS); + for (i =3D 0; i < FSL_IMX8MM_NUM_UARTS; i++) { g_autofree char *name =3D g_strdup_printf("uart%d", i + 1); object_initialize_child(obj, name, &s->uart[i], TYPE_IMX_SERIAL); @@ -340,6 +342,13 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, serial_table[i].irq)); } =20 + /* SNVS */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, + fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr); + /* Unimplemented devices */ for (i =3D 0; i < ARRAY_SIZE(fsl_imx8mm_memmap); i++) { switch (i) { @@ -348,6 +357,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_RAM: + case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: /* device implemented and treated above */ break; diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index 0716484429..4fd11798a5 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -12,6 +12,7 @@ #include "cpu.h" #include "hw/char/imx_serial.h" #include "hw/intc/arm_gicv3_common.h" +#include "hw/misc/imx7_snvs.h" #include "hw/misc/imx8mm_analog.h" #include "hw/misc/imx8mm_ccm.h" #include "qom/object.h" @@ -36,6 +37,7 @@ struct FslImx8mmState { GICv3State gic; IMX8MMCCMState ccm; IMX8MMAnalogState analog; + IMX7SNVSState snvs; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; }; =20 --=20 2.34.1