From nobody Fri Nov 14 16:59:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762916942; cv=none; d=zohomail.com; s=zohoarc; b=WBmhfxLTOAT2ol6x8dfF7yeo6jCnR8y6abhule/mFPk5yY8p+mI3/x4HMI7MQwWM0uTad0lzUoGq258/t4N1ZI++g1y5fyUnuf4GKHv+O3OFotcFGbzhCHopaiIryZIf29zRkxlgWzI2Oy8E0ngAookFKtrdqhXSX2Ut5QeJMVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762916942; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=UAxXhNtkkFV6RwY+STNJ+mTyU+oxYLiQ2vSwnI6kzlU=; b=XXQbz6JX0xMWxZTZMkYRZ/Tqc7/S4l2dlIhNCp9CdlxYV5xxj4uYFORU+SPyecPYN/vSxNVWSeb2oXEtQVwQG49zbjAAv1oTL1hpGJg80fFl7/SFo9mrnpLDAOGL/4HzGV/L06/txfoLGgLQ0fUMcXdr5rnzRzP9t4i24V8jXIg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762916942556751.7309597665574; Tue, 11 Nov 2025 19:09:02 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vJ1Br-0000es-6R; Tue, 11 Nov 2025 22:06:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vJ1Bo-0000cr-WD; Tue, 11 Nov 2025 22:06:33 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vJ1Bn-0003zx-Bi; Tue, 11 Nov 2025 22:06:32 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Wed, 12 Nov 2025 11:05:56 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Wed, 12 Nov 2025 11:05:55 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v2 08/12] hw/arm/aspeed_ast10x0: Add AST1060 SoC support Date: Wed, 12 Nov 2025 11:05:45 +0800 Message-ID: <20251112030553.291734-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251112030553.291734-1-jamin_lin@aspeedtech.com> References: <20251112030553.291734-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762916944359153000 Content-Type: text/plain; charset="utf-8" Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most of the AST1030 peripheral device models, as the two SoCs share nearly the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC, and SPI. A new common initialization and realization framework (ast10x0_init and ast10x0_realize) is leveraged so AST1060 can instantiate the existing AST1030 models without redefining duplicate device types. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast10x0.c | 59 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 1521000af0..bcfe83bdb7 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -185,6 +185,23 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 +static void aspeed_soc_ast1060_init(Object *obj) +{ + /* + * The AST1060 SoC reuses the AST1030 device models. Since all periphe= ral + * models (e.g. WDT, SCU, TIMER, HACE, ADC, I2C, FMC, SPI) defined for + * AST1030 are compatible with AST1060, we simply reuse the existing + * AST1030 models for AST1060. + * + * To simplify the implementation, AST1060 sets its socname to that of + * AST1030, avoiding the need to create a full set of new + * TYPE_ASPEED_1060_XXX device definitions. This allows the same + * TYPE_ASPEED_1030_WDT and other models to be instantiated for both + * SoCs. + */ + aspeed_soc_ast10x0_init(obj, "ast1030"); +} + static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { AspeedSoCState *s =3D ASPEED_SOC(a); @@ -451,6 +468,15 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 +static void aspeed_soc_ast1060_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } +} + static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) { static const char * const valid_cpu_types[] =3D { @@ -479,6 +505,32 @@ static void aspeed_soc_ast1030_class_init(ObjectClass = *klass, const void *data) sc->num_cpus =3D 1; } =20 +static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *= data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast1060_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST1060_A2_SILICON_REV; + sc->sram_size =3D 0xc0000; + sc->secsram_size =3D 0x40000; /* 256 * KiB */ + sc->spis_num =3D 2; + sc->wdts_num =3D 4; + sc->uarts_num =3D 1; + sc->uarts_base =3D ASPEED_DEV_UART5; + sc->irqmap =3D aspeed_soc_ast1030_irqmap; + sc->memmap =3D aspeed_soc_ast1030_memmap; + sc->num_cpus =3D 1; +} + static const TypeInfo aspeed_soc_ast10x0_types[] =3D { { .name =3D TYPE_ASPEED10X0_SOC, @@ -490,7 +542,12 @@ static const TypeInfo aspeed_soc_ast10x0_types[] =3D { .parent =3D TYPE_ASPEED10X0_SOC, .instance_init =3D aspeed_soc_ast1030_init, .class_init =3D aspeed_soc_ast1030_class_init, - }, + }, { + .name =3D "ast1060-a2", + .parent =3D TYPE_ASPEED10X0_SOC, + .instance_init =3D aspeed_soc_ast1060_init, + .class_init =3D aspeed_soc_ast1060_class_init, + } }; =20 DEFINE_TYPES(aspeed_soc_ast10x0_types) --=20 2.43.0