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Tue, 11 Nov 2025 03:48:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Daniel Henrique Barboza Subject: [PATCH v2 14/17] hw/riscv, target/riscv: send resync updiscon trace packets Date: Tue, 11 Nov 2025 08:46:53 -0300 Message-ID: <20251111114656.2285048-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111114656.2285048-1-dbarboza@ventanamicro.com> References: <20251111114656.2285048-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1762861855869158500 Content-Type: text/plain; charset="utf-8" Send updiscon packets based on the constraints already discussed in the previous patch: - We do not implement any form of call/return prediction in the encoder, and TCG will always retire a single insn per cycle, e.g. irreport will always be equal to updiscon; - irdepth is not implemented since we'll always return a package where irreport =3D=3D updiscon. Note that we're sending an updiscon packet if the 'updiscon_pending' flag is set when we're about the send a resync or a trap packet. The TCG helper in this case is just setting the trace encoder flags instead of actually triggering a RAM sink SMEM write. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/trace-encoder.c | 37 +++++++++++++++++++ hw/riscv/trace-encoder.h | 3 ++ target/riscv/helper.h | 1 + .../riscv/insn_trans/trans_privileged.c.inc | 11 ++++++ target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/trace_helper.c | 14 +++++++ target/riscv/translate.c | 9 +++++ 7 files changed, 77 insertions(+) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 9a4530bbea..5572483d26 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -402,6 +402,22 @@ static void trencoder_send_sync_msg(Object *trencoder_= obj, uint64_t pc) trencoder_send_message_smem(trencoder, msg, msg_size); } =20 +static void trencoder_send_updiscon(TraceEncoder *trencoder, uint64_t pc) +{ + g_autofree uint8_t *format2_msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); + uint8_t addr_msb =3D extract64(pc, 31, 1); + bool notify =3D addr_msb; + bool updiscon =3D !notify; + uint8_t msg_size; + + msg_size =3D rv_etrace_gen_encoded_format2_msg(format2_msg, pc, + notify, + updiscon); + trencoder_send_message_smem(trencoder, format2_msg, msg_size); + + trencoder->updiscon_pending =3D false; +} + void trencoder_set_first_trace_insn(Object *trencoder_obj, uint64_t pc) { TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); @@ -409,6 +425,10 @@ void trencoder_set_first_trace_insn(Object *trencoder_= obj, uint64_t pc) g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; =20 + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + trencoder->first_pc =3D pc; trace_trencoder_first_trace_insn(pc); msg_size =3D rv_etrace_gen_encoded_sync_msg(msg, pc, priv); @@ -426,6 +446,10 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, g_autofree uint8_t *msg =3D g_malloc0(TRACE_MSG_MAX_SIZE); uint8_t msg_size; =20 + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + msg_size =3D rv_etrace_gen_encoded_trap_msg(msg, pc, priv, ecause, is_interrupt, tval); @@ -435,9 +459,22 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, =20 void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc) { + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + + if (trencoder->updiscon_pending) { + trencoder_send_updiscon(trencoder, pc); + } + trencoder_send_sync_msg(trencoder_obj, pc); } =20 +void trencoder_report_updiscon(Object *trencoder_obj) +{ + TraceEncoder *trencoder =3D TRACE_ENCODER(trencoder_obj); + + trencoder->updiscon_pending =3D true; +} + static const Property trencoder_props[] =3D { /* * We need a link to the associated CPU to diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 2bf07c01f6..0c44092ccb 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -36,6 +36,8 @@ struct TraceEncoder { uint32_t regs[TRACE_R_MAX]; RegisterInfo regs_info[TRACE_R_MAX]; =20 + bool updiscon_pending; + bool enabled; bool trace_running; bool trace_next_insn; @@ -51,5 +53,6 @@ void trencoder_trace_trap_insn(Object *trencoder_obj, bool is_interrupt, uint64_t tval); void trencoder_trace_ppccd(Object *trencoder_obj, uint64_t pc); +void trencoder_report_updiscon(Object *trencoder_obj); =20 #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e80320ad16..f27ff319e9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -131,6 +131,7 @@ DEF_HELPER_6(csrrw_i128, tl, env, int, tl, tl, tl, tl) =20 /* Trace helpers (should be put inside ifdef) */ DEF_HELPER_2(trace_insn, void, env, i64) +DEF_HELPER_1(trace_updiscon, void, env) =20 #ifndef CONFIG_USER_ONLY DEF_HELPER_1(sret, tl, env) diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/= insn_trans/trans_privileged.c.inc index 8a62b4cfcd..28089539d5 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -26,6 +26,8 @@ =20 static bool trans_ecall(DisasContext *ctx, arg_ecall *a) { + gen_trace_updiscon(); + /* always generates U-level ECALL, fixed in do_interrupt handler */ generate_exception(ctx, RISCV_EXCP_U_ECALL); return true; @@ -40,6 +42,8 @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) uint32_t ebreak =3D 0; uint32_t post =3D 0; =20 + gen_trace_updiscon(); + /* * The RISC-V semihosting spec specifies the following * three-instruction sequence to flag a semihosting call: @@ -95,6 +99,8 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) { #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { + gen_trace_updiscon(); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_update_pc(ctx, 0); @@ -113,6 +119,8 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY + gen_trace_updiscon(); + decode_save_opc(ctx, 0); translator_io_start(&ctx->base); gen_update_pc(ctx, 0); @@ -129,6 +137,9 @@ static bool trans_mnret(DisasContext *ctx, arg_mnret *a) { #ifndef CONFIG_USER_ONLY REQUIRE_SMRNMI(ctx); + + gen_trace_updiscon(); + decode_save_opc(ctx, 0); gen_helper_mnret(cpu_pc, tcg_env); tcg_gen_exit_tb(NULL, 0); /* no chaining */ diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_tr= ans/trans_rvi.c.inc index 54b9b4f241..ac00cbc802 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -183,6 +183,8 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) } } =20 + gen_trace_updiscon(); + lookup_and_goto_ptr(ctx); =20 if (misaligned) { diff --git a/target/riscv/trace_helper.c b/target/riscv/trace_helper.c index ed84e6f79a..4b2b645f04 100644 --- a/target/riscv/trace_helper.c +++ b/target/riscv/trace_helper.c @@ -28,9 +28,23 @@ void helper_trace_insn(CPURISCVState *env, uint64_t pc) te->trace_next_insn =3D false; } } + +void helper_trace_updiscon(CPURISCVState *env) +{ + RISCVCPU *cpu =3D env_archcpu(env); + TraceEncoder *te =3D TRACE_ENCODER(cpu->trencoder); + + te->updiscon_pending =3D true; + te->trace_next_insn =3D true; +} #else /* #ifndef CONFIG_USER_ONLY */ void helper_trace_insn(CPURISCVState *env, uint64_t pc) { return; } + +void helper_trace_updiscon(CPURISCVState *env) +{ + return; +} #endif /* #ifndef CONFIG_USER_ONLY*/ diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ff288051e3..26c7678cb9 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -617,6 +617,15 @@ static void gen_ctr_jal(DisasContext *ctx, int rd, tar= get_ulong imm) } #endif =20 +static void gen_trace_updiscon(void) +{ + TCGLabel *skip =3D gen_new_label(); + + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_trace_running, 0, skip); + gen_helper_trace_updiscon(tcg_env); + gen_set_label(skip); +} + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { TCGv succ_pc =3D dest_gpr(ctx, rd); --=20 2.51.1