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Tue, 11 Nov 2025 03:48:04 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, Daniel Henrique Barboza Subject: [PATCH v2 09/17] test/qtest: add riscv-trace-test.c Date: Tue, 11 Nov 2025 08:46:48 -0300 Message-ID: <20251111114656.2285048-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.51.1 In-Reply-To: <20251111114656.2285048-1-dbarboza@ventanamicro.com> References: <20251111114656.2285048-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=dbarboza@ventanamicro.com; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1762861861932158501 Content-Type: text/plain; charset="utf-8" Add a simple smoke test for the trace encoder/trace ram sink integration with the RISC-V 'virt' machine. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 2 +- tests/qtest/meson.build | 2 +- tests/qtest/riscv-trace-test.c | 120 +++++++++++++++++++++++++++++++++ 3 files changed, 122 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/riscv-trace-test.c diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 30e89a6c5a..fe49b1eda2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1711,7 +1711,7 @@ static void virt_machine_init(MachineState *machine) hart_count, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_fatal); =20 - if (tcg_enabled()) { + if (tcg_enabled() || qtest_enabled()) { virt_init_socket_trace_hw(s, i); } =20 diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 669d07c06b..07663c4836 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -281,7 +281,7 @@ qtests_s390x =3D \ qtests_riscv32 =3D \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) =20 -qtests_riscv64 =3D ['riscv-csr-test'] + \ +qtests_riscv64 =3D ['riscv-csr-test', 'riscv-trace-test'] + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) =20 qos_test_ss =3D ss.source_set() diff --git a/tests/qtest/riscv-trace-test.c b/tests/qtest/riscv-trace-test.c new file mode 100644 index 0000000000..e442f69286 --- /dev/null +++ b/tests/qtest/riscv-trace-test.c @@ -0,0 +1,120 @@ +/* + * Testcase for RISC-V Trace framework + * + * Copyright (C) 2025 Ventana Micro Systems Inc. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" + +#include "qemu/timer.h" +#include "qemu/bitops.h" +#include "libqtest.h" +#include "hw/registerfields.h" + +/* taken from virt machine memmap */ +#define TE_BASE 0x3020000 +#define TRAM_BASE 0x6000000 + +REG32(TR_TE_CONTROL, 0x0) + FIELD(TR_TE_CONTROL, ACTIVE, 0, 1) + FIELD(TR_TE_CONTROL, ENABLE, 1, 1) + FIELD(TR_TE_CONTROL, INST_TRACING, 2, 1) + +REG32(TR_RAM_START_LOW, 0x010) + FIELD(TR_RAM_START_LOW, ADDR, 0, 32) +REG32(TR_RAM_START_HIGH, 0x014) + FIELD(TR_RAM_START_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_LIMIT_LOW, 0x018) + FIELD(TR_RAM_LIMIT_LOW, ADDR, 0, 32) +REG32(TR_RAM_LIMIT_HIGH, 0x01C) + FIELD(TR_RAM_LIMIT_HIGH, ADDR, 0, 32) + +REG32(TR_RAM_WP_LOW, 0x020) + FIELD(TR_RAM_WP_LOW, WRAP, 0, 1) + FIELD(TR_RAM_WP_LOW, ADDR, 0, 32) +REG32(TR_RAM_WP_HIGH, 0x024) + FIELD(TR_RAM_WP_HIGH, ADDR, 0, 32) + +static uint32_t test_read_te_control(QTestState *qts) +{ + return qtest_readl(qts, TE_BASE + A_TR_TE_CONTROL); +} + +static void test_write_te_control(QTestState *qts, uint32_t val) +{ + qtest_writel(qts, TE_BASE + A_TR_TE_CONTROL, val); +} + +static uint64_t test_read_tram_ramstart(QTestState *qts) +{ + uint64_t reg =3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_START_HIGH); + + reg <<=3D 32; + reg +=3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_START_LOW); + return reg; +} + +static uint64_t test_read_tram_writep(QTestState *qts) +{ + uint64_t reg =3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_WP_HIGH); + + reg <<=3D 32; + reg +=3D qtest_readl(qts, TRAM_BASE + A_TR_RAM_WP_LOW); + return reg; +} + +static void test_trace_simple(void) +{ + QTestState *qts =3D qtest_init("-machine virt -accel tcg"); + double timeout_sec =3D 0.5; + uint64_t reg_tram_start, reg_tram_writep; + uint32_t reg; + + reg =3D test_read_te_control(qts); + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, ACTIVE, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, ACTIVE)); + + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, ENABLE, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, ENABLE)); + + /* + * Verify if RAM Sink write pointer is equal to + * ramstart before start tracing. + */ + reg_tram_start =3D test_read_tram_ramstart(qts); + g_assert(reg_tram_start > 0); + reg_tram_writep =3D test_read_tram_writep(qts); + g_assert(reg_tram_writep =3D=3D reg_tram_start); + + reg =3D FIELD_DP32(reg, TR_TE_CONTROL, INST_TRACING, 1); + test_write_te_control(qts, reg); + reg =3D test_read_te_control(qts); + g_assert(1 =3D=3D FIELD_EX32(reg, TR_TE_CONTROL, INST_TRACING)); + + g_test_timer_start(); + for (;;) { + reg_tram_writep =3D test_read_tram_writep(qts); + if (reg_tram_writep > reg_tram_start) { + break; + } + + g_assert(g_test_timer_elapsed() <=3D timeout_sec); + } + + qtest_quit(qts); +} + +int main(int argc, char *argv[]) +{ + g_test_init(&argc, &argv, NULL); + qtest_add_func("/riscv-trace-test/test-trace-simple", + test_trace_simple); + return g_test_run(); +} --=20 2.51.1