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Tue, 11 Nov 2025 02:28:38 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 01/15] hw/timer: Make frequency configurable Date: Tue, 11 Nov 2025 11:28:22 +0100 Message-ID: <20251111102836.212535-2-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857062611153000 Content-Type: text/plain; charset="utf-8" From: YannickV The a9 global timer and arm mp timers rely on the PERIPHCLK as their clock source. The current implementation does not take that into account. That causes problems for applications assuming other frequencies than 1 GHz. We can now configure frequencies for the a9 global timer and arm mp timer. By allowing these values to be set according to the application's needs, we ensure that the timers behave consistently with the expected system configuration. The SoC configures the device correctly. Information can be found in the Zynq 7000 SoC Technical Reference Manual under Timers. https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: YannickV --- hw/timer/a9gtimer.c | 9 ++++++--- hw/timer/arm_mptimer.c | 15 +++++++++++---- include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 4 files changed, 20 insertions(+), 7 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 9835c35483..090d14c683 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -63,9 +63,9 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerState= *s) static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, - R_CONTROL_PRESCALER_LEN); - - return (prescale + 1) * 10; + R_CONTROL_PRESCALER_LEN) + 1; + uint64_t scaled_prescaler =3D prescale * 10; + return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz); } =20 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s) @@ -374,6 +374,9 @@ static const VMStateDescription vmstate_a9_gtimer =3D { }; =20 static const Property a9_gtimer_properties[] =3D { + /* Default clock-frequency is 1GHz (NANOSECONDS_PER_SECOND) */ + DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz, + NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), }; =20 diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 803dad1e8a..cae07090f9 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -59,9 +59,11 @@ static inline void timerblock_update_irq(TimerBlock *tb) } =20 /* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ -static inline uint32_t timerblock_scale(uint32_t control) +static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { - return (((control >> 8) & 0xff) + 1) * 10; + uint64_t prescale =3D (((control >> 8) & 0xff) + 1); + uint64_t scaled_prescaler =3D prescale * 10; + return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz); } =20 /* Must be called within a ptimer transaction block */ @@ -155,7 +157,7 @@ static void timerblock_write(void *opaque, hwaddr addr, ptimer_stop(tb->timer); } if ((control & 0xff00) !=3D (value & 0xff00)) { - ptimer_set_period(tb->timer, timerblock_scale(value)); + ptimer_set_period(tb->timer, timerblock_scale(tb, value)); } if (value & 1) { uint64_t count =3D ptimer_get_count(tb->timer); @@ -222,7 +224,8 @@ static void timerblock_reset(TimerBlock *tb) ptimer_transaction_begin(tb->timer); ptimer_stop(tb->timer); ptimer_set_limit(tb->timer, 0, 1); - ptimer_set_period(tb->timer, timerblock_scale(0)); + ptimer_set_period(tb->timer, + timerblock_scale(tb, tb->control)); ptimer_transaction_commit(tb->timer); } } @@ -269,6 +272,7 @@ static void arm_mptimer_realize(DeviceState *dev, Error= **errp) */ for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; + tb->freq_hz =3D s->freq_hz; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, @@ -301,6 +305,9 @@ static const VMStateDescription vmstate_arm_mptimer =3D= { }; =20 static const Property arm_mptimer_properties[] =3D { + /* Default clock-frequency is 1GHz (NANOSECONDS_PER_SECOND) */ + DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz, + NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), }; =20 diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 6ae9122e4b..3b63d14927 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -76,6 +76,7 @@ struct A9GTimerState { =20 MemoryRegion iomem; /* static props */ + uint64_t freq_hz; uint32_t num_cpu; =20 QEMUTimer *timer; diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index 65a96e2a0d..da43a3d351 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -31,6 +31,7 @@ typedef struct { uint32_t control; uint32_t status; struct ptimer_state *timer; + uint64_t freq_hz; qemu_irq irq; MemoryRegion iomem; } TimerBlock; @@ -43,6 +44,7 @@ struct ARMMPTimerState { SysBusDevice parent_obj; /*< public >*/ =20 + uint64_t freq_hz; uint32_t num_cpu; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Tue, 11 Nov 2025 02:28:39 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 02/15] hw/timer: Make PERIPHCLK divider configurable Date: Tue, 11 Nov 2025 11:28:23 +0100 Message-ID: <20251111102836.212535-3-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857142668153000 Content-Type: text/plain; charset="utf-8" From: YannickV The A9 global timer and ARM MP timer use PERIPHCLK as their clock source. The frequency of PERIPHCLK is derived by dividing the main clock (CLK) by a configurable divider (must be at least 2). Previously, the PERIPHCLK divider was not configurable, which could lead to unexspected behavior if the application exspected a different PERIPHCLK rate. The property periphclk-divider specifies by which value the main clock is divided to generate PERIPHCLK. This allows flexible configuration of the timer clocks to match application requirements. Information can be found in the Zynq 7000 Soc Technical Reference Manual under Timers. https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM Signed-off-by: YannickV Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/timer/a9gtimer.c | 19 ++++++++++++++++++- hw/timer/arm_mptimer.c | 19 ++++++++++++++++++- include/hw/timer/a9gtimer.h | 1 + include/hw/timer/arm_mptimer.h | 2 ++ 4 files changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 090d14c683..31eb9422f7 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -27,6 +27,7 @@ #include "hw/timer/a9gtimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/timer.h" #include "qemu/bitops.h" #include "qemu/log.h" @@ -62,9 +63,17 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerStat= e *s) =20 static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The a9 global timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to a9 + * gtimer ticks can be calculated like this: + */ uint64_t prescale =3D extract32(s->control, R_CONTROL_PRESCALER_SHIFT, R_CONTROL_PRESCALER_LEN) + 1; - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * s->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz); } =20 @@ -312,6 +321,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error = **errp) sysbus_init_mmio(sbd, &s->iomem); s->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync= , s); =20 + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >=3D 2", + s->periphclk_divider); + return; + } + for (i =3D 0; i < s->num_cpu; i++) { A9GTimerPerCPU *gtb =3D &s->per_cpu[i]; =20 @@ -378,6 +393,8 @@ static const Property a9_gtimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", A9GTimerState, + periphclk_divider, 10), }; =20 static void a9_gtimer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index cae07090f9..a7434cf56a 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -27,6 +27,7 @@ #include "hw/timer/arm_mptimer.h" #include "migration/vmstate.h" #include "qapi/error.h" +#include "qemu/error-report.h" #include "qemu/module.h" #include "hw/core/cpu.h" =20 @@ -61,8 +62,16 @@ static inline void timerblock_update_irq(TimerBlock *tb) /* Return conversion factor from mpcore timer ticks to qemu timer ticks. = */ static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control) { + /* + * Referring to the ARM-Cortex-A9 MPCore TRM + * + * The arm mp timer relies on the PERIPHCLK as its clock source. + * The PERIPHCLK clock period must be configured as a multiple of the + * main clock CLK. The conversion from the qemu clock (1GHz) to arm mp + * timer ticks can be calculated like this: + */ uint64_t prescale =3D (((control >> 8) & 0xff) + 1); - uint64_t scaled_prescaler =3D prescale * 10; + uint64_t scaled_prescaler =3D prescale * tb->periphclk_divider; return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz); } =20 @@ -273,6 +282,12 @@ static void arm_mptimer_realize(DeviceState *dev, Erro= r **errp) for (i =3D 0; i < s->num_cpu; i++) { TimerBlock *tb =3D &s->timerblock[i]; tb->freq_hz =3D s->freq_hz; + if (s->periphclk_divider < 2) { + error_setg(errp, "Invalid periphclk-divider (%lu), must be >= =3D 2", + s->periphclk_divider); + return; + } + tb->periphclk_divider =3D s->periphclk_divider; tb->timer =3D ptimer_init(timerblock_tick, tb, PTIMER_POLICY); sysbus_init_irq(sbd, &tb->irq); memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, @@ -309,6 +324,8 @@ static const Property arm_mptimer_properties[] =3D { DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz, NANOSECONDS_PER_SECOND), DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), + DEFINE_PROP_UINT64("periphclk-divider", ARMMPTimerState, + periphclk_divider, 10), }; =20 static void arm_mptimer_class_init(ObjectClass *klass, void *data) diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h index 3b63d14927..ff9baf1c77 100644 --- a/include/hw/timer/a9gtimer.h +++ b/include/hw/timer/a9gtimer.h @@ -77,6 +77,7 @@ struct A9GTimerState { MemoryRegion iomem; /* static props */ uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; =20 QEMUTimer *timer; diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h index da43a3d351..061934e4b5 100644 --- a/include/hw/timer/arm_mptimer.h +++ b/include/hw/timer/arm_mptimer.h @@ -32,6 +32,7 @@ typedef struct { uint32_t status; struct ptimer_state *timer; uint64_t freq_hz; + uint64_t periphclk_divider; qemu_irq irq; MemoryRegion iomem; } TimerBlock; @@ -45,6 +46,7 @@ struct ARMMPTimerState { /*< public >*/ =20 uint64_t freq_hz; + uint64_t periphclk_divider; uint32_t num_cpu; TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS]; MemoryRegion iomem; --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 11 Nov 2025 02:28:40 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 03/15] hw/dma/zynq-devcfg: Handle bitstream loading via DMA to 0xffffffff Date: Tue, 11 Nov 2025 11:28:24 +0100 Message-ID: <20251111102836.212535-4-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857007643158500 Content-Type: text/plain; charset="utf-8" From: YannickV A DMA transfer to destination address `0xffffffff` should trigger a bitstream load via the PCAP interface. Currently, this case is not intercepted, causing loaders to enter an infinite loop when polling the status register. This commit adds a check for `0xffffffff` as the destination address. If detected, the relevant status register bits (`DMA_DONE`, `DMA_P_DONE`, and `PCFG_DONE`) are set to indicate a successful bitstream load. If the address is different, the DMA transfer proceeds as usual. A successful load is indicated but nothing is actually done. Guests relying on FPGA functions are still known to fail. This feature is required for the integration of the Beckhoff CX7200 model. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 0fd0d23f57..b838c1c0d0 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -247,7 +247,14 @@ static uint64_t r_lock_pre_write(RegisterInfo *reg, ui= nt64_t val) static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); - + if ((s->regs[R_DMA_DST_ADDR]) =3D=3D 0xffffffff) { + DB_PRINT("bitstream loading detected\n"); + s->regs[R_INT_STS] |=3D R_INT_STS_DMA_DONE_MASK | + R_INT_STS_DMA_P_DONE_MASK | + R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); + return; + } s->dma_cmd_fifo[s->dma_cmd_fifo_num] =3D (XlnxZynqDevcfgDMACmd) { .src_addr =3D s->regs[R_DMA_SRC_ADDR] & ~0x3UL, .dest_addr =3D s->regs[R_DMA_DST_ADDR] & ~0x3UL, --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 11 Nov 2025 02:28:41 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 04/15] hw/arm/zynq-devcfg: Prevent unintended unlock during initialization Date: Tue, 11 Nov 2025 11:28:25 +0100 Message-ID: <20251111102836.212535-5-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857088534153000 Content-Type: text/plain; charset="utf-8" From: YannickV During the emulation startup, all registers are reset, which triggers the `r_unlock_post_write` function with a value of 0. This led to an unintended memory access disable, making the devcfg unusable. During startup, the memory space no longer gets locked. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index b838c1c0d0..f28d0015e6 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -221,7 +221,9 @@ static void r_unlock_post_write(RegisterInfo *reg, uint= 64_t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); const char *device_prefix =3D object_get_typename(OBJECT(s)); - + if (device_is_in_reset(DEVICE(s))) { + return; + } if (val =3D=3D R_UNLOCK_MAGIC) { DB_PRINT("successful unlock\n"); s->regs[R_CTRL] |=3D R_CTRL_PCAP_PR_MASK; --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1762857156; 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Tue, 11 Nov 2025 02:28:42 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 05/15] hw/dma/zynq: Ensure PCFG_DONE bit remains set to indicate PL is in user mode Date: Tue, 11 Nov 2025 11:28:26 +0100 Message-ID: <20251111102836.212535-6-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857157914158500 Content-Type: text/plain; charset="utf-8" From: YannickV All register bits are clear on write by writing 1s to those bits, however the register bits will only be cleared if the condition that sets the interrupt flag is no longer true. Since we can assume that programming is always done, the `PCFG_DONE` flag is always set to 1, so it will not never be cleared. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index f28d0015e6..28b3cd2902 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -188,6 +188,8 @@ static void r_ixr_post_write(RegisterInfo *reg, uint64_= t val) { XlnxZynqDevcfg *s =3D XLNX_ZYNQ_DEVCFG(reg->opaque); =20 + s->regs[R_INT_STS] |=3D R_INT_STS_PCFG_DONE_MASK; + xlnx_zynq_devcfg_update_ixr(s); } =20 --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1762857126; cv=none; d=zohomail.com; s=zohoarc; b=ZwTEwwz0t0ascK9dOo2PNuu6HJOb36O0VTGJOcqMkyHgavFNFIhaJ7K52mzq08PLGrO9u54+Q+V9/iPk8nMcO4ttDIA9W86OEEwQ2ZZPWln2dXA8agld+hH1d4JaGcs6mMuug0g8wXjlxpieW5zrZgPkHjAm4HXv/CGNp/ElT2A= ARC-Message-Signature: i=1; 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Tue, 11 Nov 2025 02:28:43 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 06/15] hw/dma/zynq-devcfg: Simulate dummy PL reset Date: Tue, 11 Nov 2025 11:28:27 +0100 Message-ID: <20251111102836.212535-7-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857127454158500 Content-Type: text/plain; charset="utf-8" From: YannickV Setting PCFG_PROG_B should reset the PL. After a reset PCFG_INIT should indicate that the reset is finished successfully. In order to add a MMIO-Device as part of the PL in the Zynq, the reset logic must succeed. The PCFG_INIT flag is now set when the PL reset is triggered by PCFG_PROG_B. Indicating the reset was successful. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 28b3cd2902..53bcf49140 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -49,6 +49,7 @@ =20 REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignor= ed */ + FIELD(CTRL, PCFG_PROG_B, 30, 1) FIELD(CTRL, PCAP_PR, 27, 1) /* Forced to 0 on bad unlo= ck */ FIELD(CTRL, PCAP_MODE, 26, 1) FIELD(CTRL, MULTIBOOT_EN, 24, 1) @@ -116,6 +117,7 @@ REG32(STATUS, 0x14) FIELD(STATUS, PSS_GTS_USR_B, 11, 1) FIELD(STATUS, PSS_FST_CFG_B, 10, 1) FIELD(STATUS, PSS_CFG_RESET_B, 5, 1) + FIELD(STATUS, PCFG_INIT, 4, 1) =20 REG32(DMA_SRC_ADDR, 0x18) REG32(DMA_DST_ADDR, 0x1C) @@ -204,6 +206,13 @@ static uint64_t r_ctrl_pre_write(RegisterInfo *reg, ui= nt64_t val) val |=3D lock_ctrl_map[i] & s->regs[R_CTRL]; } } + + if (FIELD_EX32(val, CTRL, PCFG_PROG_B)) { + s->regs[R_STATUS] |=3D R_STATUS_PCFG_INIT_MASK; + } else { + s->regs[R_STATUS] &=3D ~R_STATUS_PCFG_INIT_MASK; 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Tue, 11 Nov 2025 02:28:44 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 07/15] hw/dma/zynq-devcfg: Indicate power-up status of PL Date: Tue, 11 Nov 2025 11:28:28 +0100 Message-ID: <20251111102836.212535-8-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857218914153000 Content-Type: text/plain; charset="utf-8" From: YannickV It is assumed, that the programmable logic (PL) is always powered during emulation. Therefor the PCFG_POR_B bit in the MCTRL register is set. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/dma/xlnx-zynq-devcfg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 53bcf49140..512a33b066 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -333,7 +333,8 @@ static const RegisterAccessInfo xlnx_zynq_devcfg_regs_i= nfo[] =3D { /* Silicon 3.0 for version field, the mysterious reserved bit 23 * and QEMU platform identifier. */ - .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | R_MCTRL_QEMU= _MASK, + .reset =3D 0x2 << R_MCTRL_PS_VERSION_SHIFT | 1 << 23 | + R_MCTRL_PCFG_POR_B_MASK | R_MCTRL_QEMU_MASK, .ro =3D ~R_MCTRL_INT_PCAP_LPBK_MASK, .rsvd =3D 0x00f00303, }, --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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Tue, 11 Nov 2025 02:28:45 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 08/15] hw/dma/zynq-devcfg: Fix register memory Date: Tue, 11 Nov 2025 11:28:29 +0100 Message-ID: <20251111102836.212535-9-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857176622153000 Content-Type: text/plain; charset="utf-8" From: YannickV Registers are always 32 bit aligned. R_MAX is not the maximum register address, it is the maximum register number. The memory size can be determined by 4 * R_MAX. Currently every register with an offset bigger than 0x40 will be ignored, because the memory size is set wrong. This effects the MCTRL register and makes it useless. This commit restores the correct behaviour. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/dma/xlnx-zynq-devcfg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 512a33b066..abb8c419d9 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -393,7 +393,7 @@ static void xlnx_zynq_devcfg_init(Object *obj) s->regs_info, s->regs, &xlnx_zynq_devcfg_reg_ops, XLNX_ZYNQ_DEVCFG_ERR_DEBUG, - XLNX_ZYNQ_DEVCFG_R_MAX); + XLNX_ZYNQ_DEVCFG_R_MAX * 4); memory_region_add_subregion(&s->iomem, A_CTRL, ®_array->mem); --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1762857134; cv=none; d=zohomail.com; s=zohoarc; b=iMHrEYU1mF1ktUEq/NmxUrXkng3NE6mUONOW8cEdO1LCTZPMnwsr6kqSLCbxjnWtCgCWkOi+n4lwrlWZfUhOdxNQQtmkdfgvF3y76EBL6ThLG+1+RtQfvHgFX0H2YixBz/FMsvSJjZxU1xf49OugyOpPC27VDWr0mgxnzx8mlTk= ARC-Message-Signature: i=1; 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Tue, 11 Nov 2025 02:28:46 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 09/15] hw/misc: Add dummy ZYNQ DDR controller Date: Tue, 11 Nov 2025 11:28:30 +0100 Message-ID: <20251111102836.212535-10-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=corvin.koehne@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857135589158500 Content-Type: text/plain; charset="utf-8" From: YannickV A dummy DDR controller for ZYNQ has been added. While all registers are pre= sent, not all are functional. Read and write access is validated, and the user mo= de can be set. This provides a basic DDR controller initialization, preventing system hangs due to endless polling or similar issues. Signed-off-by: YannickV --- hw/misc/Kconfig | 3 + hw/misc/meson.build | 1 + hw/misc/xlnx-zynq-ddrc.c | 413 +++++++++++++++++++++++++++++++ include/hw/misc/xlnx-zynq-ddrc.h | 148 +++++++++++ 4 files changed, 565 insertions(+) create mode 100644 hw/misc/xlnx-zynq-ddrc.c create mode 100644 include/hw/misc/xlnx-zynq-ddrc.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 8f9ce2f68c..99548e146f 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -220,4 +220,7 @@ config IOSB config XLNX_VERSAL_TRNG bool =20 +config XLNX_ZYNQ_DDRC + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 55f493521b..6ee7b6c71d 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -89,6 +89,7 @@ system_ss.add(when: 'CONFIG_RASPI', if_true: files( )) system_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) +system_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xlnx-zynq-ddrc.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= crf.c')) system_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-= apu-ctrl.c')) system_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( diff --git a/hw/misc/xlnx-zynq-ddrc.c b/hw/misc/xlnx-zynq-ddrc.c new file mode 100644 index 0000000000..13d64329c3 --- /dev/null +++ b/hw/misc/xlnx-zynq-ddrc.c @@ -0,0 +1,413 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/registerfields.h" +#include "system/block-backend.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "system/dma.h" +#include "hw/misc/xlnx-zynq-ddrc.h" +#include "migration/vmstate.h" + +#ifndef DDRCTRL_ERR_DEBUG +#define DDRCTRL_ERR_DEBUG 0 +#endif + +static void zynq_ddrctrl_post_write(RegisterInfo *reg, uint64_t val) +{ + DDRCTRLState *s =3D DDRCTRL(reg->opaque); + if (reg->access->addr =3D=3D A_DDRC_CTRL) { + if (val & 0x1) { + s->reg[R_MODE_STS_REG] |=3D + (R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK & 0x1); + } else { + s->reg[R_MODE_STS_REG] &=3D + ~R_MODE_STS_REG_DDR_REG_OPERATING_MODE_MASK; + } + } +} + +static const RegisterAccessInfo xlnx_zynq_ddrc_regs_info[] =3D { + /* 0x00 - 0x3C: Basic DDRC control and config */ + { .name =3D "DDRC_CTRL", + .addr =3D A_DDRC_CTRL, + .reset =3D 0x00000200, + .post_write =3D zynq_ddrctrl_post_write }, + { .name =3D "TWO_RANK_CFG", + .addr =3D A_TWO_RANK_CFG, + .reset =3D 0x000C1076 }, + { .name =3D "HPR_REG", + .addr =3D A_HPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "LPR_REG", + .addr =3D A_LPR_REG, + .reset =3D 0x03C0780F }, + { .name =3D "WR_REG", + .addr =3D A_WR_REG, + .reset =3D 0x0007F80F }, + { .name =3D "DRAM_PARAM_REG0", + .addr =3D A_DRAM_PARAM_REG0, + .reset =3D 0x00041016 }, + { .name =3D "DRAM_PARAM_REG1", + .addr =3D A_DRAM_PARAM_REG1, + .reset =3D 0x351B48D9 }, + { .name =3D "DRAM_PARAM_REG2", + .addr =3D A_DRAM_PARAM_REG2, + .reset =3D 0x83015904 }, + { .name =3D "DRAM_PARAM_REG3", + .addr =3D A_DRAM_PARAM_REG3, + .reset =3D 0x250882D0 }, + { .name =3D "DRAM_PARAM_REG4", + .addr =3D A_DRAM_PARAM_REG4, + .reset =3D 0x0000003C }, + { .name =3D "DRAM_INIT_PARAM", + .addr =3D A_DRAM_INIT_PARAM, + .reset =3D 0x00002007 }, + { .name =3D "DRAM_EMR_REG", + .addr =3D A_DRAM_EMR_REG, + .reset =3D 0x00000008 }, + { .name =3D "DRAM_EMR_MR_REG", + .addr =3D A_DRAM_EMR_MR_REG, + .reset =3D 0x00000940 }, + { .name =3D "DRAM_BURST8_RDWR", + .addr =3D A_DRAM_BURST8_RDWR, + .reset =3D 0x00020034 }, + { .name =3D "DRAM_DISABLE_DQ", + .addr =3D A_DRAM_DISABLE_DQ }, + { .name =3D "DRAM_ADDR_MAP_BANK", + .addr =3D A_DRAM_ADDR_MAP_BANK, + .reset =3D 0x00000F77 }, + { .name =3D "DRAM_ADDR_MAP_COL", + .addr =3D A_DRAM_ADDR_MAP_COL, + .reset =3D 0xFFF00000 }, + { .name =3D "DRAM_ADDR_MAP_ROW", + .addr =3D A_DRAM_ADDR_MAP_ROW, + .reset =3D 0x0FF55555 }, + { .name =3D "DRAM_ODT_REG", + .addr =3D A_DRAM_ODT_REG, + .reset =3D 0x00000249 }, + + /* 0x4C - 0x5C: PHY and DLL */ + { .name =3D "PHY_DBG_REG", + .addr =3D A_PHY_DBG_REG }, + { .name =3D "PHY_CMD_TIMEOUT_RDDATA_CPT", + .addr =3D A_PHY_CMD_TIMEOUT_RDDATA_CPT, + .reset =3D 0x00010200 }, + { .name =3D "MODE_STS_REG", + .addr =3D A_MODE_STS_REG }, + { .name =3D "DLL_CALIB", + .addr =3D A_DLL_CALIB, + .reset =3D 0x00000101 }, + { .name =3D "ODT_DELAY_HOLD", + .addr =3D A_ODT_DELAY_HOLD, + .reset =3D 0x00000023 }, + + /* 0x60 - 0x7C: Control registers */ + { .name =3D "CTRL_REG1", + .addr =3D A_CTRL_REG1, + .reset =3D 0x0000003E }, + { .name =3D "CTRL_REG2", + .addr =3D A_CTRL_REG2, + .reset =3D 0x00020000 }, + { .name =3D "CTRL_REG3", + .addr =3D A_CTRL_REG3, + .reset =3D 0x00284027 }, + { .name =3D "CTRL_REG4", + .addr =3D A_CTRL_REG4, + .reset =3D 0x00001610 }, + { .name =3D "CTRL_REG5", + .addr =3D A_CTRL_REG5, + .reset =3D 0x00455111 }, + { .name =3D "CTRL_REG6", + .addr =3D A_CTRL_REG6, + .reset =3D 0x00032222 }, + + /* 0xA0 - 0xB4: Refresh, ZQ, powerdown, misc */ + { .name =3D "CHE_REFRESH_TIMER0", + .addr =3D A_CHE_REFRESH_TIMER0, + .reset =3D 0x00008000 }, + { .name =3D "CHE_T_ZQ", + .addr =3D A_CHE_T_ZQ, + .reset =3D 0x10300802 }, + { .name =3D "CHE_T_ZQ_SHORT_INTERVAL_REG", + .addr =3D A_CHE_T_ZQ_SHORT_INTERVAL_REG, + .reset =3D 0x0020003A }, + { .name =3D "DEEP_PWRDWN_REG", + .addr =3D A_DEEP_PWRDWN_REG }, + { .name =3D "REG_2C", + .addr =3D A_REG_2C }, + { .name =3D "REG_2D", + .addr =3D A_REG_2D, + .reset =3D 0x00000200 }, + + /* 0xB8 - 0xF8: ECC, DFI, etc. */ + { .name =3D "DFI_TIMING", + .addr =3D A_DFI_TIMING, + .reset =3D 0x00200067 }, + { .name =3D "CHE_ECC_CONTROL_REG_OFFSET", + .addr =3D A_CHE_ECC_CONTROL_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_CORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_CORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_LOG_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_LOG_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_ADDR_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_ADDR_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET }, + { .name =3D "CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET", + .addr =3D A_CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET }, + { .name =3D "CHE_ECC_STATS_REG_OFFSET", + .addr =3D A_CHE_ECC_STATS_REG_OFFSET }, + { .name =3D "ECC_SCRUB", + .addr =3D A_ECC_SCRUB, + .reset =3D 0x00000008 }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET }, + { .name =3D "CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET", + .addr =3D A_CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET }, + + /* 0x114 - 0x174: PHY config, ratios, DQS, WE */ + { .name =3D "PHY_RCVER_ENABLE", + .addr =3D A_PHY_RCVER_ENABLE }, + { .name =3D "PHY_CONFIG0", + .addr =3D A_PHY_CONFIG0, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG1", + .addr =3D A_PHY_CONFIG1, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG2", + .addr =3D A_PHY_CONFIG2, + .reset =3D 0x40000001 }, + { .name =3D "PHY_CONFIG3", + .addr =3D A_PHY_CONFIG3, + .reset =3D 0x40000001 }, + { .name =3D "PHY_INIT_RATIO0", + .addr =3D A_PHY_INIT_RATIO0 }, + { .name =3D "PHY_INIT_RATIO1", + .addr =3D A_PHY_INIT_RATIO1 }, + { .name =3D "PHY_INIT_RATIO2", + .addr =3D A_PHY_INIT_RATIO2 }, + { .name =3D "PHY_INIT_RATIO3", + .addr =3D A_PHY_INIT_RATIO3 }, + { .name =3D "PHY_RD_DQS_CFG0", + .addr =3D A_PHY_RD_DQS_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG1", + .addr =3D A_PHY_RD_DQS_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG2", + .addr =3D A_PHY_RD_DQS_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_RD_DQS_CFG3", + .addr =3D A_PHY_RD_DQS_CFG3, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WR_DQS_CFG0", + .addr =3D A_PHY_WR_DQS_CFG0 }, + { .name =3D "PHY_WR_DQS_CFG1", + .addr =3D A_PHY_WR_DQS_CFG1 }, + { .name =3D "PHY_WR_DQS_CFG2", + .addr =3D A_PHY_WR_DQS_CFG2 }, + { .name =3D "PHY_WR_DQS_CFG3", + .addr =3D A_PHY_WR_DQS_CFG3 }, + { .name =3D "PHY_WE_CFG0", + .addr =3D A_PHY_WE_CFG0, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG1", + .addr =3D A_PHY_WE_CFG1, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG2", + .addr =3D A_PHY_WE_CFG2, + .reset =3D 0x00000040 }, + { .name =3D "PHY_WE_CFG3", + .addr =3D A_PHY_WE_CFG3, + .reset =3D 0x00000040 }, + + /* 0x17C - 0x194: Write data slaves, misc */ + { .name =3D "WR_DATA_SLV0", + .addr =3D A_WR_DATA_SLV0, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV1", + .addr =3D A_WR_DATA_SLV1, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV2", + .addr =3D A_WR_DATA_SLV2, + .reset =3D 0x00000080 }, + { .name =3D "WR_DATA_SLV3", + .addr =3D A_WR_DATA_SLV3, + .reset =3D 0x00000080 }, + { .name =3D "REG_64", + .addr =3D A_REG_64, + .reset =3D 0x10020000 }, + { .name =3D "REG_65", + .addr =3D A_REG_65 }, + + /* 0x1A4 - 0x1C4: Misc registers */ + { .name =3D "REG69_6A0", + .addr =3D A_REG69_6A0 }, + { .name =3D "REG69_6A1", + .addr =3D A_REG69_6A1 }, + { .name =3D "REG6C_6D2", + .addr =3D A_REG6C_6D2 }, + { .name =3D "REG6C_6D3", + .addr =3D A_REG6C_6D3 }, + { .name =3D "REG6E_710", + .addr =3D A_REG6E_710 }, + { .name =3D "REG6E_711", + .addr =3D A_REG6E_711 }, + { .name =3D "REG6E_712", + .addr =3D A_REG6E_712 }, + { .name =3D "REG6E_713", + .addr =3D A_REG6E_713 }, + + /* 0x1CC - 0x1E8: DLL, PHY status */ + { .name =3D "PHY_DLL_STS0", + .addr =3D A_PHY_DLL_STS0 }, + { .name =3D "PHY_DLL_STS1", + .addr =3D A_PHY_DLL_STS1 }, + { .name =3D "PHY_DLL_STS2", + .addr =3D A_PHY_DLL_STS2 }, + { .name =3D "PHY_DLL_STS3", + .addr =3D A_PHY_DLL_STS3 }, + { .name =3D "DLL_LOCK_STS", + .addr =3D A_DLL_LOCK_STS }, + { .name =3D "PHY_CTRL_STS", + .addr =3D A_PHY_CTRL_STS }, + { .name =3D "PHY_CTRL_STS_REG2", + .addr =3D A_PHY_CTRL_STS_REG2 }, + + /* 0x200 - 0x2B4: AXI, LPDDR, misc */ + { .name =3D "AXI_ID", + .addr =3D A_AXI_ID }, + { .name =3D "PAGE_MASK", + .addr =3D A_PAGE_MASK }, + { .name =3D "AXI_PRIORITY_WR_PORT0", + .addr =3D A_AXI_PRIORITY_WR_PORT0, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT1", + .addr =3D A_AXI_PRIORITY_WR_PORT1, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT2", + .addr =3D A_AXI_PRIORITY_WR_PORT2, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_WR_PORT3", + .addr =3D A_AXI_PRIORITY_WR_PORT3, + .reset =3D 0x000803FF }, + { .name =3D "AXI_PRIORITY_RD_PORT0", + .addr =3D A_AXI_PRIORITY_RD_PORT0, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT1", + .addr =3D A_AXI_PRIORITY_RD_PORT1, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT2", + .addr =3D A_AXI_PRIORITY_RD_PORT2, + .reset =3D 0x000003FF }, + { .name =3D "AXI_PRIORITY_RD_PORT3", + .addr =3D A_AXI_PRIORITY_RD_PORT3, + .reset =3D 0x000003FF }, + { .name =3D "EXCL_ACCESS_CFG0", + .addr =3D A_EXCL_ACCESS_CFG0 }, + { .name =3D "EXCL_ACCESS_CFG1", + .addr =3D A_EXCL_ACCESS_CFG1 }, + { .name =3D "EXCL_ACCESS_CFG2", + .addr =3D A_EXCL_ACCESS_CFG2 }, + { .name =3D "EXCL_ACCESS_CFG3", + .addr =3D A_EXCL_ACCESS_CFG3 }, + { .name =3D "MODE_REG_READ", + .addr =3D A_MODE_REG_READ }, + { .name =3D "LPDDR_CTRL0", + .addr =3D A_LPDDR_CTRL0 }, + { .name =3D "LPDDR_CTRL1", + .addr =3D A_LPDDR_CTRL1 }, + { .name =3D "LPDDR_CTRL2", + .addr =3D A_LPDDR_CTRL2, + .reset =3D 0x003C0015 }, + { .name =3D "LPDDR_CTRL3", + .addr =3D A_LPDDR_CTRL3, + .reset =3D 0x00000601 }, +}; + +static void zynq_ddrctrl_reset(DeviceState *dev) +{ + DDRCTRLState *s =3D DDRCTRL(dev); + int i; + + for (i =3D 0; i < ZYNQ_DDRCTRL_NUM_REG; ++i) { + register_reset(&s->regs_info[i]); + } +} + +static const MemoryRegionOps ddrctrl_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const VMStateDescription vmstate_zynq_ddrctrl =3D { + .name =3D "zynq_ddrc", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT32_ARRAY(reg, DDRCTRLState, ZYNQ_DDRCTRL_NUM_REG), + VMSTATE_END_OF_LIST() + } +}; + +static void zynq_ddrctrl_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + DDRCTRLState *s =3D DDRCTRL(obj); + + s->reg_array =3D + register_init_block32(DEVICE(obj), xlnx_zynq_ddrc_regs_info, + ARRAY_SIZE(xlnx_zynq_ddrc_regs_info), + s->regs_info, s->reg, + &ddrctrl_ops, + DDRCTRL_ERR_DEBUG, + ZYNQ_DDRCTRL_MMIO_SIZE); + + sysbus_init_mmio(sbd, &s->reg_array->mem); +} + +static void zynq_ddrctrl_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_legacy_reset(dc, zynq_ddrctrl_reset); + dc->vmsd =3D &vmstate_zynq_ddrctrl; +} + +static const TypeInfo ddrctrl_info =3D { + .name =3D TYPE_DDRCTRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DDRCTRLState), + .instance_init =3D zynq_ddrctrl_init, + .class_init =3D zynq_ddrctrl_class_init, +}; + +static void ddrctrl_register_types(void) +{ + type_register_static(&ddrctrl_info); +} + +type_init(ddrctrl_register_types) diff --git a/include/hw/misc/xlnx-zynq-ddrc.h b/include/hw/misc/xlnx-zynq-d= drc.h new file mode 100644 index 0000000000..3d45a02176 --- /dev/null +++ b/include/hw/misc/xlnx-zynq-ddrc.h @@ -0,0 +1,148 @@ +/* + * QEMU model of the Xilinx Zynq Double Data Rate Controller + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef XLNX_ZYNQ_DDRC_H +#define XLNX_ZYNQ_DDRC_H + +#include "hw/sysbus.h" +#include "hw/register.h" + +#define TYPE_DDRCTRL "zynq.ddr-ctlr" +#define DDRCTRL(obj) \ + OBJECT_CHECK(DDRCTRLState, (obj), TYPE_DDRCTRL) + +REG32(DDRC_CTRL, 0x00) +REG32(TWO_RANK_CFG, 0x04) +REG32(HPR_REG, 0x08) +REG32(LPR_REG, 0x0C) +REG32(WR_REG, 0x10) +REG32(DRAM_PARAM_REG0, 0x14) +REG32(DRAM_PARAM_REG1, 0x18) +REG32(DRAM_PARAM_REG2, 0x1C) +REG32(DRAM_PARAM_REG3, 0x20) +REG32(DRAM_PARAM_REG4, 0x24) +REG32(DRAM_INIT_PARAM, 0x28) +REG32(DRAM_EMR_REG, 0x2C) +REG32(DRAM_EMR_MR_REG, 0x30) +REG32(DRAM_BURST8_RDWR, 0x34) +REG32(DRAM_DISABLE_DQ, 0x38) +REG32(DRAM_ADDR_MAP_BANK, 0x3C) +REG32(DRAM_ADDR_MAP_COL, 0x40) +REG32(DRAM_ADDR_MAP_ROW, 0x44) +REG32(DRAM_ODT_REG, 0x48) +REG32(PHY_DBG_REG, 0x4C) +REG32(PHY_CMD_TIMEOUT_RDDATA_CPT, 0x50) +REG32(MODE_STS_REG, 0x54) + FIELD(MODE_STS_REG, DDR_REG_DBG_STALL, 3, 3) + FIELD(MODE_STS_REG, DDR_REG_OPERATING_MODE, 0, 2) +REG32(DLL_CALIB, 0x58) +REG32(ODT_DELAY_HOLD, 0x5C) +REG32(CTRL_REG1, 0x60) +REG32(CTRL_REG2, 0x64) +REG32(CTRL_REG3, 0x68) +REG32(CTRL_REG4, 0x6C) +REG32(CTRL_REG5, 0x78) +REG32(CTRL_REG6, 0x7C) +REG32(CHE_REFRESH_TIMER0, 0xA0) +REG32(CHE_T_ZQ, 0xA4) +REG32(CHE_T_ZQ_SHORT_INTERVAL_REG, 0xA8) +REG32(DEEP_PWRDWN_REG, 0xAC) +REG32(REG_2C, 0xB0) +REG32(REG_2D, 0xB4) +REG32(DFI_TIMING, 0xB8) +REG32(CHE_ECC_CONTROL_REG_OFFSET, 0xC4) +REG32(CHE_CORR_ECC_LOG_REG_OFFSET, 0xC8) +REG32(CHE_CORR_ECC_ADDR_REG_OFFSET, 0xCC) +REG32(CHE_CORR_ECC_DATA_31_0_REG_OFFSET, 0xD0) +REG32(CHE_CORR_ECC_DATA_63_32_REG_OFFSET, 0xD4) +REG32(CHE_CORR_ECC_DATA_71_64_REG_OFFSET, 0xD8) +REG32(CHE_UNCORR_ECC_LOG_REG_OFFSET, 0xDC) +REG32(CHE_UNCORR_ECC_ADDR_REG_OFFSET, 0xE0) +REG32(CHE_UNCORR_ECC_DATA_31_0_REG_OFFSET, 0xE4) +REG32(CHE_UNCORR_ECC_DATA_63_32_REG_OFFSET, 0xE8) +REG32(CHE_UNCORR_ECC_DATA_71_64_REG_OFFSET, 0xEC) +REG32(CHE_ECC_STATS_REG_OFFSET, 0xF0) +REG32(ECC_SCRUB, 0xF4) +REG32(CHE_ECC_CORR_BIT_MASK_31_0_REG_OFFSET, 0xF8) +REG32(CHE_ECC_CORR_BIT_MASK_63_32_REG_OFFSET, 0xFC) +REG32(PHY_RCVER_ENABLE, 0x114) +REG32(PHY_CONFIG0, 0x118) +REG32(PHY_CONFIG1, 0x11C) +REG32(PHY_CONFIG2, 0x120) +REG32(PHY_CONFIG3, 0x124) +REG32(PHY_INIT_RATIO0, 0x12C) +REG32(PHY_INIT_RATIO1, 0x130) +REG32(PHY_INIT_RATIO2, 0x134) +REG32(PHY_INIT_RATIO3, 0x138) +REG32(PHY_RD_DQS_CFG0, 0x140) +REG32(PHY_RD_DQS_CFG1, 0x144) +REG32(PHY_RD_DQS_CFG2, 0x148) +REG32(PHY_RD_DQS_CFG3, 0x14C) +REG32(PHY_WR_DQS_CFG0, 0x154) +REG32(PHY_WR_DQS_CFG1, 0x158) +REG32(PHY_WR_DQS_CFG2, 0x15C) +REG32(PHY_WR_DQS_CFG3, 0x160) +REG32(PHY_WE_CFG0, 0x168) +REG32(PHY_WE_CFG1, 0x16C) +REG32(PHY_WE_CFG2, 0x170) +REG32(PHY_WE_CFG3, 0x174) +REG32(WR_DATA_SLV0, 0x17C) +REG32(WR_DATA_SLV1, 0x180) +REG32(WR_DATA_SLV2, 0x184) +REG32(WR_DATA_SLV3, 0x188) +REG32(REG_64, 0x190) +REG32(REG_65, 0x194) +REG32(REG69_6A0, 0x1A4) +REG32(REG69_6A1, 0x1A8) +REG32(REG6C_6D2, 0x1B0) +REG32(REG6C_6D3, 0x1B4) +REG32(REG6E_710, 0x1B8) +REG32(REG6E_711, 0x1BC) +REG32(REG6E_712, 0x1C0) +REG32(REG6E_713, 0x1C4) +REG32(PHY_DLL_STS0, 0x1CC) +REG32(PHY_DLL_STS1, 0x1D0) +REG32(PHY_DLL_STS2, 0x1D4) +REG32(PHY_DLL_STS3, 0x1D8) +REG32(DLL_LOCK_STS, 0x1E0) +REG32(PHY_CTRL_STS, 0x1E4) +REG32(PHY_CTRL_STS_REG2, 0x1E8) +REG32(AXI_ID, 0x200) +REG32(PAGE_MASK, 0x204) +REG32(AXI_PRIORITY_WR_PORT0, 0x208) +REG32(AXI_PRIORITY_WR_PORT1, 0x20C) +REG32(AXI_PRIORITY_WR_PORT2, 0x210) +REG32(AXI_PRIORITY_WR_PORT3, 0x214) +REG32(AXI_PRIORITY_RD_PORT0, 0x218) +REG32(AXI_PRIORITY_RD_PORT1, 0x21C) +REG32(AXI_PRIORITY_RD_PORT2, 0x220) +REG32(AXI_PRIORITY_RD_PORT3, 0x224) +REG32(EXCL_ACCESS_CFG0, 0x294) +REG32(EXCL_ACCESS_CFG1, 0x298) +REG32(EXCL_ACCESS_CFG2, 0x29C) +REG32(EXCL_ACCESS_CFG3, 0x2A0) +REG32(MODE_REG_READ, 0x2A4) +REG32(LPDDR_CTRL0, 0x2A8) +REG32(LPDDR_CTRL1, 0x2AC) +REG32(LPDDR_CTRL2, 0x2B0) +REG32(LPDDR_CTRL3, 0x2B4) + + +#define ZYNQ_DDRCTRL_MMIO_SIZE 0x400 +#define ZYNQ_DDRCTRL_NUM_REG (ZYNQ_DDRCTRL_MMIO_SIZE / 4) + +typedef struct DDRCTRLState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + RegisterInfoArray *reg_array; + uint32_t reg[ZYNQ_DDRCTRL_NUM_REG]; + RegisterInfo regs_info[ZYNQ_DDRCTRL_NUM_REG]; +} DDRCTRLState; +#endif --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1762857105; cv=none; d=zohomail.com; s=zohoarc; b=WQy4zaR3Zx2asK+IISJ65zDzrQur/YsDwV2431mnKBDLwMZxW51gjayj5ByYpB8yPp3r9HuU9Rm3zpcXOVO4TgtGoh70WSZKtPr9PZF4rGaeHfkqI0pwYuqdF4LqL38ME+i5VUBE92S8D7/0BjlS8wtshVa+iJbzJq9XLKxtO6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762857105; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 11 Nov 2025 02:28:47 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV , "Edgar E. Iglesias" Subject: [PATCH v4 10/15] hw/misc/zynq_slcr: Add logic for DCI configuration Date: Tue, 11 Nov 2025 11:28:31 +0100 Message-ID: <20251111102836.212535-11-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857108519153000 Content-Type: text/plain; charset="utf-8" From: YannickV The registers for the digitally controlled impedance (DCI) clock are part of the system level control registers (SLCR). The DONE bit in the status register indicates a successfull DCI calibration. An description of the calibration process can be found here: https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/DDR-IOB-Impedance-Cali= bration The DCI control register and status register have been added. As soon as the ENABLE and RESET bit are set, the RESET bit has also been toggled to 0 before and the UPDATE_CONTROL is not set, the DONE bit in the status register is set. If these bits change the DONE bit is reset. Note that the option bits are not taken into consideration. Signed-off-by: YannickV Reviewed-by: Edgar E. Iglesias --- hw/misc/zynq_slcr.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index a766bab182..d7a2994f47 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -180,6 +180,12 @@ REG32(GPIOB_CFG_HSTL, 0xb14) REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18) =20 REG32(DDRIOB, 0xb40) +REG32(DDRIOB_DCI_CTRL, 0xb70) + FIELD(DDRIOB_DCI_CTRL, RESET, 0, 1) + FIELD(DDRIOB_DCI_CTRL, ENABLE, 1, 1) + FIELD(DDRIOB_DCI_CTRL, UPDATE_CONTROL, 20, 1) +REG32(DDRIOB_DCI_STATUS, 0xb74) + FIELD(DDRIOB_DCI_STATUS, DONE, 13, 1) #define DDRIOB_LENGTH 14 =20 #define ZYNQ_SLCR_MMIO_SIZE 0x1000 @@ -193,6 +199,8 @@ struct ZynqSLCRState { =20 MemoryRegion iomem; =20 + bool ddriob_dci_ctrl_reset_toggled; + uint32_t regs[ZYNQ_SLCR_NUM_REGS]; =20 Clock *ps_clk; @@ -331,6 +339,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) =20 DB_PRINT("RESET\n"); =20 + s->ddriob_dci_ctrl_reset_toggled =3D false; + s->regs[R_LOCKSTA] =3D 1; /* 0x100 - 0x11C */ s->regs[R_ARM_PLL_CTRL] =3D 0x0001A008; @@ -418,6 +428,8 @@ static void zynq_slcr_reset_init(Object *obj, ResetType= type) s->regs[R_DDRIOB + 4] =3D s->regs[R_DDRIOB + 5] =3D s->regs[R_DDRIOB += 6] =3D 0x00000e00; s->regs[R_DDRIOB + 12] =3D 0x00000021; + + s->regs[R_DDRIOB_DCI_CTRL] =3D 0x00000020; } =20 static void zynq_slcr_reset_hold(Object *obj, ResetType type) @@ -554,6 +566,25 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, (int)offset, (unsigned)val & 0xFFFF); } return; + + case R_DDRIOB_DCI_CTRL: + if (!FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + FIELD_EX32(s->regs[R_DDRIOB_DCI_CTRL], DDRIOB_DCI_CTRL, RESET)= ) { + + s->ddriob_dci_ctrl_reset_toggled =3D true; + DB_PRINT("DDRIOB DCI CTRL RESET was toggled\n"); + } + + if (FIELD_EX32(val, DDRIOB_DCI_CTRL, ENABLE) && + FIELD_EX32(val, DDRIOB_DCI_CTRL, RESET) && + !FIELD_EX32(val, DDRIOB_DCI_CTRL, UPDATE_CONTROL) && + s->ddriob_dci_ctrl_reset_toggled) { + + s->regs[R_DDRIOB_DCI_STATUS] |=3D R_DDRIOB_DCI_STATUS_DONE_MAS= K; + } else { + s->regs[R_DDRIOB_DCI_STATUS] &=3D ~R_DDRIOB_DCI_STATUS_DONE_MA= SK; + } + break; } =20 if (s->regs[R_LOCKSTA]) { --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1762857030; cv=none; d=zohomail.com; s=zohoarc; b=PckvjAkEsnJ61SmAGjrKQCJMvIL4Jo3mloTC3myQsLTh+6brx4et0yHhIT3S7o6WneMA5nbO5Nfr7o9eiUOvpzfiCTh8kaZEQrjCQ4ZzkKIUcVZP40rO+k9RNgquI4UMgdsd/aCaAE46ENvUwV9Z1cZ033OKwybryruyoyqYY98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762857030; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Tue, 11 Nov 2025 02:28:47 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 11/15] hw/misc: Add Beckhoff CCAT device Date: Tue, 11 Nov 2025 11:28:32 +0100 Message-ID: <20251111102836.212535-12-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857032191158500 Content-Type: text/plain; charset="utf-8" From: YannickV This adds the Beckhoff Communication Controller (CCAT). The information block, EEPROM interface and DMA controller are currently implemented. The EEPROM provides production information for Beckhoff Devices. An EEPORM binary must therefor be handed over. It should be aligned to a power of two. If no EEPROM binary is handed over an empty EEPROM of size 4096 is initialized. This device is needed for the Beckhoff CX7200 board emulation. Signed-off-by: YannickV --- hw/misc/Kconfig | 3 + hw/misc/beckhoff_ccat.c | 338 ++++++++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 342 insertions(+) create mode 100644 hw/misc/beckhoff_ccat.c diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 99548e146f..f3a2efa350 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -223,4 +223,7 @@ config XLNX_VERSAL_TRNG config XLNX_ZYNQ_DDRC bool =20 +config BECKHOFF_CCAT + bool + source macio/Kconfig diff --git a/hw/misc/beckhoff_ccat.c b/hw/misc/beckhoff_ccat.c new file mode 100644 index 0000000000..cba570e767 --- /dev/null +++ b/hw/misc/beckhoff_ccat.c @@ -0,0 +1,338 @@ +/* + * Beckhoff Communication Controller Emulation + * + * Copyright (c) Beckhoff Automation GmbH. & Co. KG + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "system/block-backend.h" +#include "exec/address-spaces.h" +#include "exec/memory.h" +#include "system/dma.h" +#include "qemu/error-report.h" +#include "block/block.h" +#include "block/block_int.h" +#include "block/qdict.h" +#include "hw/block/block.h" +#include "migration/vmstate.h" +#include "qemu/bswap.h" + +#ifndef CCAT_ERR_DEBUG +#define CCAT_ERR_DEBUG 0 +#endif + +#define TYPE_BECKHOFF_CCAT "beckhoff-ccat" +OBJECT_DECLARE_SIMPLE_TYPE(BeckhoffCcat, BECKHOFF_CCAT) + +#define MAX_NUM_SLOTS 32 +#define CCAT_FUNCTION_BLOCK_SIZE 16 + +#define CCAT_EEPROM_OFFSET 0x100 +#define CCAT_DMA_OFFSET 0x8000 + +#define CCAT_MEM_SIZE 0xFFFF +#define CCAT_DMA_SIZE 0x800 +#define CCAT_EEPROM_SIZE 0x20 + +#define EEPROM_MEMORY_SIZE 0x1000 + +#define EEPROM_CMD_OFFSET (CCAT_EEPROM_OFFSET + 0x00) + #define EEPROM_CMD_WRITE_MASK 0x2 + #define EEPROM_CMD_READ_MASK 0x1 +#define EEPROM_ADR_OFFSET (CCAT_EEPROM_OFFSET + 0x04) +#define EEPROM_DATA_OFFSET (CCAT_EEPROM_OFFSET + 0x08) + +#define DMA_BUFFER_OFFSET (CCAT_DMA_OFFSET + 0x00) +#define DMA_DIRECTION_OFFSET (CCAT_DMA_OFFSET + 0x7c0) + #define DMA_DIRECTION_MASK 1 +#define DMA_TRANSFER_OFFSET (CCAT_DMA_OFFSET + 0x7c4) +#define DMA_HOST_ADR_OFFSET (CCAT_DMA_OFFSET + 0x7c8) +#define DMA_TRANSFER_LENGTH_OFFSET (CCAT_DMA_OFFSET + 0x7cc) + +/* + * The informationblock is always located at address 0x0. + * Address and size are therefor replaced by two identifiers. + * The Parameter give information about the maximal number of + * function slots and the creation date (in this case 01.01.2001) + */ +#define CCAT_ID_1 0x88a4 +#define CCAT_ID_2 0x54414343 +#define CCAT_INFO_BLOCK_PARAMS ((MAX_NUM_SLOTS << 0) | (0x1 << 8) | \ + (0x1 << 16) | (0x1 << 24)) + +#define CCAT_FUN_TYPE_ENTRY 0x0001 +#define CCAT_FUN_TYPE_EEPROM 0x0012 +#define CCAT_FUN_TYPE_DMA 0x0013 + +typedef struct BeckhoffCcat { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + uint8_t mem[CCAT_MEM_SIZE]; + + BlockBackend *eeprom_blk; + uint8_t *eeprom_storage; + uint32_t eeprom_size; +} BeckhoffCcat; + +static void sync_eeprom(BeckhoffCcat *s) +{ + if (!s->eeprom_blk) { + return; + } + blk_pwrite(s->eeprom_blk, 0, s->eeprom_size, s->eeprom_storage, 0); +} + +static uint64_t beckhoff_ccat_eeprom_read(void *opaque, hwaddr addr, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_eeprom_write(void *opaque, hwaddr addr, uint64_t= val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + uint64_t eeprom_adr; + uint64_t buf; + uint32_t bytes_to_read; + + switch (addr) { + case EEPROM_CMD_OFFSET: + eeprom_adr =3D ldl_le_p(&s->mem[EEPROM_ADR_OFFSET]); + eeprom_adr =3D (eeprom_adr * 2) % s->eeprom_size; + if (val & EEPROM_CMD_READ_MASK) { + buf =3D 0; + bytes_to_read =3D 8; + if (eeprom_adr > s->eeprom_size - 8) { + bytes_to_read =3D s->eeprom_size - eeprom_adr; + } + buf =3D ldn_le_p(s->eeprom_storage + eeprom_adr, bytes_to_read= ); + stq_le_p(&s->mem[EEPROM_DATA_OFFSET], buf); + } else if (val & EEPROM_CMD_WRITE_MASK) { + buf =3D ldl_le_p(&s->mem[EEPROM_DATA_OFFSET]); + stw_le_p((uint16_t *)(s->eeprom_storage + eeprom_adr), buf); + sync_eeprom(s); + } + break; + default: + stn_le_p(&s->mem[addr], size, val); + } +} + +static uint64_t beckhoff_ccat_dma_read(void *opaque, hwaddr addr, unsigned= size) +{ + BeckhoffCcat *s =3D opaque; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + if (s->mem[DMA_TRANSFER_OFFSET] & 0x1) { + s->mem[DMA_TRANSFER_OFFSET] =3D 0; + } + break; + } + return ldn_le_p(&s->mem[addr], size); +} + +static void beckhoff_ccat_dma_write(void *opaque, hwaddr addr, uint64_t va= l, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + dma_addr_t dmaAddr; + uint8_t len; + uint8_t *mem_buf; + + switch (addr) { + case DMA_TRANSFER_OFFSET: + len =3D s->mem[DMA_TRANSFER_LENGTH_OFFSET]; + mem_buf =3D &s->mem[DMA_BUFFER_OFFSET]; + dmaAddr =3D ldl_le_p(&s->mem[DMA_HOST_ADR_OFFSET]); + if (s->mem[DMA_DIRECTION_OFFSET] & DMA_DIRECTION_MASK) { + dma_memory_read(&address_space_memory, dmaAddr, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } else { + /* + * The write transfer uses Host DMA Address + 8 as the target + * offset, as described in the CCAT manual Version 0.0.41 + * section 20.2. + */ + dma_memory_write(&address_space_memory, dmaAddr + 8, + mem_buf, len * 8, MEMTXATTRS_UNSPECIFIED); + } + break; + } + stn_le_p(&s->mem[addr], size, val); +} + +static uint64_t beckhoff_ccat_read(void *opaque, hwaddr addr, unsigned siz= e) +{ + BeckhoffCcat *s =3D opaque; + uint64_t val =3D 0; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + return beckhoff_ccat_eeprom_read(opaque, addr, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + return beckhoff_ccat_dma_read(opaque, addr, size); + } else { + val =3D ldn_le_p(&s->mem[addr], size); + } + + return val; +} + +static void beckhoff_ccat_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + BeckhoffCcat *s =3D opaque; + + assert(addr <=3D CCAT_MEM_SIZE - size); + + if (addr >=3D CCAT_EEPROM_OFFSET && + addr <=3D CCAT_EEPROM_OFFSET + s->eeprom_size) { + beckhoff_ccat_eeprom_write(opaque, addr, val, size); + } else if (addr >=3D CCAT_DMA_OFFSET && + addr <=3D CCAT_DMA_OFFSET + CCAT_DMA_SIZE) { + beckhoff_ccat_dma_write(opaque, addr, val, size); + } else { + stn_le_p(&s->mem[addr], size, val); + } +} + +static const MemoryRegionOps beckhoff_ccat_ops =3D { + .read =3D beckhoff_ccat_read, + .write =3D beckhoff_ccat_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 1, + .max_access_size =3D 8, + }, +}; + +static void beckhoff_ccat_reset(DeviceState *dev) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + + memset(&s->mem[0], 0, MAX_NUM_SLOTS * CCAT_FUNCTION_BLOCK_SIZE); + + size_t offset =3D 0 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_ENTRY); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], CCAT_INFO_BLOCK_PARAMS); + stl_le_p(&s->mem[offset + 8], CCAT_ID_1); + stl_le_p(&s->mem[offset + 12], CCAT_ID_2); + + offset =3D 11 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_EEPROM); + stw_le_p(&s->mem[offset + 2], 0x0001); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_EEPROM_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_EEPROM_SIZE); + + offset =3D 15 * CCAT_FUNCTION_BLOCK_SIZE; + stw_le_p(&s->mem[offset + 0], CCAT_FUN_TYPE_DMA); + stw_le_p(&s->mem[offset + 2], 0x0000); + stl_le_p(&s->mem[offset + 4], 0); + stl_le_p(&s->mem[offset + 8], CCAT_DMA_OFFSET); + stl_le_p(&s->mem[offset + 12], CCAT_DMA_SIZE); +} + +static void beckhoff_ccat_realize(DeviceState *dev, Error **errp) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(dev); + BlockBackend *blk; + + blk =3D s->eeprom_blk; + + if (blk) { + uint64_t blk_size =3D blk_getlength(blk); + if (!is_power_of_2(blk_size)) { + error_setg(errp, "Blockend size is not a power of two."); + return; + } + + if (blk_size < 512) { + error_setg(errp, "Blockend size is too small."); + return; + } else { + blk_set_perm(blk, BLK_PERM_WRITE, BLK_PERM_ALL, errp); + + s->eeprom_size =3D blk_size; + s->eeprom_blk =3D blk; + s->eeprom_storage =3D blk_blockalign(s->eeprom_blk, s->eeprom_= size); + + if (!blk_check_size_and_read_all(s->eeprom_blk, DEVICE(s), + s->eeprom_storage, s->eeprom_= size, + errp)) { + return; + } + } + } else { + s->eeprom_size =3D EEPROM_MEMORY_SIZE; + s->eeprom_storage =3D blk_blockalign(NULL, s->eeprom_size); + memset(s->eeprom_storage, 0x00, s->eeprom_size); + } +} + +static void beckhoff_ccat_init(Object *obj) +{ + BeckhoffCcat *s =3D BECKHOFF_CCAT(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + memory_region_init_io(&s->iomem, obj, &beckhoff_ccat_ops, s, + TYPE_BECKHOFF_CCAT, CCAT_MEM_SIZE); + sysbus_init_mmio(sbd, &s->iomem); +} + +static const VMStateDescription vmstate_beckhoff_ccat =3D { + .name =3D "beckhoff-ccat", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (const VMStateField[]) { + VMSTATE_UINT8_ARRAY(mem, BeckhoffCcat, CCAT_MEM_SIZE), + VMSTATE_UINT32(eeprom_size, BeckhoffCcat), + VMSTATE_VBUFFER_UINT32(eeprom_storage, BeckhoffCcat, 1, NULL, + eeprom_size), + VMSTATE_END_OF_LIST() + } +}; + +static const Property beckhoff_ccat_properties[] =3D { + DEFINE_PROP_DRIVE("eeprom", BeckhoffCcat, eeprom_blk), +}; + +static void beckhoff_ccat_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D beckhoff_ccat_realize; + device_class_set_legacy_reset(dc, beckhoff_ccat_reset); + dc->vmsd =3D &vmstate_beckhoff_ccat; + device_class_set_props(dc, beckhoff_ccat_properties); +} + +static const TypeInfo beckhoff_ccat_info =3D { + .name =3D TYPE_BECKHOFF_CCAT, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BeckhoffCcat), + .instance_init =3D beckhoff_ccat_init, + .class_init =3D beckhoff_ccat_class_init, +}; + +static void beckhoff_ccat_register_types(void) +{ + type_register_static(&beckhoff_ccat_info); +} + +type_init(beckhoff_ccat_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6ee7b6c71d..1fc1468464 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -14,6 +14,7 @@ system_ss.add(when: 'CONFIG_PL310', if_true: files('arm_l= 2x0.c')) system_ss.add(when: 'CONFIG_INTEGRATOR_DEBUG', if_true: files('arm_integra= tor_debug.c')) system_ss.add(when: 'CONFIG_A9SCU', if_true: files('a9scu.c')) system_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('arm11scu.c')) +system_ss.add(when: 'CONFIG_BECKHOFF_CCAT', if_true: files('beckhoff_ccat.= c')) =20 system_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_ras.c')) =20 --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 11 Nov 2025 02:28:48 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 12/15] hw/block/m25p80: Add HAS_SR_TB flag for is25lp016d Date: Tue, 11 Nov 2025 11:28:33 +0100 Message-ID: <20251111102836.212535-13-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857100596153000 Content-Type: text/plain; charset="utf-8" From: YannickV The is25lp016d has 4 Block Write Protect Bits. BP3 specifies whether the upper or lower range should be protected. Therefore, we add the HAS_SR_TB flag to the is25lp016d flags. Signed-off-by: YannickV --- hw/block/m25p80.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index b84c6afb32..4c9d79ec44 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -217,7 +217,8 @@ static const FlashPartInfo known_devices[] =3D { /* ISSI */ { INFO("is25lq040b", 0x9d4013, 0, 64 << 10, 8, ER_4K) }, { INFO("is25lp080d", 0x9d6014, 0, 64 << 10, 16, ER_4K) }, - { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, ER_4K) }, + { INFO("is25lp016d", 0x9d6015, 0, 64 << 10, 32, + ER_4K | HAS_SR_TB) }, { INFO("is25lp032", 0x9d6016, 0, 64 << 10, 64, ER_4K) }, { INFO("is25lp064", 0x9d6017, 0, 64 << 10, 128, ER_4K) }, { INFO("is25lp128", 0x9d6018, 0, 64 << 10, 256, ER_4K) }, --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Tue, 11 Nov 2025 02:28:49 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 13/15] hw/arm: Add new machine based on xilinx-zynq-a9 for Beckhoff CX7200 Date: Tue, 11 Nov 2025 11:28:34 +0100 Message-ID: <20251111102836.212535-14-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857012691153000 Content-Type: text/plain; charset="utf-8" From: YannickV This commit introduces a new machine, derived from xilinx-zynq-a9. While retaining the foundational architecture, unnecessary peripherals have been removed and the remaining peripherals have been adapted to match the CX7200's hardware layout and behavior. Signed-off-by: YannickV --- hw/arm/Kconfig | 18 ++ hw/arm/beckhoff_CX7200.c | 443 +++++++++++++++++++++++++++++++++++++++ hw/arm/meson.build | 1 + 3 files changed, 462 insertions(+) create mode 100644 hw/arm/beckhoff_CX7200.c diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 256013ca80..66af990da9 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -310,6 +310,24 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG =20 +config BECKHOFF_CX7200 + bool + default y + depends on TCG && ARM + select A9MPCORE + select CADENCE # UART + select PFLASH_CFI02 + select PL310 # cache controller + select PL330 + select SDHCI + select SSI_M25P80 + select XILINX # UART + select XILINX_AXI + select XILINX_SPI + select XILINX_SPIPS + select ZYNQ_DEVCFG + select BECKHOFF_CCAT + config ARM_V7M bool # currently v7M must be included in a TCG build due to translate.c diff --git a/hw/arm/beckhoff_CX7200.c b/hw/arm/beckhoff_CX7200.c new file mode 100644 index 0000000000..b99e022931 --- /dev/null +++ b/hw/arm/beckhoff_CX7200.c @@ -0,0 +1,443 @@ +/* + * Modified Xilinx Zynq Baseboard System emulation for Beckhoff CX7200. + * + * Copyright (c) 2024 Beckhoff Automation GmbH & Co. KG + * + * Based on /hw/arm/xilinx_zynq.c: + * Copyright (c) 2010 Xilinx. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.= com) + * Copyright (c) 2012 Petalogix Pty Ltd. + * Original code by Haibing Ma. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/sysbus.h" +#include "hw/arm/boot.h" +#include "net/net.h" +#include "system/system.h" +#include "hw/boards.h" +#include "hw/block/flash.h" +#include "hw/loader.h" +#include "hw/adc/zynq-xadc.h" +#include "hw/ssi/ssi.h" +#include "qemu/error-report.h" +#include "hw/sd/sdhci.h" +#include "hw/char/cadence_uart.h" +#include "hw/net/cadence_gem.h" +#include "hw/cpu/a9mpcore.h" +#include "hw/qdev-clock.h" +#include "hw/misc/unimp.h" +#include "system/reset.h" +#include "qom/object.h" +#include "exec/tswap.h" +#include "target/arm/cpu-qom.h" +#include "qapi/visitor.h" +#include "system/block-backend.h" + + +#define TYPE_CX7200_MACHINE MACHINE_TYPE_NAME("beckhoff-cx7200") +OBJECT_DECLARE_SIMPLE_TYPE(CX7200MachineState, CX7200_MACHINE) + +/* board base frequency: 33.333333 MHz */ +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) + +#define PERIPHCLK_DIVIDER 2 +#define PS7_CPU_CLK_FREQUENCY 720000000 + +#define NUM_SPI_FLASHES 0 +#define NUM_QSPI_FLASHES 1 +#define NUM_QSPI_BUSSES 1 + +#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ + +#define MPCORE_PERIPHBASE 0xF8F00000 +#define ZYNQ_BOARD_MIDR 0x413FC090 + +static const int dma_irqs[8] =3D { + 46, 47, 48, 49, 72, 73, 74, 75 +}; + +#define BOARD_SETUP_ADDR 0x100 + +#define SLCR_LOCK_OFFSET 0x004 +#define SLCR_UNLOCK_OFFSET 0x008 +#define SLCR_ARM_PLL_OFFSET 0x100 + +#define SLCR_XILINX_UNLOCK_KEY 0xdf0d +#define SLCR_XILINX_LOCK_KEY 0x767b + +#define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) = */ + +#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ + extract32((x), 12, 4) << 16) + +/* + * Write immediate val to address r0 + addr. r0 should contain base offset + * of the SLCR block. Clobbers r1. + */ + +#define SLCR_WRITE(addr, val) \ + 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ + 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ + 0xe5801000 + (addr) + +#define ZYNQ_MAX_CPUS 2 + +struct CX7200MachineState { + MachineState parent; + Clock *ps_clk; + ARMCPU *cpu[ZYNQ_MAX_CPUS]; + uint8_t boot_mode; +}; + +static void beckhoff_cx7200_write_board_setup(ARMCPU *cpu, + const struct arm_boot_info *info) +{ + int n; + uint32_t board_setup_blob[] =3D { + 0xe3a004f8, /* mov r0, #0xf8000000 */ + SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), + SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), + SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), + 0xe12fff1e, /* bx lr */ + }; + for (n =3D 0; n < ARRAY_SIZE(board_setup_blob); n++) { + board_setup_blob[n] =3D tswap32(board_setup_blob[n]); + } + rom_add_blob_fixed("board-setup", board_setup_blob, + sizeof(board_setup_blob), BOARD_SETUP_ADDR); +} + +static struct arm_boot_info beckhoff_cx7200_binfo =3D {}; + +static void gem_init(uint32_t base, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *s; + + dev =3D qdev_new(TYPE_CADENCE_GEM); + qemu_configure_nic_device(dev, true, NULL); + object_property_set_int(OBJECT(dev), "phy-addr", 7, &error_abort); + s =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_mmio_map(s, 0, base); + sysbus_connect_irq(s, 0, irq); +} + +static void ccat_init(uint32_t base, BlockBackend *eeprom_blk) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("beckhoff-ccat"); + if (eeprom_blk) { + qdev_prop_set_drive_err(dev, "eeprom", eeprom_blk, &error_fatal); + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + +static void ddr_ctrl_init(uint32_t base) +{ + DeviceState *dev; + SysBusDevice *busdev; + + dev =3D qdev_new("zynq.ddr-ctlr"); + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base); +} + +static inline int beckhoff_cx7200_init_spi_flashes(uint32_t base_addr, + qemu_irq irq, bool is_qspi, int un= it0) +{ + int unit =3D unit0; + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + DeviceState *flash_dev; + int i, j; + int num_busses =3D is_qspi ? NUM_QSPI_BUSSES : 1; + int num_ss =3D is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; + + dev =3D qdev_new(is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi"); + qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1); + qdev_prop_set_uint8(dev, "num-ss-bits", num_ss); + qdev_prop_set_uint8(dev, "num-busses", num_busses); + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, base_addr); + if (is_qspi) { + sysbus_mmio_map(busdev, 1, 0xFC000000); + } + sysbus_connect_irq(busdev, 0, irq); + + for (i =3D 0; i < num_busses; ++i) { + char bus_name[16]; + qemu_irq cs_line; + + snprintf(bus_name, 16, "spi%d", i); + spi =3D (SSIBus *)qdev_get_child_bus(dev, bus_name); + + for (j =3D 0; j < num_ss; ++j) { + DriveInfo *dinfo =3D drive_get(IF_MTD, 0, unit++); + flash_dev =3D qdev_new("is25lp016d"); + if (dinfo) { + qdev_prop_set_drive_err(flash_dev, "drive", + blk_by_legacy_dinfo(dinfo), + &error_fatal); + } + qdev_prop_set_uint8(flash_dev, "cs", j); + qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); + + cs_line =3D qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); + sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); + } + } + + return unit; +} + +static void beckhoff_cx7200_set_boot_mode(Object *obj, const char *str, + Error **errp) +{ + CX7200MachineState *m =3D CX7200_MACHINE(obj); + uint8_t mode =3D 0; + + if (!strncasecmp(str, "qspi", 4)) { + mode =3D 1; + } else if (!strncasecmp(str, "sd", 2)) { + mode =3D 5; + } else if (!strncasecmp(str, "nor", 3)) { + mode =3D 2; + } else if (!strncasecmp(str, "jtag", 4)) { + mode =3D 0; + } else { + error_setg(errp, "%s boot mode not supported", str); + return; + } + m->boot_mode =3D mode; +} + +static void beckhoff_cx7200_init(MachineState *machine) +{ + CX7200MachineState *cx7200_machine =3D CX7200_MACHINE(machine); + MemoryRegion *address_space_mem =3D get_system_memory(); + MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); + DeviceState *carddev, *dev, *slcr; + SysBusDevice *busdev; + qemu_irq pic[64]; + int n; + unsigned int smp_cpus =3D machine->smp.cpus; + DriveInfo *di; + BlockBackend *blk; + + /* max 2GB ram */ + if (machine->ram_size > 2 * GiB) { + error_report("RAM size more than 2 GiB is not supported"); + exit(EXIT_FAILURE); + } + + for (n =3D 0; n < smp_cpus; n++) { + Object *cpuobj =3D object_new(machine->cpu_type); + + object_property_set_int(cpuobj, "midr", ZYNQ_BOARD_MIDR, + &error_fatal); + object_property_set_int(cpuobj, "reset-cbar", MPCORE_PERIPHBASE, + &error_fatal); + + qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); + + cx7200_machine->cpu[n] =3D ARM_CPU(cpuobj); + } + + /* DDR remapped to address zero. */ + memory_region_add_subregion(address_space_mem, 0, machine->ram); + + /* 256K of on-chip memory */ + memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 * KiB, + &error_fatal); + memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); + + /* Create the main clock source, and feed slcr with it */ + cx7200_machine->ps_clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(cx7200_machine), "ps_clk", + OBJECT(cx7200_machine->ps_clk)); + object_unref(OBJECT(cx7200_machine->ps_clk)); + clock_set_hz(cx7200_machine->ps_clk, PS_CLK_FREQUENCY); + + /* Create slcr, keep a pointer to connect clocks */ + slcr =3D qdev_new("xilinx-zynq_slcr"); + qdev_connect_clock_in(slcr, "ps_clk", cx7200_machine->ps_clk); + qdev_prop_set_uint8(slcr, "boot-mode", cx7200_machine->boot_mode); + sysbus_realize_and_unref(SYS_BUS_DEVICE(slcr), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); + + dev =3D qdev_new(TYPE_A9MPCORE_PRIV); + qdev_prop_set_uint32(dev, "num-cpu", smp_cpus); + A9MPPrivState *a9mp_priv_state =3D A9MPCORE_PRIV(dev); + a9mp_priv_state->gtimer.freq_hz =3D PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->gtimer.periphclk_divider =3D PERIPHCLK_DIVIDER; + a9mp_priv_state->mptimer.freq_hz =3D PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->mptimer.periphclk_divider =3D PERIPHCLK_DIVIDER; + a9mp_priv_state->wdt.freq_hz =3D PS7_CPU_CLK_FREQUENCY; + a9mp_priv_state->wdt.periphclk_divider =3D PERIPHCLK_DIVIDER; + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); + beckhoff_cx7200_binfo.gic_cpu_if_addr =3D MPCORE_PERIPHBASE + 0x100; + sysbus_create_varargs("l2x0", MPCORE_PERIPHBASE + 0x2000, NULL); + for (n =3D 0; n < smp_cpus; n++) { + /* See "hw/intc/arm_gic.h" for the IRQ line association */ + DeviceState *cpudev =3D DEVICE(cx7200_machine->cpu[n]); + sysbus_connect_irq(busdev, n, + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); + sysbus_connect_irq(busdev, smp_cpus + n, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + } + + for (n =3D 0; n < 64; n++) { + pic[n] =3D qdev_get_gpio_in(dev, n); + } + + n =3D beckhoff_cx7200_init_spi_flashes(0xE0006000, pic[58 - IRQ_OFFSET= ], + false, 0); + n =3D beckhoff_cx7200_init_spi_flashes(0xE0007000, pic[81 - IRQ_OFFSET= ], + false, n); + n =3D beckhoff_cx7200_init_spi_flashes(0xE000D000, pic[51 - IRQ_OFFSET= ], + true, n); + + dev =3D qdev_new(TYPE_CADENCE_UART); + busdev =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart0_ref_clk")); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xE0000000); + sysbus_connect_irq(busdev, 0, pic[59 - IRQ_OFFSET]); + dev =3D qdev_new(TYPE_CADENCE_UART); + busdev =3D SYS_BUS_DEVICE(dev); + qdev_prop_set_chr(dev, "chardev", serial_hd(1)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart1_ref_clk")); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xE0001000); + sysbus_connect_irq(busdev, 0, pic[82 - IRQ_OFFSET]); + + sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42 - IRQ_OFFSET], + pic[43 - IRQ_OFFSET], pic[44 - IRQ_OFFSET], NULL= ); + sysbus_create_varargs("cadence_ttc", 0xF8002000, pic[69 - IRQ_OFFSET], + pic[70 - IRQ_OFFSET], pic[71 - IRQ_OFFSET], NULL= ); + + gem_init(0xE000C000, pic[77 - IRQ_OFFSET]); + + di =3D drive_get(IF_NONE, 0, 0); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + ccat_init(0x40000000, blk); + + ddr_ctrl_init(0xF8006000); + + /* + * Compatible with: + * - SD Host Controller Specification Version 2.0 Part A2 + * - SDIO Specification Version 2.0 + * - MMC Specification Version 3.31 + */ + dev =3D qdev_new(TYPE_SYSBUS_SDHCI); + qdev_prop_set_uint8(dev, "sd-spec-version", 2); + qdev_prop_set_uint64(dev, "capareg", ZYNQ_SDHCI_CAPABILITIES); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79 - IRQ_OFFSET]); + + di =3D drive_get(IF_SD, 0, 0); + blk =3D di ? blk_by_legacy_dinfo(di) : NULL; + carddev =3D qdev_new(TYPE_SD_CARD); + qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); + qdev_realize_and_unref(carddev, qdev_get_child_bus(dev, "sd-bus"), + &error_fatal); + + dev =3D qdev_new(TYPE_ZYNQ_XADC); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39 - IRQ_OFFSET]); + + dev =3D qdev_new("pl330"); + object_property_set_link(OBJECT(dev), "memory", + OBJECT(address_space_mem), + &error_fatal); + qdev_prop_set_uint8(dev, "num_chnls", 8); + qdev_prop_set_uint8(dev, "num_periph_req", 4); + qdev_prop_set_uint8(dev, "num_events", 16); + + qdev_prop_set_uint8(dev, "data_width", 64); + qdev_prop_set_uint8(dev, "wr_cap", 8); + qdev_prop_set_uint8(dev, "wr_q_dep", 16); + qdev_prop_set_uint8(dev, "rd_cap", 8); + qdev_prop_set_uint8(dev, "rd_q_dep", 16); + qdev_prop_set_uint16(dev, "data_buffer_dep", 256); + + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_mmio_map(busdev, 0, 0xF8003000); + sysbus_connect_irq(busdev, 0, pic[45 - IRQ_OFFSET]); /* abort irq line= */ + for (n =3D 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ + sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); + } + + dev =3D qdev_new("xlnx.ps7-dev-cfg"); + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(busdev, &error_fatal); + sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); + sysbus_mmio_map(busdev, 0, 0xF8007000); + + beckhoff_cx7200_binfo.ram_size =3D machine->ram_size; + beckhoff_cx7200_binfo.board_id =3D 0xd32; + beckhoff_cx7200_binfo.loader_start =3D 0; + beckhoff_cx7200_binfo.board_setup_addr =3D BOARD_SETUP_ADDR; + beckhoff_cx7200_binfo.write_board_setup =3D beckhoff_cx7200_write_boar= d_setup; + + arm_load_kernel(cx7200_machine->cpu[0], machine, &beckhoff_cx7200_binf= o); +} + +static void beckhoff_cx7200_machine_class_init(ObjectClass *oc, void *data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-a9"), + NULL + }; + MachineClass *mc =3D MACHINE_CLASS(oc); + ObjectProperty *prop; + mc->desc =3D "Beckhoff IPC based on the Xilinx Zynq Platform Baseboard= "; + mc->init =3D beckhoff_cx7200_init; + mc->max_cpus =3D ZYNQ_MAX_CPUS; + mc->no_sdcard =3D 1; + mc->ignore_memory_transaction_failures =3D true; + mc->valid_cpu_types =3D valid_cpu_types; + mc->default_ram_id =3D "zynq.ext_ram"; + prop =3D object_class_property_add_str(oc, "boot-mode", NULL, + beckhoff_cx7200_set_boot_mode); + object_class_property_set_description(oc, "boot-mode", + "Supported boot modes:" + " jtag qspi sd nor"); + object_property_set_default_str(prop, "qspi"); +} + +static const TypeInfo beckhoff_cx7200_machine_type =3D { + .name =3D TYPE_CX7200_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D beckhoff_cx7200_machine_class_init, + .instance_size =3D sizeof(CX7200MachineState), +}; + +static void beckhoff_cx7200_machine_register_types(void) +{ + type_register_static(&beckhoff_cx7200_machine_type); +} + +type_init(beckhoff_cx7200_machine_register_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index 490234b3b8..b774b066dd 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -17,6 +17,7 @@ arm_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa-= ref.c')) arm_ss.add(when: 'CONFIG_STELLARIS', if_true: files('stellaris.c')) arm_ss.add(when: 'CONFIG_STM32VLDISCOVERY', if_true: files('stm32vldiscove= ry.c')) arm_ss.add(when: 'CONFIG_ZYNQ', if_true: files('xilinx_zynq.c')) +arm_ss.add(when: 'CONFIG_BECKHOFF_CX7200', if_true: files('beckhoff_CX7200= .c')) arm_ss.add(when: 'CONFIG_SABRELITE', if_true: files('sabrelite.c')) =20 arm_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m.c')) --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 11 Nov 2025 02:28:50 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 14/15] tests/functional: Add a Beckhoff CX7200 test Date: Tue, 11 Nov 2025 11:28:35 +0100 Message-ID: <20251111102836.212535-15-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857101016158500 Content-Type: text/plain; charset="utf-8" From: YannickV TODO --- tests/functional/test_arm_beckhoff_cx7200.py | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 tests/functional/test_arm_beckhoff_cx7200.py diff --git a/tests/functional/test_arm_beckhoff_cx7200.py b/tests/functiona= l/test_arm_beckhoff_cx7200.py new file mode 100644 index 0000000000..a7fb88ac30 --- /dev/null +++ b/tests/functional/test_arm_beckhoff_cx7200.py @@ -0,0 +1,19 @@ +#!/usr/bin/env python3 +# +# Functional test that boots a bare metal application on the Beckhoff CX72= 00 +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from qemu_test import LinuxKernelTest + +class CX7200Test(LinuxKernelTest): + def test_baremetal_elf(self): + self.set_machine('beckhoff-cx7200') + elf_path =3D '/home/yannickv/git/build-TCRTOS/FreeRTOS/Zynq7000/Dr= iveZynq_Fsbl/build/CX7200/Optg/ZYNQ7000S/CX7200_Zynq_Fsbl.elf' + self.vm.set_console() + self.vm.add_args('-kernel', elf_path, '-nographic') + self.vm.launch() + self.wait_for_console_pattern('Boot mode is SD') + +if __name__ =3D=3D '__main__': + LinuxKernelTest.main() \ No newline at end of file --=20 2.47.3 From nobody Fri Nov 14 18:21:31 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Tue, 11 Nov 2025 02:28:51 -0800 (PST) From: =?UTF-8?q?Corvin=20K=C3=B6hne?= To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Yannick=20Vo=C3=9Fen?= , qemu-block@nongnu.org, Paolo Bonzini , Hanna Reitz , Alistair Francis , qemu-arm@nongnu.org, =?UTF-8?q?Corvin=20K=C3=B6hne?= , Kevin Wolf , "Edgar E. Iglesias" , YannickV Subject: [PATCH v4 15/15] docs/system/arm: Add support for Beckhoff CX7200 Date: Tue, 11 Nov 2025 11:28:36 +0100 Message-ID: <20251111102836.212535-16-corvin.koehne@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20251111102836.212535-1-corvin.koehne@gmail.com> References: <20251111102836.212535-1-corvin.koehne@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=corvin.koehne@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, WEIRD_QUOTING=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1762857145770158500 Content-Type: text/plain; charset="utf-8" From: YannickV This commit offers some documentation on the Beckhoff CX7200 qemu emulation. Signed-off-by: YannickV --- docs/system/arm/beckhoff-cx7200.rst | 57 +++++++++++++++++++++++++++++ docs/system/target-arm.rst | 1 + 2 files changed, 58 insertions(+) create mode 100644 docs/system/arm/beckhoff-cx7200.rst diff --git a/docs/system/arm/beckhoff-cx7200.rst b/docs/system/arm/beckhoff= -cx7200.rst new file mode 100644 index 0000000000..f060319b0f --- /dev/null +++ b/docs/system/arm/beckhoff-cx7200.rst @@ -0,0 +1,57 @@ +Beckhoff CX7200 (``beckhoff-cx7200``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The Beckhoff CX7200 is based on the same architecture as the Xilinx Zynq A= 9. +The Zynq 7000 family is based on the AMD SoC architecture. These products +integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based +processing system (PS) and AMD programmable logic (PL) in a single device. +The Beckhoff Communication Controller (CCAT) can be found in the PL of Zyn= q. + +More details here: +https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technic= al-Reference-Manual +https://www.beckhoff.com/de-de/produkte/ipc/embedded-pcs/cx7000-arm-r-cort= ex-r/cx7293.html + +The CX7200 supports following devices: + - A9 MPCORE + - cortex-a9 + - GIC v1 + - Generic timer + - wdt + - OCM 256KB + - SMC SRAM@0xe2000000 64MB + - Zynq SLCR + - SPI x2 + - QSPI + - UART + - TTC x2 + - Gigabit Ethernet Controller + - SD Controller + - XADC + - Arm PrimeCell DMA Controller + - DDR Memory + - DDR Controller + - Beckhoff Communication Controller (CCAT) + - EEPROM Interface + - DMA Controller + +Following devices are not supported: + - I2C + +Running +""""""" +Directly loading an ELF file to the CPU of the CX7200 to run f.e. TC/RTOS = (based on FreeRTOS): + +.. code-block:: bash + + $ qemu-system-arm -M beckhoff-cx7200 \ + -device loader,file=3DCX7200_Zynq_Fsbl.elf \ + -display none \ + -icount shift=3Dauto \ + + +For setting the EEPROM content of the CCAT provide the following on the co= mmand line: + +.. code-block:: bash + + -drive file=3Deeprom.bin,format=3Draw,id=3Dccat-eeprom + +The size of eeprom.bin must be aligned to a power of 2 and bigger than 256= bytes. diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst index 9aaa9c414c..5f15fda630 100644 --- a/docs/system/target-arm.rst +++ b/docs/system/target-arm.rst @@ -81,6 +81,7 @@ Board-specific documentation arm/aspeed arm/bananapi_m2u.rst arm/b-l475e-iot01a.rst + arm/beckhoff-cx7200 arm/sabrelite arm/highbank arm/digic --=20 2.47.3