From nobody Sun Dec 14 12:18:18 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762775401686193.02215941020245; Mon, 10 Nov 2025 03:50:01 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vIQOl-0006sH-Ac; Mon, 10 Nov 2025 06:49:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vIPzl-0003vz-FA for qemu-devel@nongnu.org; Mon, 10 Nov 2025 06:23:40 -0500 Received: from inva021.nxp.com ([92.121.34.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vIPzi-00068s-Um for qemu-devel@nongnu.org; Mon, 10 Nov 2025 06:23:37 -0500 Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id B228B202DE0; Mon, 10 Nov 2025 12:23:33 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 7DFD6201524; Mon, 10 Nov 2025 12:23:33 +0100 (CET) Received: from lsv031015.swis.in-blr01.nxp.com (lsv031015.swis.in-blr01.nxp.com [10.12.177.77]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id A4BE818000A4; Mon, 10 Nov 2025 19:23:32 +0800 (+08) From: Gaurav Sharma To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peter.maydell@linaro.org, Gaurav Sharma Subject: [PATCH 08/13] hw/arm/fsl-imx8mm: Adding support for SPI controller Date: Mon, 10 Nov 2025 16:52:52 +0530 Message-Id: <20251110112257.184578-9-gaurav.sharma_7@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251110112257.184578-1-gaurav.sharma_7@nxp.com> References: <20251110112257.184578-1-gaurav.sharma_7@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=92.121.34.21; envelope-from=gaurav.sharma_7@nxp.com; helo=inva021.nxp.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762775402866158500 Content-Type: text/plain; charset="utf-8" It enables emulation of ECSPI in iMX8MM Added SPI IRQ lines Signed-off-by: Gaurav Sharma Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/imx8mm-evk.rst | 1 + hw/arm/fsl-imx8mm.c | 26 ++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 7 +++++++ 3 files changed, 34 insertions(+) diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst index faf90336e0..bbe2d2e6e2 100644 --- a/docs/system/arm/imx8mm-evk.rst +++ b/docs/system/arm/imx8mm-evk.rst @@ -16,6 +16,7 @@ The ``imx8mm-evk`` machine implements the following devic= es: * 1 Designware PCI Express Controller * 5 GPIO Controllers * 6 I2C Controllers + * 3 SPI Controllers * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index eaa9a66efc..c15d8cf8d6 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -192,6 +192,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->usdhc[i], TYPE_IMX_USDHC); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { + g_autofree char *name =3D g_strdup_printf("spi%d", i + 1); + object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -449,6 +454,26 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) qdev_get_gpio_in(gicdev, usdhc_table[i].irq)); } =20 + /* ECSPIs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_ECSPIS; i++) { + struct { + hwaddr addr; + unsigned int irq; + } spi_table[FSL_IMX8MM_NUM_ECSPIS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI1].addr, FSL_IMX8MM_ECSPI1= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI2].addr, FSL_IMX8MM_ECSPI2= _IRQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_ECSPI3].addr, FSL_IMX8MM_ECSPI3= _IRQ }, + }; + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + qdev_get_gpio_in(gicdev, spi_table[i].irq)); + } + /* SNVS */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->snvs), errp)) { return; @@ -488,6 +513,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_GIC_DIST: case FSL_IMX8MM_GIC_REDIST: case FSL_IMX8MM_GPIO1 ... FSL_IMX8MM_GPIO5: + case FSL_IMX8MM_ECSPI1 ... FSL_IMX8MM_ECSPI3: case FSL_IMX8MM_I2C1 ... FSL_IMX8MM_I2C4: case FSL_IMX8MM_PCIE1: case FSL_IMX8MM_PCIE_PHY1: diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index e68dbd188b..f3a3304565 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -20,6 +20,7 @@ #include "hw/pci-host/designware.h" #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" +#include "hw/ssi/imx_spi.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -31,6 +32,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(FslImx8mmState, FSL_IMX8MM) =20 enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_CPUS =3D 4, + FSL_IMX8MM_NUM_ECSPIS =3D 3, FSL_IMX8MM_NUM_GPIOS =3D 5, FSL_IMX8MM_NUM_I2CS =3D 4, FSL_IMX8MM_NUM_IRQS =3D 128, @@ -47,6 +49,7 @@ struct FslImx8mmState { IMX8MMCCMState ccm; IMX8MMAnalogState analog; IMX7SNVSState snvs; + IMXSPIState spi[FSL_IMX8MM_NUM_ECSPIS]; IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; @@ -175,6 +178,10 @@ enum FslImx8mmIrqs { FSL_IMX8MM_UART3_IRQ =3D 28, FSL_IMX8MM_UART4_IRQ =3D 29, =20 + FSL_IMX8MM_ECSPI1_IRQ =3D 31, + FSL_IMX8MM_ECSPI2_IRQ =3D 32, + FSL_IMX8MM_ECSPI3_IRQ =3D 33, + FSL_IMX8MM_I2C1_IRQ =3D 35, FSL_IMX8MM_I2C2_IRQ =3D 36, FSL_IMX8MM_I2C3_IRQ =3D 37, --=20 2.34.1