From nobody Sun Dec 14 12:18:20 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=nxp.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762775113948383.65954644412295; Mon, 10 Nov 2025 03:45:13 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vIQIH-0001Mq-4k; Mon, 10 Nov 2025 06:42:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vIPzl-0003w2-Ih for qemu-devel@nongnu.org; Mon, 10 Nov 2025 06:23:40 -0500 Received: from inva020.nxp.com ([92.121.34.13]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vIPzj-00068z-ND for qemu-devel@nongnu.org; Mon, 10 Nov 2025 06:23:37 -0500 Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id AC33B1A2576; Mon, 10 Nov 2025 12:23:34 +0100 (CET) Received: from aprdc01srsp001v.ap-rdc01.nxp.com (aprdc01srsp001v.ap-rdc01.nxp.com [165.114.16.16]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 763311A1D48; Mon, 10 Nov 2025 12:23:34 +0100 (CET) Received: from lsv031015.swis.in-blr01.nxp.com (lsv031015.swis.in-blr01.nxp.com [10.12.177.77]) by aprdc01srsp001v.ap-rdc01.nxp.com (Postfix) with ESMTP id 996481800083; Mon, 10 Nov 2025 19:23:33 +0800 (+08) From: Gaurav Sharma To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, peter.maydell@linaro.org, Gaurav Sharma Subject: [PATCH 09/13] hw/arm/fsl-imx8mm: Adding support for Watchdog Timers Date: Mon, 10 Nov 2025 16:52:53 +0530 Message-Id: <20251110112257.184578-10-gaurav.sharma_7@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251110112257.184578-1-gaurav.sharma_7@nxp.com> References: <20251110112257.184578-1-gaurav.sharma_7@nxp.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Virus-Scanned: ClamAV using ClamSMTP Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=92.121.34.13; envelope-from=gaurav.sharma_7@nxp.com; helo=inva020.nxp.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762775114648158500 Content-Type: text/plain; charset="utf-8" It enables emulation of WDT in iMX8MM Added WDT IRQ lines Signed-off-by: Gaurav Sharma Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/imx8mm-evk.rst | 1 + hw/arm/Kconfig | 1 + hw/arm/fsl-imx8mm.c | 28 ++++++++++++++++++++++++++++ include/hw/arm/fsl-imx8mm.h | 7 +++++++ 4 files changed, 37 insertions(+) diff --git a/docs/system/arm/imx8mm-evk.rst b/docs/system/arm/imx8mm-evk.rst index bbe2d2e6e2..5311e685fb 100644 --- a/docs/system/arm/imx8mm-evk.rst +++ b/docs/system/arm/imx8mm-evk.rst @@ -17,6 +17,7 @@ The ``imx8mm-evk`` machine implements the following devic= es: * 5 GPIO Controllers * 6 I2C Controllers * 3 SPI Controllers + * 3 Watchdogs * Secure Non-Volatile Storage (SNVS) including an RTC * Clock Tree =20 diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d442ea0624..9498a96f30 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -638,6 +638,7 @@ config FSL_IMX8MM select SDHCI select PCI_EXPRESS_DESIGNWARE select PCI_EXPRESS_FSL_IMX8M_PHY + select WDT_IMX2 =20 config FSL_IMX8MM_EVK bool diff --git a/hw/arm/fsl-imx8mm.c b/hw/arm/fsl-imx8mm.c index c15d8cf8d6..6ee2890736 100644 --- a/hw/arm/fsl-imx8mm.c +++ b/hw/arm/fsl-imx8mm.c @@ -197,6 +197,11 @@ static void fsl_imx8mm_init(Object *obj) object_initialize_child(obj, name, &s->spi[i], TYPE_IMX_SPI); } =20 + for (i =3D 0; i < FSL_IMX8MM_NUM_WDTS; i++) { + g_autofree char *name =3D g_strdup_printf("wdt%d", i); + object_initialize_child(obj, name, &s->wdt[i], TYPE_IMX2_WDT); + } + object_initialize_child(obj, "pcie", &s->pcie, TYPE_DESIGNWARE_PCIE_HO= ST); object_initialize_child(obj, "pcie_phy", &s->pcie_phy, TYPE_FSL_IMX8M_PCIE_PHY); @@ -481,6 +486,28 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error= **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->snvs), 0, fsl_imx8mm_memmap[FSL_IMX8MM_SNVS_HP].addr); =20 + /* Watchdogs */ + for (i =3D 0; i < FSL_IMX8MM_NUM_WDTS; i++) { + struct { + hwaddr addr; + unsigned int irq; + } wdog_table[FSL_IMX8MM_NUM_WDTS] =3D { + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG1].addr, FSL_IMX8MM_WDOG1_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG2].addr, FSL_IMX8MM_WDOG2_I= RQ }, + { fsl_imx8mm_memmap[FSL_IMX8MM_WDOG3].addr, FSL_IMX8MM_WDOG3_I= RQ }, + }; + + object_property_set_bool(OBJECT(&s->wdt[i]), "pretimeout-support", + true, &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, wdog_table[i].addr); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->wdt[i]), 0, + qdev_get_gpio_in(gicdev, wdog_table[i].irq)); + } + /* PCIe */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->pcie), errp)) { return; @@ -521,6 +548,7 @@ static void fsl_imx8mm_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MM_SNVS_HP: case FSL_IMX8MM_UART1 ... FSL_IMX8MM_UART4: case FSL_IMX8MM_USDHC1 ... FSL_IMX8MM_USDHC3: + case FSL_IMX8MM_WDOG1 ... FSL_IMX8MM_WDOG3: /* device implemented and treated above */ break; =20 diff --git a/include/hw/arm/fsl-imx8mm.h b/include/hw/arm/fsl-imx8mm.h index f3a3304565..7107e932c6 100644 --- a/include/hw/arm/fsl-imx8mm.h +++ b/include/hw/arm/fsl-imx8mm.h @@ -21,6 +21,7 @@ #include "hw/pci-host/fsl_imx8m_phy.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" +#include "hw/watchdog/wdt_imx2.h" #include "qom/object.h" #include "qemu/units.h" =20 @@ -38,6 +39,7 @@ enum FslImx8mmConfiguration { FSL_IMX8MM_NUM_IRQS =3D 128, FSL_IMX8MM_NUM_UARTS =3D 4, FSL_IMX8MM_NUM_USDHCS =3D 3, + FSL_IMX8MM_NUM_WDTS =3D 3, }; =20 struct FslImx8mmState { @@ -53,6 +55,7 @@ struct FslImx8mmState { IMXI2CState i2c[FSL_IMX8MM_NUM_I2CS]; IMXSerialState uart[FSL_IMX8MM_NUM_UARTS]; SDHCIState usdhc[FSL_IMX8MM_NUM_USDHCS]; + IMX2WdtState wdt[FSL_IMX8MM_NUM_WDTS]; DesignwarePCIEHost pcie; FslImx8mPciePhyState pcie_phy; }; @@ -198,6 +201,10 @@ enum FslImx8mmIrqs { FSL_IMX8MM_GPIO5_LOW_IRQ =3D 72, FSL_IMX8MM_GPIO5_HIGH_IRQ =3D 73, =20 + FSL_IMX8MM_WDOG1_IRQ =3D 78, + FSL_IMX8MM_WDOG2_IRQ =3D 79, + FSL_IMX8MM_WDOG3_IRQ =3D 10, + FSL_IMX8MM_PCI_INTA_IRQ =3D 122, FSL_IMX8MM_PCI_INTB_IRQ =3D 123, FSL_IMX8MM_PCI_INTC_IRQ =3D 124, --=20 2.34.1