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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C From: Luc Michel To: , CC: Luc Michel , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Francisco Iglesias Subject: [PATCH 8/9] target/riscv: RISCVCPUTimeSrcIf: add register_time_change_notifier Date: Fri, 7 Nov 2025 11:23:34 +0100 Message-ID: <20251107102340.471141-9-luc.michel@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251107102340.471141-1-luc.michel@amd.com> References: <20251107102340.471141-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|BN7PPF862C85B20:EE_ X-MS-Office365-Filtering-Correlation-Id: 92e86384-37f3-4920-a886-08de1de7caf3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" Add the register_time_change_notifier method to the RISCVCPUTimeSrcIf interface. This method allows the time source user to register a notifier on tick counter asynchronous modification (i.e., a modification that is not due to the monotonic nature of the counter). This can happen if the time source counter is writable, which is the case of the `time' register of the ACLINT. Use this mechanism in time_helper.c to recompute the sstc timers deadlines. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu-qom.h | 7 +++++++ target/riscv/cpu.h | 1 + target/riscv/time_helper.h | 11 +++++++++++ target/riscv/time_helper.c | 13 +++++++++++++ 4 files changed, 32 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index e5bc23b2ef5..29cb30d23a9 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -90,8 +90,15 @@ struct RISCVCPUTimeSrcIfClass { =20 /** * get_tick_freq: get the tick frequency of this time source. */ uint32_t (*get_tick_freq)(RISCVCPUTimeSrcIf *); + + /* + * register_time_change_notifier: register a notifier which get notifi= ed + * when the value of the free running counter observes a discontinuity + * (e.g., the counter value gets reset to 0). + */ + void (*register_time_change_notifier)(RISCVCPUTimeSrcIf *, Notifier *); }; =20 #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 368b9e2532d..40b198d8d4a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -460,10 +460,11 @@ struct CPUArchState { int64_t last_icount; bool itrigger_enabled; =20 /* machine specific time source interface */ RISCVCPUTimeSrcIf *time_src; + Notifier time_change_notifier; =20 /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ ((((__xlen) & 0xff) << 24) | \ (((__vgein) & 0x3f) << 20) | \ diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index b51fdd96570..074b516f4ad 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -42,6 +42,17 @@ static inline uint32_t riscv_cpu_time_src_get_tick_freq(= RISCVCPUTimeSrcIf *src) =20 g_assert(rctsc->get_tick_freq !=3D NULL); return rctsc->get_tick_freq(src); } =20 +static inline void +riscv_cpu_time_src_register_time_change_notifier(RISCVCPUTimeSrcIf *src, + Notifier *notifier) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + if (rctsc->register_time_change_notifier) { + rctsc->register_time_change_notifier(src, notifier); + } +} + #endif diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 7b493b7a233..b1d7bba1afe 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -181,10 +181,19 @@ void riscv_timer_stce_changed(CPURISCVState *env, boo= l is_m_mode, bool enable) riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP); } } } =20 +static void time_src_ticks_change_cb(Notifier *notifier, void *opaque) +{ + CPURISCVState *env =3D container_of(notifier, CPURISCVState, time_chan= ge_notifier); + + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); +} + void riscv_timer_init(RISCVCPU *cpu) { CPURISCVState *env; =20 if (!cpu) { @@ -200,10 +209,14 @@ void riscv_timer_init(RISCVCPU *cpu) } =20 void riscv_cpu_set_time_src(CPURISCVState *env, RISCVCPUTimeSrcIf *src) { env->time_src =3D src; + env->time_change_notifier.notify =3D time_src_ticks_change_cb; + + riscv_cpu_time_src_register_time_change_notifier(src, + &env->time_change_not= ifier); } =20 static const TypeInfo riscv_cpu_time_src_if_info =3D { .name =3D TYPE_RISCV_CPU_TIME_SRC_IF, .parent =3D TYPE_INTERFACE, --=20 2.51.0