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bh=TLyg2tIbzCGed7Z28p+7QJIGBNjERlHLbng5v7CiLrA=; b=ojHtDS4DFC9EMvBG6e+tNptN4uiurxB461lIdPIePyUPlDU0S2yp7B//zLAD4JUw2MjKcwWsBaA2yhcAFeB0BJOrcMRuqByVIpvtkkDDEpkV1ygAslpBTd/bW5WxrzyGOaqqpf63kSFNaCX4vWMFmHFJG5fjGHfib4Ht3VCT1rU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C From: Luc Michel To: , CC: Luc Michel , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Francisco Iglesias Subject: [PATCH 4/9] target/riscv: add the RISCVCPUTimeSrcIf interface Date: Fri, 7 Nov 2025 11:23:30 +0100 Message-ID: <20251107102340.471141-5-luc.michel@amd.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20251107102340.471141-1-luc.michel@amd.com> References: <20251107102340.471141-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF000044A2:EE_|SA1PR12MB7176:EE_ X-MS-Office365-Filtering-Correlation-Id: b394dfc8-4bb8-4759-8f18-08de1de7c7f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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charset="utf-8" Add the RISCVCPUTimeSrcIf QOM interface to the RISC-V target. This interface aims at replacing the existing env->rdtime_fn callback in the RISC-V CPU env. It allows to query the current number of ticks, and the tick frequency. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu-qom.h | 34 ++++++++++++++++++++++++++++++++++ target/riscv/time_helper.h | 16 ++++++++++++++++ target/riscv/time_helper.c | 13 +++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 75f4e434085..e5bc23b2ef5 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -58,6 +58,40 @@ #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kun= minghu") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) =20 +#define TYPE_RISCV_CPU_TIME_SRC_IF "riscv-cpu-time-src-if" + +typedef struct RISCVCPUTimeSrcIfClass RISCVCPUTimeSrcIfClass; +DECLARE_CLASS_CHECKERS(RISCVCPUTimeSrcIfClass, RISCV_CPU_TIME_SRC_IF, + TYPE_RISCV_CPU_TIME_SRC_IF) +#define RISCV_CPU_TIME_SRC_IF(obj) \ + INTERFACE_CHECK(RISCVCPUTimeSrcIf, (obj), TYPE_RISCV_CPU_TIME_SRC_= IF) + +typedef struct RISCVCPUTimeSrcIf RISCVCPUTimeSrcIf; + +/** + * RISCVCPUTimeSrcIf interface + * + * This interface is used by CPUs implementing the sstc extension. When th= e CPU + * implements this extension, it must have a time source to implement the = sstc + * timers. Devices implementing this interface provide a monotonic tick co= unter + * and the associated tick frequency so that the CPU code can compute timer + * deadlines. + */ +struct RISCVCPUTimeSrcIfClass { + InterfaceClass parent_class; + + /** + * get_ticks: get the current value of the free running counter associ= ated + * with this time source. + */ + uint64_t (*get_ticks)(RISCVCPUTimeSrcIf *); + + /** + * get_tick_freq: get the tick frequency of this time source. + */ + uint32_t (*get_tick_freq)(RISCVCPUTimeSrcIf *); +}; + #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index af1f634f890..b51fdd96570 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -26,6 +26,22 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUT= imer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq); void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool ena= ble); void riscv_timer_init(RISCVCPU *cpu); =20 +static inline uint64_t riscv_cpu_time_src_get_ticks(RISCVCPUTimeSrcIf *src) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + g_assert(rctsc->get_ticks !=3D NULL); + return rctsc->get_ticks(src); +} + +static inline uint32_t riscv_cpu_time_src_get_tick_freq(RISCVCPUTimeSrcIf = *src) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + g_assert(rctsc->get_tick_freq !=3D NULL); + return rctsc->get_tick_freq(src); +} + #endif diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index d2ec8a94166..dc0777607ab 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -198,5 +198,18 @@ void riscv_timer_init(RISCVCPU *cpu) env->stimecmp =3D 0; =20 env->vstimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, c= pu); env->vstimecmp =3D 0; } + +static const TypeInfo riscv_cpu_time_src_if_info =3D { + .name =3D TYPE_RISCV_CPU_TIME_SRC_IF, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(RISCVCPUTimeSrcIfClass), +}; + +static void riscv_cpu_time_src_if_register_types(void) +{ + type_register_static(&riscv_cpu_time_src_if_info); +} + +type_init(riscv_cpu_time_src_if_register_types) --=20 2.51.0