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charset="utf-8" Drop the unused qemu/log.h include directive in time_helper.c Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/time_helper.c | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 400e9173542..d2ec8a94166 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -15,11 +15,10 @@ * You should have received a copy of the GNU General Public License along= with * this program. If not, see . */ =20 #include "qemu/osdep.h" -#include "qemu/log.h" #include "cpu_bits.h" #include "time_helper.h" #include "hw/intc/riscv_aclint.h" =20 static void riscv_vstimer_cb(void *opaque) --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; a=rsa-sha256; t=1762511130; cv=pass; d=zohomail.com; s=zohoarc; b=lLsH60GDcDlryw14Cktpv/PpjO9Zp3xTy6sOhfLQou4lnNXf/Qdr75PUBEFepY7kJoUl27P/MPchdtfGsHPkph6Uvyxkv7CQbcTDnxddGm9oRBLB3h8hklzUW85/vpV1uDJtfDUuY6Paxfc/aM0Ub/fMAS9jTuSPPuQCM1aVYl0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762511130; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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charset="utf-8" Fix coding style in `riscv_aclint_mtimer_class_init' and `riscv_aclint_swi_class_init' functions. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/riscv_aclint.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index c6f13f647ec..5f5ffc61e80 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -342,13 +342,14 @@ static const VMStateDescription vmstate_riscv_mtimer = =3D { }; =20 static void riscv_aclint_mtimer_class_init(ObjectClass *klass, const void = *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + dc->realize =3D riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); - ResettableClass *rc =3D RESETTABLE_CLASS(klass); rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; dc->vmsd =3D &vmstate_riscv_mtimer; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { @@ -528,13 +529,14 @@ static void riscv_aclint_swi_reset_enter(Object *obj,= ResetType type) } =20 static void riscv_aclint_swi_class_init(ObjectClass *klass, const void *da= ta) { DeviceClass *dc =3D DEVICE_CLASS(klass); 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charset="utf-8" For more clarity, rename the cpu_riscv_read_rtc function to riscv_aclint_mtimer_get_ticks: - The ACLINT is the time source here, not the CPU, - This function returns a number of ticks based on the timer frequency. Rename the _raw version of this function as well and the local variables storing the result of those function. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/riscv_aclint.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 5f5ffc61e80..95398e48821 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -38,20 +38,21 @@ typedef struct riscv_aclint_mtimer_callback { RISCVAclintMTimerState *s; int num; } riscv_aclint_mtimer_callback; =20 -static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) +static uint64_t riscv_aclint_mtimer_get_ticks_raw(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), timebase_freq, NANOSECONDS_PER_SECOND); } =20 -static uint64_t cpu_riscv_read_rtc(void *opaque) +static uint64_t riscv_aclint_mtimer_get_ticks(void *opaque) { RISCVAclintMTimerState *mtimer =3D opaque; - return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_de= lta; + return riscv_aclint_mtimer_get_ticks_raw(mtimer->timebase_freq) + + mtimer->time_delta; } =20 /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. @@ -63,28 +64,28 @@ static void riscv_aclint_mtimer_write_timecmp(RISCVAcli= ntMTimerState *mtimer, { uint32_t timebase_freq =3D mtimer->timebase_freq; uint64_t next; uint64_t diff; =20 - uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); + uint64_t ticks =3D riscv_aclint_mtimer_get_ticks(mtimer); =20 /* Compute the relative hartid w.r.t the socket */ hartid =3D hartid - mtimer->hartid_base; =20 mtimer->timecmp[hartid] =3D value; - if (mtimer->timecmp[hartid] <=3D rtc) { + if (mtimer->timecmp[hartid] <=3D ticks) { /* * If we're setting an MTIMECMP value in the "past", * immediately raise the timer interrupt */ qemu_irq_raise(mtimer->timer_irqs[hartid]); return; } =20 /* otherwise, set up the future timer interrupt */ qemu_irq_lower(mtimer->timer_irqs[hartid]); - diff =3D mtimer->timecmp[hartid] - rtc; + diff =3D mtimer->timecmp[hartid] - ticks; /* back to ns (note args switched in muldiv64) */ uint64_t ns_diff =3D muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_f= req); =20 /* * check if ns_diff overflowed and check if the addition would potenti= ally @@ -149,15 +150,15 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque= , hwaddr addr, "aclint-mtimer: invalid read: %08x", (uint32_t)a= ddr); return 0; } } else if (addr =3D=3D mtimer->time_base) { /* time_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); - return (size =3D=3D 4) ? (rtc & 0xFFFFFFFF) : rtc; + uint64_t ticks =3D riscv_aclint_mtimer_get_ticks(mtimer); + return (size =3D=3D 4) ? (ticks & 0xFFFFFFFF) : ticks; } else if (addr =3D=3D mtimer->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; + return (riscv_aclint_mtimer_get_ticks(mtimer) >> 32) & 0xFFFFFFFF; } =20 qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid read: %08x", (uint32_t)addr); return 0; @@ -206,25 +207,25 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, "aclint-mtimer: invalid timecmp write: %08x", (uint32_t)addr); } return; } else if (addr =3D=3D mtimer->time_base || addr =3D=3D mtimer->time_b= ase + 4) { - uint64_t rtc_r =3D cpu_riscv_read_rtc_raw(mtimer->timebase_freq); - uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); + uint64_t ticks_r =3D riscv_aclint_mtimer_get_ticks_raw(mtimer->tim= ebase_freq); + uint64_t ticks =3D riscv_aclint_mtimer_get_ticks(mtimer); =20 if (addr =3D=3D mtimer->time_base) { if (size =3D=3D 4) { /* time_lo for RV32/RV64 */ - mtimer->time_delta =3D ((rtc & ~0xFFFFFFFFULL) | value) - = rtc_r; + mtimer->time_delta =3D ((ticks & ~0xFFFFFFFFULL) | value) = - ticks_r; } else { /* time for RV64 */ - mtimer->time_delta =3D value - rtc_r; + mtimer->time_delta =3D value - ticks_r; } } else { if (size =3D=3D 4) { /* time_hi for RV32/RV64 */ - mtimer->time_delta =3D (value << 32 | (rtc & 0xFFFFFFFF)) = - rtc_r; + mtimer->time_delta =3D (value << 32 | (ticks & 0xFFFFFFFF)= ) - ticks_r; } else { qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid time_hi write: %08x", (uint32_t)addr); return; @@ -395,11 +396,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, = hwaddr size, if (!env) { g_free(cb); continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); + riscv_cpu_set_rdtime_fn(env, riscv_aclint_mtimer_get_ticks, de= v); } =20 cb->s =3D s; cb->num =3D i; s->timers[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Add the RISCVCPUTimeSrcIf QOM interface to the RISC-V target. This interface aims at replacing the existing env->rdtime_fn callback in the RISC-V CPU env. It allows to query the current number of ticks, and the tick frequency. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu-qom.h | 34 ++++++++++++++++++++++++++++++++++ target/riscv/time_helper.h | 16 ++++++++++++++++ target/riscv/time_helper.c | 13 +++++++++++++ 3 files changed, 63 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 75f4e434085..e5bc23b2ef5 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -58,6 +58,40 @@ #define TYPE_RISCV_CPU_XIANGSHAN_KMH RISCV_CPU_TYPE_NAME("xiangshan-kun= minghu") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") =20 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) =20 +#define TYPE_RISCV_CPU_TIME_SRC_IF "riscv-cpu-time-src-if" + +typedef struct RISCVCPUTimeSrcIfClass RISCVCPUTimeSrcIfClass; +DECLARE_CLASS_CHECKERS(RISCVCPUTimeSrcIfClass, RISCV_CPU_TIME_SRC_IF, + TYPE_RISCV_CPU_TIME_SRC_IF) +#define RISCV_CPU_TIME_SRC_IF(obj) \ + INTERFACE_CHECK(RISCVCPUTimeSrcIf, (obj), TYPE_RISCV_CPU_TIME_SRC_= IF) + +typedef struct RISCVCPUTimeSrcIf RISCVCPUTimeSrcIf; + +/** + * RISCVCPUTimeSrcIf interface + * + * This interface is used by CPUs implementing the sstc extension. When th= e CPU + * implements this extension, it must have a time source to implement the = sstc + * timers. Devices implementing this interface provide a monotonic tick co= unter + * and the associated tick frequency so that the CPU code can compute timer + * deadlines. + */ +struct RISCVCPUTimeSrcIfClass { + InterfaceClass parent_class; + + /** + * get_ticks: get the current value of the free running counter associ= ated + * with this time source. + */ + uint64_t (*get_ticks)(RISCVCPUTimeSrcIf *); + + /** + * get_tick_freq: get the tick frequency of this time source. + */ + uint32_t (*get_tick_freq)(RISCVCPUTimeSrcIf *); +}; + #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index af1f634f890..b51fdd96570 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -26,6 +26,22 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUT= imer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq); void riscv_timer_stce_changed(CPURISCVState *env, bool is_m_mode, bool ena= ble); void riscv_timer_init(RISCVCPU *cpu); =20 +static inline uint64_t riscv_cpu_time_src_get_ticks(RISCVCPUTimeSrcIf *src) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + g_assert(rctsc->get_ticks !=3D NULL); + return rctsc->get_ticks(src); +} + +static inline uint32_t riscv_cpu_time_src_get_tick_freq(RISCVCPUTimeSrcIf = *src) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + g_assert(rctsc->get_tick_freq !=3D NULL); + return rctsc->get_tick_freq(src); +} + #endif diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index d2ec8a94166..dc0777607ab 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -198,5 +198,18 @@ void riscv_timer_init(RISCVCPU *cpu) env->stimecmp =3D 0; =20 env->vstimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, c= pu); env->vstimecmp =3D 0; } + +static const TypeInfo riscv_cpu_time_src_if_info =3D { + .name =3D TYPE_RISCV_CPU_TIME_SRC_IF, + .parent =3D TYPE_INTERFACE, + .class_size =3D sizeof(RISCVCPUTimeSrcIfClass), +}; + +static void riscv_cpu_time_src_if_register_types(void) +{ + type_register_static(&riscv_cpu_time_src_if_info); +} + +type_init(riscv_cpu_time_src_if_register_types) --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" Implement the RISCVCPUTimeSrcIf QOM interface in the ACLINT mtimer device model. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/riscv_aclint.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 95398e48821..4a4449d9d2f 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -325,10 +325,25 @@ static void riscv_aclint_mtimer_reset_enter(Object *o= bj, ResetType type) * Pending mtime interrupts will also be cleared at the same time. */ riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); } =20 +static uint64_t riscv_aclint_mtimer_time_src_get_ticks(RISCVCPUTimeSrcIf *= iface) +{ + RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(iface); + + return riscv_aclint_mtimer_get_ticks(mtimer); +} + +static uint32_t riscv_aclint_mtimer_time_src_get_tick_freq(RISCVCPUTimeSrc= If *iface) +{ + RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(iface); + + return mtimer->timebase_freq; +} + + static const VMStateDescription vmstate_riscv_mtimer =3D { .name =3D "riscv_mtimer", .version_id =3D 3, .minimum_version_id =3D 3, .fields =3D (const VMStateField[]) { @@ -344,22 +359,29 @@ static const VMStateDescription vmstate_riscv_mtimer = =3D { =20 static void riscv_aclint_mtimer_class_init(ObjectClass *klass, const void = *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); ResettableClass *rc =3D RESETTABLE_CLASS(klass); + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_CLASS(klass); =20 dc->realize =3D riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; dc->vmsd =3D &vmstate_riscv_mtimer; + rctsc->get_ticks =3D riscv_aclint_mtimer_time_src_get_ticks; + rctsc->get_tick_freq =3D riscv_aclint_mtimer_time_src_get_tick_freq; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { .name =3D TYPE_RISCV_ACLINT_MTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(RISCVAclintMTimerState), .class_init =3D riscv_aclint_mtimer_class_init, + .interfaces =3D (const InterfaceInfo []) { + { TYPE_RISCV_CPU_TIME_SRC_IF }, + { }, + }, }; =20 /* * Create ACLINT MTIMER device. */ --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Replace the env->rdtime_fn function pointer with an instance of the RISCVCPUTimeSrcIf QOM interface. This allows to remove the dependency on the ACLINT in the riscv_timer_write_timecmp function: - This dependency was buggy because env->rdtime_fn_arg was an opaque pointer and was converted in riscv_timer_write_timecmp to a ACLINT without dynamic type check. - This will allow to have time sources provided by other devices than an ACLINT. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/riscv/cpu.h | 8 +++----- hw/intc/riscv_aclint.c | 2 +- target/riscv/cpu_helper.c | 7 ------- target/riscv/csr.c | 24 ++++++++++++------------ target/riscv/time_helper.c | 15 +++++++++------ 5 files changed, 25 insertions(+), 31 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 36e7f100374..368b9e2532d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -458,13 +458,12 @@ struct CPUArchState { struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; int64_t last_icount; bool itrigger_enabled; =20 - /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(void *); - void *rdtime_fn_arg; + /* machine specific time source interface */ + RISCVCPUTimeSrcIf *time_src; =20 /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ ((((__xlen) & 0xff) << 24) | \ (((__vgein) & 0x3f) << 20) | \ @@ -642,12 +641,11 @@ int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_= t interrupts); uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, uint64_t value); void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); void riscv_cpu_interrupt(CPURISCVState *env); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), - void *arg); +void riscv_cpu_set_time_src(CPURISCVState *env, RISCVCPUTimeSrcIf *src); void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, int (*rmw_fn)(void *arg, target_ulong reg, target_ulong *val, target_ulong new_val, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 4a4449d9d2f..8d001a5eb20 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -418,11 +418,11 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, = hwaddr size, if (!env) { g_free(cb); continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, riscv_aclint_mtimer_get_ticks, de= v); + riscv_cpu_set_time_src(env, RISCV_CPU_TIME_SRC_IF(dev)); } =20 cb->s =3D s; cb->num =3D i; s->timers[i] =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c4fb68b5de8..f642ec80b31 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -757,17 +757,10 @@ uint64_t riscv_cpu_update_mip(CPURISCVState *env, uin= t64_t mask, uint64_t value) riscv_cpu_interrupt(env); =20 return old; } =20 -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), - void *arg) -{ - env->rdtime_fn =3D fn; - env->rdtime_fn_arg =3D arg; -} - void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, int (*rmw_fn)(void *arg, target_ulong reg, target_ulong *val, target_ulong new_val, diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c91658c3dc..583f646460c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -572,11 +572,11 @@ static RISCVException sstateen(CPURISCVState *env, in= t csrno) =20 static RISCVException sstc(CPURISCVState *env, int csrno) { bool hmode_check =3D false; =20 - if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn) { + if (!riscv_cpu_cfg(env)->ext_sstc || !env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 if ((csrno =3D=3D CSR_VSTIMECMP) || (csrno =3D=3D CSR_VSTIMECMPH)) { hmode_check =3D true; @@ -1634,28 +1634,28 @@ static RISCVException read_scountovf(CPURISCVState = *env, int csrno, static RISCVException read_time(CPURISCVState *env, int csrno, target_ulong *val) { uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 - *val =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; + *val =3D riscv_cpu_time_src_get_ticks(env->time_src) + delta; return RISCV_EXCP_NONE; } =20 static RISCVException read_timeh(CPURISCVState *env, int csrno, target_ulong *val) { uint64_t delta =3D env->virt_enabled ? env->htimedelta : 0; =20 - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 - *val =3D (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; + *val =3D (riscv_cpu_time_src_get_ticks(env->time_src) + delta) >> 32; return RISCV_EXCP_NONE; } =20 static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, target_ulong *val) @@ -4965,60 +4965,60 @@ static RISCVException write_hgatp(CPURISCVState *en= v, int csrno, } =20 static RISCVException read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val) { - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta; return RISCV_EXCP_NONE; } =20 static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->htimedelta =3D deposit64(env->htimedelta, 0, 32, (uint64_t)va= l); } else { env->htimedelta =3D val; } =20 - if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + if (riscv_cpu_cfg(env)->ext_sstc) { riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 return RISCV_EXCP_NONE; } =20 static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val) { - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 *val =3D env->htimedelta >> 32; return RISCV_EXCP_NONE; } =20 static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val, uintptr_t ra) { - if (!env->rdtime_fn) { + if (!env->time_src) { return RISCV_EXCP_ILLEGAL_INST; } =20 env->htimedelta =3D deposit64(env->htimedelta, 32, 32, (uint64_t)val); =20 - if (riscv_cpu_cfg(env)->ext_sstc && env->rdtime_fn) { + if (riscv_cpu_cfg(env)->ext_sstc) { riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, env->htimedelta, MIP_VSTIP); } =20 return RISCV_EXCP_NONE; @@ -5825,11 +5825,11 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_CYCLEH] =3D { "cycleh", ctr32, read_hpmcounterh }, [CSR_INSTRETH] =3D { "instreth", ctr32, read_hpmcounterh }, =20 /* * In privileged mode, the monitor will have to emulate TIME CSRs only= if - * rdtime callback is not provided by machine/platform emulation. + * CPU time source interface is not provided by machine/platform emula= tion. */ [CSR_TIME] =3D { "time", ctr, read_time }, [CSR_TIMEH] =3D { "timeh", ctr32, read_timeh }, =20 /* Crypto Extension */ diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index dc0777607ab..7b493b7a233 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -17,11 +17,10 @@ */ =20 #include "qemu/osdep.h" #include "cpu_bits.h" #include "time_helper.h" -#include "hw/intc/riscv_aclint.h" =20 static void riscv_vstimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; CPURISCVState *env =3D &cpu->env; @@ -42,28 +41,27 @@ static void riscv_stimer_cb(void *opaque) void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer, uint64_t timecmp, uint64_t delta, uint32_t timer_irq) { uint64_t diff, ns_diff, next; - RISCVAclintMTimerState *mtimer =3D env->rdtime_fn_arg; uint32_t timebase_freq; uint64_t rtc_r; =20 - if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn || - !env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) { + if (!riscv_cpu_cfg(env)->ext_sstc || !env->time_src || + !get_field(env->menvcfg, MENVCFG_STCE)) { /* S/VS Timer IRQ depends on sstc extension, rdtime_fn(), and STCE= . */ return; } =20 if (timer_irq =3D=3D MIP_VSTIP && (!riscv_has_ext(env, RVH) || !get_field(env->henvcfg, HENVCFG_STCE= ))) { /* VS Timer IRQ also depends on RVH and henvcfg.STCE. */ return; } =20 - timebase_freq =3D mtimer->timebase_freq; - rtc_r =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; + timebase_freq =3D riscv_cpu_time_src_get_tick_freq(env->time_src); + rtc_r =3D riscv_cpu_time_src_get_ticks(env->time_src) + delta; =20 if (timecmp <=3D rtc_r) { /* * If we're setting an stimecmp value in the "past", * immediately raise the timer interrupt @@ -199,10 +197,15 @@ void riscv_timer_init(RISCVCPU *cpu) =20 env->vstimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, c= pu); env->vstimecmp =3D 0; } =20 +void riscv_cpu_set_time_src(CPURISCVState *env, RISCVCPUTimeSrcIf *src) +{ + env->time_src =3D src; +} + static const TypeInfo riscv_cpu_time_src_if_info =3D { .name =3D TYPE_RISCV_CPU_TIME_SRC_IF, .parent =3D TYPE_INTERFACE, .class_size =3D sizeof(RISCVCPUTimeSrcIfClass), }; --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1 dmarc=pass fromdomain=amd.com); dmarc=pass(p=quarantine dis=none) header.from=amd.com ARC-Seal: i=2; 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charset="utf-8" Now that the riscv_aclint_mtimer_get_ticks is only used internally, replace its void* argument with the proper RISCVAclintMTimerState type. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/intc/riscv_aclint.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 8d001a5eb20..014b733d72f 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -44,13 +44,12 @@ static uint64_t riscv_aclint_mtimer_get_ticks_raw(uint3= 2_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), timebase_freq, NANOSECONDS_PER_SECOND); } =20 -static uint64_t riscv_aclint_mtimer_get_ticks(void *opaque) +static uint64_t riscv_aclint_mtimer_get_ticks(RISCVAclintMTimerState *mtim= er) { - RISCVAclintMTimerState *mtimer =3D opaque; return riscv_aclint_mtimer_get_ticks_raw(mtimer->timebase_freq) + mtimer->time_delta; } =20 /* --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Add the register_time_change_notifier method to the RISCVCPUTimeSrcIf interface. This method allows the time source user to register a notifier on tick counter asynchronous modification (i.e., a modification that is not due to the monotonic nature of the counter). This can happen if the time source counter is writable, which is the case of the `time' register of the ACLINT. Use this mechanism in time_helper.c to recompute the sstc timers deadlines. Signed-off-by: Luc Michel --- target/riscv/cpu-qom.h | 7 +++++++ target/riscv/cpu.h | 1 + target/riscv/time_helper.h | 11 +++++++++++ target/riscv/time_helper.c | 13 +++++++++++++ 4 files changed, 32 insertions(+) diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index e5bc23b2ef5..29cb30d23a9 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -90,8 +90,15 @@ struct RISCVCPUTimeSrcIfClass { =20 /** * get_tick_freq: get the tick frequency of this time source. */ uint32_t (*get_tick_freq)(RISCVCPUTimeSrcIf *); + + /* + * register_time_change_notifier: register a notifier which get notifi= ed + * when the value of the free running counter observes a discontinuity + * (e.g., the counter value gets reset to 0). + */ + void (*register_time_change_notifier)(RISCVCPUTimeSrcIf *, Notifier *); }; =20 #endif /* RISCV_CPU_QOM_H */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 368b9e2532d..40b198d8d4a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -460,10 +460,11 @@ struct CPUArchState { int64_t last_icount; bool itrigger_enabled; =20 /* machine specific time source interface */ RISCVCPUTimeSrcIf *time_src; + Notifier time_change_notifier; =20 /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ ((((__xlen) & 0xff) << 24) | \ (((__vgein) & 0x3f) << 20) | \ diff --git a/target/riscv/time_helper.h b/target/riscv/time_helper.h index b51fdd96570..074b516f4ad 100644 --- a/target/riscv/time_helper.h +++ b/target/riscv/time_helper.h @@ -42,6 +42,17 @@ static inline uint32_t riscv_cpu_time_src_get_tick_freq(= RISCVCPUTimeSrcIf *src) =20 g_assert(rctsc->get_tick_freq !=3D NULL); return rctsc->get_tick_freq(src); } =20 +static inline void +riscv_cpu_time_src_register_time_change_notifier(RISCVCPUTimeSrcIf *src, + Notifier *notifier) +{ + RISCVCPUTimeSrcIfClass *rctsc =3D RISCV_CPU_TIME_SRC_IF_GET_CLASS(src); + + if (rctsc->register_time_change_notifier) { + rctsc->register_time_change_notifier(src, notifier); + } +} + #endif diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 7b493b7a233..b1d7bba1afe 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -181,10 +181,19 @@ void riscv_timer_stce_changed(CPURISCVState *env, boo= l is_m_mode, bool enable) riscv_timer_disable_timecmp(env, env->stimer, MIP_STIP); } } } =20 +static void time_src_ticks_change_cb(Notifier *notifier, void *opaque) +{ + CPURISCVState *env =3D container_of(notifier, CPURISCVState, time_chan= ge_notifier); + + riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, MIP_STIP= ); + riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); +} + void riscv_timer_init(RISCVCPU *cpu) { CPURISCVState *env; =20 if (!cpu) { @@ -200,10 +209,14 @@ void riscv_timer_init(RISCVCPU *cpu) } =20 void riscv_cpu_set_time_src(CPURISCVState *env, RISCVCPUTimeSrcIf *src) { env->time_src =3D src; + env->time_change_notifier.notify =3D time_src_ticks_change_cb; + + riscv_cpu_time_src_register_time_change_notifier(src, + &env->time_change_not= ifier); } =20 static const TypeInfo riscv_cpu_time_src_if_info =3D { .name =3D TYPE_RISCV_CPU_TIME_SRC_IF, .parent =3D TYPE_INTERFACE, --=20 2.51.0 From nobody Fri Nov 14 15:21:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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charset="utf-8" Implement the register_time_change_notifier method of the RISCVCPUTimeSrcIf interface in the ACLINT. Keep a notifier list and notify it upon `time' register modification. This effectively replaces the explicit calls to the internal riscv_timer_write_timecmp CPU functions as this is now done by the corresponding CPU notifier. Signed-off-by: Luc Michel --- include/hw/intc/riscv_aclint.h | 1 + hw/intc/riscv_aclint.c | 16 +++++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 4b7406eec00..3451aa1786b 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -32,10 +32,11 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; uint64_t time_delta; uint64_t *timecmp; QEMUTimer **timers; + NotifierList time_change_notifiers; =20 /*< public >*/ MemoryRegion mmio; uint32_t hartid_base; uint32_t num_harts; diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 014b733d72f..f5e120cc853 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -26,11 +26,10 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" -#include "target/riscv/time_helper.h" #include "hw/qdev-properties.h" #include "hw/intc/riscv_aclint.h" #include "qemu/timer.h" #include "hw/irq.h" #include "migration/vmstate.h" @@ -239,15 +238,13 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, continue; } riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), mtimer->hartid_base + i, mtimer->timecmp[i]); - riscv_timer_write_timecmp(env, env->stimer, env->stimecmp, 0, = MIP_STIP); - riscv_timer_write_timecmp(env, env->vstimer, env->vstimecmp, - env->htimedelta, MIP_VSTIP); - } + + notifier_list_notify(&mtimer->time_change_notifiers, NULL); return; } =20 qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid write: %08x", (uint32_t)addr); @@ -284,10 +281,11 @@ static const Property riscv_aclint_mtimer_properties[= ] =3D { static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) { RISCVAclintMTimerState *s =3D RISCV_ACLINT_MTIMER(dev); int i; =20 + notifier_list_init(&s->time_change_notifiers); memory_region_init_io(&s->mmio, OBJECT(dev), &riscv_aclint_mtimer_ops, s, TYPE_RISCV_ACLINT_MTIMER, s->aperture_size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); =20 s->timer_irqs =3D g_new(qemu_irq, s->num_harts); @@ -338,10 +336,17 @@ static uint32_t riscv_aclint_mtimer_time_src_get_tick= _freq(RISCVCPUTimeSrcIf *if RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(iface); =20 return mtimer->timebase_freq; } =20 +static void mtimer_time_src_register_change_notifier(RISCVCPUTimeSrcIf *if= ace, + Notifier *notifier) +{ + RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(iface); + + notifier_list_add(&mtimer->time_change_notifiers, notifier); +} =20 static const VMStateDescription vmstate_riscv_mtimer =3D { .name =3D "riscv_mtimer", .version_id =3D 3, .minimum_version_id =3D 3, @@ -366,10 +371,11 @@ static void riscv_aclint_mtimer_class_init(ObjectClas= s *klass, const void *data) device_class_set_props(dc, riscv_aclint_mtimer_properties); rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; dc->vmsd =3D &vmstate_riscv_mtimer; rctsc->get_ticks =3D riscv_aclint_mtimer_time_src_get_ticks; rctsc->get_tick_freq =3D riscv_aclint_mtimer_time_src_get_tick_freq; + rctsc->register_time_change_notifier =3D mtimer_time_src_register_chan= ge_notifier; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { .name =3D TYPE_RISCV_ACLINT_MTIMER, .parent =3D TYPE_SYS_BUS_DEVICE, --=20 2.51.0