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c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1762696639; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=s4NQAtf7TbdXclJV1DiwxB4R+oO7azwdGGte+itj1sw=; b=csRLnWYIl9KZKX9I2c/wAHAs+Lc+5HM6KjCdd4LBz3OtuQZE5SUUo+2AOd84hvx5UXhgTP aYBBnyytA/Is+rdlFpf2cqpP7pzwBlEGLnUsdWAANQS2oqmtR8Cv4uZXzrZ8vsPKLl+202 j5umYYT44X4yajpE4+E55oncfhq6Dnc= X-MC-Unique: a6iYOrxgPJabp4T-rS3JwQ-1 X-Mimecast-MFC-AGG-ID: a6iYOrxgPJabp4T-rS3JwQ_1762696636 From: Stefan Hajnoczi To: qemu-devel@nongnu.org Cc: Manos Pitsidianakis , Zhao Liu , Paolo Bonzini , qemu-rust@nongnu.org, Stefan Hajnoczi Subject: [PATCH 2/2] rust/hpet: add trace events Date: Thu, 6 Nov 2025 16:56:06 -0500 Message-ID: <20251106215606.36598-3-stefanha@redhat.com> In-Reply-To: <20251106215606.36598-1-stefanha@redhat.com> References: <20251106215606.36598-1-stefanha@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.4 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Implement the same trace events as the C implementation. Notes: - Keep order of hpet_ram_write_invalid_tn_cmp and hpet_ram_write_tn_cmp the same as the C implementation. - Put hpet_ram_write_timer_id in HPETTimer::write() instead of HPETState::decode() so that reads can be excluded. Signed-off-by: Stefan Hajnoczi Reviewed-by: Manos Pitsidianakis --- rust/hw/timer/hpet/Cargo.toml | 1 + rust/hw/timer/hpet/meson.build | 1 + rust/hw/timer/hpet/src/device.rs | 45 +++++++++++++++++++------------- 3 files changed, 29 insertions(+), 18 deletions(-) diff --git a/rust/hw/timer/hpet/Cargo.toml b/rust/hw/timer/hpet/Cargo.toml index f781b28d8b..5567eefda4 100644 --- a/rust/hw/timer/hpet/Cargo.toml +++ b/rust/hw/timer/hpet/Cargo.toml @@ -18,6 +18,7 @@ bql =3D { path =3D "../../../bql" } qom =3D { path =3D "../../../qom" } system =3D { path =3D "../../../system" } hwcore =3D { path =3D "../../../hw/core" } +trace =3D { path =3D "../../../trace" } =20 [lints] workspace =3D true diff --git a/rust/hw/timer/hpet/meson.build b/rust/hw/timer/hpet/meson.build index bb64b96672..465995bb5a 100644 --- a/rust/hw/timer/hpet/meson.build +++ b/rust/hw/timer/hpet/meson.build @@ -11,6 +11,7 @@ _libhpet_rs =3D static_library( qom_rs, system_rs, hwcore_rs, + trace_rs ], ) =20 diff --git a/rust/hw/timer/hpet/src/device.rs b/rust/hw/timer/hpet/src/devi= ce.rs index 3564aa79c6..90b0ae927c 100644 --- a/rust/hw/timer/hpet/src/device.rs +++ b/rust/hw/timer/hpet/src/device.rs @@ -32,6 +32,8 @@ =20 use crate::fw_cfg::HPETFwConfig; =20 +::trace::include_trace!("hw_timer"); + /// Register space for each timer block (`HPET_BASE` is defined in hpet.h). const HPET_REG_SPACE_LEN: u64 =3D 0x400; // 1024 bytes =20 @@ -402,7 +404,8 @@ fn del_timer(&mut self) { =20 /// Configuration and Capability Register fn set_tn_cfg_reg(&mut self, shift: u32, len: u32, val: u64) { - // TODO: Add trace point - trace_hpet_ram_write_tn_cfg(addr & 4) + trace::trace_hpet_ram_write_tn_cfg((shift / 8).try_into().unwrap()= ); + let old_val: u64 =3D self.config; let mut new_val: u64 =3D old_val.deposit(shift, len, val); new_val =3D hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MAS= K); @@ -435,17 +438,18 @@ fn set_tn_cmp_reg(&mut self, shift: u32, len: u32, va= l: u64) { let mut length =3D len; let mut value =3D val; =20 - // TODO: Add trace point - trace_hpet_ram_write_tn_cmp(addr & 4) if self.is_32bit_mod() { // High 32-bits are zero, leave them untouched. if shift !=3D 0 { - // TODO: Add trace point - trace_hpet_ram_write_invalid_tn= _cmp() + trace::trace_hpet_ram_write_invalid_tn_cmp(); return; } length =3D 64; value =3D u64::from(value as u32); // truncate! } =20 + trace::trace_hpet_ram_write_tn_cmp((shift / 8).try_into().unwrap()= ); + if !self.is_periodic() || self.is_valset_enabled() { self.cmp =3D self.cmp.deposit(shift, length, value); } @@ -512,6 +516,9 @@ const fn read(&self, reg: TimerRegister) -> u64 { =20 fn write(&mut self, reg: TimerRegister, value: u64, shift: u32, len: u= 32) { use TimerRegister::*; + + trace::trace_hpet_ram_write_timer_id(self.index as u64); + match reg { CFG =3D> self.set_tn_cfg_reg(shift, len, value), CMP =3D> self.set_tn_cmp_reg(shift, len, value), @@ -689,15 +696,13 @@ fn set_int_status_reg(&self, shift: u32, _len: u32, v= al: u64) { /// Main Counter Value Register fn set_counter_reg(&self, shift: u32, len: u32, val: u64) { if self.is_hpet_enabled() { - // TODO: Add trace point - - // trace_hpet_ram_write_counter_write_while_enabled() - // // HPET spec says that writes to this register should only be // done while the counter is halted. So this is an undefined // behavior. There's no need to forbid it, but when HPET is // enabled, the changed counter value will not affect the // tick count (i.e., the previously calculated offset will // not be changed as well). + trace::trace_hpet_ram_write_counter_write_while_enabled(); } self.counter .set(self.counter.get().deposit(shift, len, val)); @@ -787,11 +792,10 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPET= AddrDecode<'_> { } else { let timer_id: usize =3D ((addr - 0x100) / 0x20) as usize; if timer_id < self.num_timers { - // TODO: Add trace point - trace_hpet_ram_[read|write]_tim= er_id(timer_id) TimerRegister::try_from(addr & 0x18) .map(|reg| HPETRegister::Timer(&self.timers[timer_id],= reg)) } else { - // TODO: Add trace point - trace_hpet_timer_id_out_of_ran= ge(timer_id) + trace::trace_hpet_timer_id_out_of_range(timer_id.try_into(= ).unwrap()); Err(addr) } }; @@ -803,7 +807,8 @@ fn decode(&self, mut addr: hwaddr, size: u32) -> HPETAd= drDecode<'_> { } =20 fn read(&self, addr: hwaddr, size: u32) -> u64 { - // TODO: Add trace point - trace_hpet_ram_read(addr) + trace::trace_hpet_ram_read(addr); + let HPETAddrDecode { shift, reg, .. } =3D self.decode(addr, size); =20 use GlobalRegister::*; @@ -814,16 +819,21 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 { Global(CFG) =3D> self.config.get(), Global(INT_STATUS) =3D> self.int_status.get(), Global(COUNTER) =3D> { - // TODO: Add trace point - // trace_hpet_ram_read_reading_counter(addr & 4, cur_tick) - if self.is_hpet_enabled() { + let cur_tick =3D if self.is_hpet_enabled() { self.get_ticks() } else { self.counter.get() - } + }; + + trace::trace_hpet_ram_read_reading_counter( + (addr & 4) as u8, + cur_tick + ); + + cur_tick } Unknown(_) =3D> { - // TODO: Add trace point- trace_hpet_ram_read_invalid() + trace::trace_hpet_ram_read_invalid(); 0 } }) >> shift @@ -832,7 +842,8 @@ fn read(&self, addr: hwaddr, size: u32) -> u64 { fn write(&self, addr: hwaddr, value: u64, size: u32) { let HPETAddrDecode { shift, len, reg } =3D self.decode(addr, size); =20 - // TODO: Add trace point - trace_hpet_ram_write(addr, value) + trace::trace_hpet_ram_write(addr, value); + use GlobalRegister::*; use HPETRegister::*; match reg { @@ -841,9 +852,7 @@ fn write(&self, addr: hwaddr, value: u64, size: u32) { Global(CFG) =3D> self.set_cfg_reg(shift, len, value), Global(INT_STATUS) =3D> self.set_int_status_reg(shift, len, va= lue), Global(COUNTER) =3D> self.set_counter_reg(shift, len, value), - Unknown(_) =3D> { - // TODO: Add trace point - trace_hpet_ram_write_invalid() - } + Unknown(_) =3D> trace::trace_hpet_ram_write_invalid(), } } =20 --=20 2.51.1