From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419025; cv=none; d=zohomail.com; s=zohoarc; b=dGPrM4woTeqyw5JHmX2mbPtYyh9lYMxH6pdQaQm1ttaqXC7xJrnmC7Ue0XTSJSuK6uNld8GxVWcaYA3zy+UYAMSxj6Pcq5xJY9vr5MF7t8l4oqW6uMAa3Hdfnqp/dUT6ob7hUmBx+IWzkZrC46KrAGqohAHNL26tl46XLxHbdy8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762419025; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=H5nn6aPSuVbQ9j7SUP9btTx+BFaAQEG41snu8FEZXpo=; b=E21NByN2mWqaoEdcowdLwKETq5ioKUqArGrrY1uB8OBsn6sJasjiDU8ezXI3jSOMS+GeQT/MvRhEk4TFQ2e9WnY8avzWNfWNgWzl6n9Jc5gUyzCPlYkb8dksFOmuVhtgqsLrC0qXukrXx0FRgibe3rpECUEQ7BAR2mNiBP03rAo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762419025294585.3096367528407; Thu, 6 Nov 2025 00:50:25 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvga-0002xi-Qk; Thu, 06 Nov 2025 03:49:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgZ-0002vw-2f; Thu, 06 Nov 2025 03:49:39 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgX-0005Sg-ES; Thu, 06 Nov 2025 03:49:38 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:25 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:25 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 01/12] hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure Date: Thu, 6 Nov 2025 16:49:10 +0800 Message-ID: <20251106084925.1253704-2-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419030688158500 Content-Type: text/plain; charset="utf-8" It did not connect SPI IRQ to the Interrupt Controller, so even the SPI model raised the IRQ, the interrupt was not received. The CPU therefore did not trigger an interrupt via the controller, and the firmware never received the interrupt. Fixes: 356b230ed13889e09d087a96498887de695df17e ("aspeed/soc: Add AST1030 s= upport") Fixes: f25c0ae1079dc0b9de02676eb3e3949a09df9f41 ("aspeed/soc: Add AST2600 s= upport") Fixes: 5dd883ab0635c9f715c77cc32622e458a0724581 ("aspeed/soc: Add AST2700 s= upport") Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 2 ++ hw/arm/aspeed_ast2600.c | 2 ++ hw/arm/aspeed_ast27x0.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 7f49c13391..ca487774ae 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -372,6 +372,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) sc->memmap[ASPEED_DEV_SPI1 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_SPI1 += i)); } =20 /* Secure Boot Controller */ diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 498d1ecc07..4c5a42ea17 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -557,6 +557,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev= , Error **errp) sc->memmap[ASPEED_DEV_SPI1 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast2600_get_irq(s, ASPEED_DEV_SPI1 += i)); } =20 /* EHCI */ diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c index c484bcd4e2..e02a674b13 100644 --- a/hw/arm/aspeed_ast27x0.c +++ b/hw/arm/aspeed_ast27x0.c @@ -831,6 +831,8 @@ static void aspeed_soc_ast2700_realize(DeviceState *dev= , Error **errp) sc->memmap[ASPEED_DEV_SPI0 + i]); aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 1, ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_bas= e); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0, + aspeed_soc_ast2700_get_irq(s, ASPEED_DEV_SPI0 += i)); } =20 /* EHCI */ --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 17624190142991004.7394012818933; Thu, 6 Nov 2025 00:50:14 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvge-000339-Ge; Thu, 06 Nov 2025 03:49:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgc-00030T-0C; Thu, 06 Nov 2025 03:49:42 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvga-0005Sg-8M; Thu, 06 Nov 2025 03:49:41 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 02/12] hw/block/m25p80: Add SFDP table for Winbond W25Q02JVM flash Date: Thu, 6 Nov 2025 16:49:11 +0800 Message-ID: <20251106084925.1253704-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419016578154100 Content-Type: text/plain; charset="utf-8" Add the SFDP data table for Winbond W25Q02JVM flash device. The table was generated under Linux kernel by dumping the SFDP content using the following command: ``` hexdump -v -e '8/1 "0x%02x, " "\n"' \ /sys/bus/spi/devices/spi0.0/spi-nor/sfdp ``` Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/block/m25p80_sfdp.h | 1 + hw/block/m25p80.c | 2 ++ hw/block/m25p80_sfdp.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/hw/block/m25p80_sfdp.h b/hw/block/m25p80_sfdp.h index 35785686a0..c1e532de5a 100644 --- a/hw/block/m25p80_sfdp.h +++ b/hw/block/m25p80_sfdp.h @@ -27,6 +27,7 @@ uint8_t m25p80_sfdp_w25q256(uint32_t addr); uint8_t m25p80_sfdp_w25q512jv(uint32_t addr); uint8_t m25p80_sfdp_w25q80bl(uint32_t addr); uint8_t m25p80_sfdp_w25q01jvq(uint32_t addr); +uint8_t m25p80_sfdp_w25q02jvm(uint32_t addr); =20 uint8_t m25p80_sfdp_is25wp256(uint32_t addr); =20 diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index a5336d92ff..338e17bf1d 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -364,6 +364,8 @@ static const FlashPartInfo known_devices[] =3D { .sfdp_read =3D m25p80_sfdp_w25q512jv }, { INFO("w25q01jvq", 0xef4021, 0, 64 << 10, 2048, ER_4K), .sfdp_read =3D m25p80_sfdp_w25q01jvq }, + { INFO("w25q02jvm", 0xef7022, 0, 64 << 10, 4096, ER_4K), + .sfdp_read =3D m25p80_sfdp_w25q02jvm }, =20 /* Microchip */ { INFO("25csm04", 0x29cc00, 0x100, 64 << 10, 8, 0) }, diff --git a/hw/block/m25p80_sfdp.c b/hw/block/m25p80_sfdp.c index a03a291a09..87878c2bf0 100644 --- a/hw/block/m25p80_sfdp.c +++ b/hw/block/m25p80_sfdp.c @@ -440,6 +440,42 @@ static const uint8_t sfdp_w25q80bl[] =3D { }; define_sfdp_read(w25q80bl); =20 +static const uint8_t sfdp_w25q02jvm[] =3D { + 0x53, 0x46, 0x44, 0x50, 0x06, 0x01, 0x01, 0xff, + 0x00, 0x06, 0x01, 0x10, 0x80, 0x00, 0x00, 0xff, + 0x84, 0x00, 0x01, 0x02, 0xd0, 0x00, 0x00, 0xff, + 0x03, 0x00, 0x01, 0x02, 0xf0, 0x00, 0x00, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xe5, 0x20, 0xfb, 0xff, 0xff, 0xff, 0xff, 0x7f, + 0x44, 0xeb, 0x08, 0x6b, 0x08, 0x3b, 0x42, 0xbb, + 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, + 0xff, 0xff, 0x40, 0xeb, 0x0c, 0x20, 0x0f, 0x52, + 0x10, 0xd8, 0x00, 0x00, 0x36, 0x02, 0xa6, 0x00, + 0x82, 0xea, 0x14, 0xe2, 0xe9, 0x63, 0x76, 0x33, + 0x7a, 0x75, 0x7a, 0x75, 0xf7, 0xa2, 0xd5, 0x5c, + 0x19, 0xf7, 0x4d, 0xff, 0xe9, 0x70, 0xf9, 0xa5, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0x0a, 0xf0, 0xff, 0x21, 0xff, 0xdc, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +}; +define_sfdp_read(w25q02jvm); + /* * Integrated Silicon Solution (ISSI) */ --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419112; cv=none; d=zohomail.com; s=zohoarc; b=joVaPn4WKR8lcdEi9Xk/FOJYQ+DxHGuKrbbkZw3i4b48U6dBcKc/HFUOZqLDMrdpy0GVLX+KlAcLw7wm9PeUcF5LMoiTsIVD2eIAjkXjTQj5LN1cMVPOdR+XdPhWXhe4iyjpiRydni+VNNi1v/FZaA3pqkZoxFcd5J5lBxWPz7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762419112; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; 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Thu, 06 Nov 2025 03:49:44 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:26 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:26 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 03/12] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2600 and AST1030 Date: Thu, 6 Nov 2025 16:49:12 +0800 Message-ID: <20251106084925.1253704-4-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419115423154100 Content-Type: text/plain; charset="utf-8" According to the design of the AST2600, it has a Silicon Revision ID Register, specifically SCU004 and SCU014, to set the Revision ID for the AST2600. For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303. In the "aspeed_ast2600_scu_reset" function, the hardcoded value "AST2600_A3_SILICON_REV" was used for SCU004, while "s->silicon_rev" was used for SCU014. The value of "s->silicon_rev" is set by the SoC layer via the "silicon-rev" property. This patch aligns both SCU004 and SCU014 to use "s->silicon_rev" for consistency and flexibility. Similarly, the "aspeed_ast1030_scu_reset" function also used a fixed revision constant ("AST1030_A1_SILICON_REV"). This change updates it to use the same "s->silicon_rev" property, ensuring that both SoCs follow a consistent and configurable revision handling mechanism. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index a0ab5eed8f..1f996d5398 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -841,7 +841,7 @@ static void aspeed_ast2600_scu_reset(DeviceState *dev) * of actual revision. QEMU and Linux only support A1 onwards so this = is * sufficient. */ - s->regs[AST2600_SILICON_REV] =3D AST2600_A3_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; @@ -1137,7 +1137,7 @@ static void aspeed_ast1030_scu_reset(DeviceState *dev) =20 memcpy(s->regs, asc->resets, asc->nr_regs * 4); =20 - s->regs[AST2600_SILICON_REV] =3D AST1030_A1_SILICON_REV; + s->regs[AST2600_SILICON_REV] =3D s->silicon_rev; s->regs[AST2600_SILICON_REV2] =3D s->silicon_rev; s->regs[AST2600_HW_STRAP1] =3D s->hw_strap1; s->regs[AST2600_HW_STRAP2] =3D s->hw_strap2; --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; 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dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 176241908060915.076330211859272; Thu, 6 Nov 2025 00:51:20 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvgj-00034U-2T; Thu, 06 Nov 2025 03:49:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgh-000342-Mm; Thu, 06 Nov 2025 03:49:47 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgg-0005Sg-AY; Thu, 06 Nov 2025 03:49:47 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:27 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:27 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 04/12] hhw/misc/aspeed_scu: Add AST1060 A2 silicon revision definition Date: Thu, 6 Nov 2025 16:49:13 +0800 Message-ID: <20251106084925.1253704-5-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419082386158500 Content-Type: text/plain; charset="utf-8" Add a new silicon revision constant AST1060_A2_SILICON_REV for the AST1060 SoC. This allows the SCU model and related SoC layers to identify and handle AST1060 A2 revision properly in the same way as other Aspeed SoC families. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- include/hw/misc/aspeed_scu.h | 1 + hw/misc/aspeed_scu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 684b48b722..76ef8dc592 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -51,6 +51,7 @@ struct AspeedSCUState { #define AST2600_A3_SILICON_REV 0x05030303U #define AST1030_A0_SILICON_REV 0x80000000U #define AST1030_A1_SILICON_REV 0x80010000U +#define AST1060_A2_SILICON_REV 0xA0030000U #define AST2700_A0_SILICON_REV 0x06000103U #define AST2720_A0_SILICON_REV 0x06000203U #define AST2750_A0_SILICON_REV 0x06000003U diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 1f996d5398..300571256a 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -565,6 +565,7 @@ static uint32_t aspeed_silicon_revs[] =3D { AST2600_A3_SILICON_REV, AST1030_A0_SILICON_REV, AST1030_A1_SILICON_REV, + AST1060_A2_SILICON_REV, AST2700_A0_SILICON_REV, AST2720_A0_SILICON_REV, AST2750_A0_SILICON_REV, --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 6 Nov 2025 16:49:27 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:27 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 05/12] hw/arm/aspeed_ast10x0: Add common init function for AST10x0 SoCs Date: Thu, 6 Nov 2025 16:49:14 +0800 Message-ID: <20251106084925.1253704-6-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419051777158500 Content-Type: text/plain; charset="utf-8" Introduce a new common initialization function aspeed_soc_ast10x0_init() for AST10x0 series SoCs. This separates the shared initialization logic from the AST1030-specific part, allowing reuse by future SoCs such as AST1060. The AST1060 does not include the LPC and PECI models, so the common initializer is used for all shared modules, while aspeed_soc_ast1030_init() adds initialization of LPC and PECI, which are unique to AST1030. This refactor improves code reuse and prepares the codebase for supporting the AST1060 platform. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index ca487774ae..5941ebe00c 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -107,7 +107,7 @@ static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCSta= te *s, int dev) return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); } =20 -static void aspeed_soc_ast1030_init(Object *obj) +static void aspeed_soc_ast10x0_init(Object *obj) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj); AspeedSoCState *s =3D ASPEED_SOC(obj); @@ -150,10 +150,6 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "spi[*]", &s->spi[i], typename); } =20 - object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); - - object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); - object_initialize_child(obj, "sbc", &s->sbc, TYPE_ASPEED_AST10X0_SBC); =20 for (i =3D 0; i < sc->wdts_num; i++) { @@ -185,6 +181,15 @@ static void aspeed_soc_ast1030_init(Object *obj) TYPE_UNIMPLEMENTED_DEVICE); } =20 +static void aspeed_soc_ast1030_init(Object *obj) +{ + AspeedSoCState *s =3D ASPEED_SOC(obj); + + aspeed_soc_ast10x0_init(obj); + object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); +} + static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419049; cv=none; d=zohomail.com; s=zohoarc; b=i6b/MQ9nxRPktHfM2dv+zmUa5lXl6wNnIVvOukX2WJX6fpo1tzN2pVQwiMsCcRAZ7r91Z6yODRIxLErRE8NOsON2xAiwo/1n/YreAs1/Dk8rzUpzLA9YPs/BTuOgzh4NsKNNfr8Or0Mz8VJssqAPnFqXtn/1EeMfJV+rKHRYem0= ARC-Message-Signature: i=1; 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Thu, 06 Nov 2025 03:49:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgn-00036U-NB; Thu, 06 Nov 2025 03:49:53 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgl-0005Sg-MN; Thu, 06 Nov 2025 03:49:53 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:28 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:28 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 06/12] hw/arm/aspeed_ast10x0: Add common realize function for AST10x0 SoCs Date: Thu, 6 Nov 2025 16:49:15 +0800 Message-ID: <20251106084925.1253704-7-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419053835158500 Content-Type: text/plain; charset="utf-8" Introduce a new common realize function aspeed_soc_ast10x0_realize() for AST10x0 series SoCs. The shared initialization and realization logic is now placed in this common function to improve code reuse and reduce duplication between different SoCs in the same family. The AST1030 realization function aspeed_soc_ast1030_realize() is updated to call the new common routine and then perform realization of its own specific devices such as LPC and PECI, which are not present on future SoCs like AST1060. This refactor simplifies maintenance and prepares the framework for adding AST1060 support. No functional changes. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 128 ++++++++++++++++++++++------------------ 1 file changed, 70 insertions(+), 58 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 5941ebe00c..5bbe16af24 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -190,10 +190,9 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 -static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { - Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); - AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(a); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); DeviceState *armv7m; Error *err =3D NULL; @@ -203,7 +202,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 if (!clock_has_source(s->sysclk)) { error_setg(errp, "sysclk clock must be wired up by the board code"= ); - return; + return false; } =20 /* General I/O memory space to catch all unimplemented device */ @@ -216,7 +215,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], 0x40000); =20 - /* AST1030 CPU Core */ + /* AST10x0 CPU Core */ armv7m =3D DEVICE(&a->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 256); qdev_prop_set_string(armv7m, "cpu-type", @@ -232,7 +231,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, = &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], @@ -241,14 +240,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sc->secsram_size, &err); if (err !=3D NULL) { error_propagate(errp, err); - return; + return false; } memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], &s->secsram); =20 /* SCU */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); @@ -258,7 +257,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); @@ -271,7 +270,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* I3C */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->i3c), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); @@ -282,50 +281,11 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->i3c.devices[i]), 0, irq); } =20 - /* PECI */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, - sc->memmap[ASPEED_DEV_PECI]); - sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); - - /* LPC */ - if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { - return; - } - aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, - sc->memmap[ASPEED_DEV_LPC]); - - /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, - aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); - - /* - * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. - */ - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); - - sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, - qdev_get_gpio_in(DEVICE(&a->armv7m), - sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); - /* UART */ for (i =3D 0, uart =3D sc->uarts_base; i < sc->uarts_num; i++, uart++)= { if (!aspeed_soc_uart_realize(s->memory, &s->uart[i], sc->memmap[uart], errp)) { - return; + return false; } sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0, aspeed_soc_ast1030_get_irq(s, uart)); @@ -335,7 +295,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->timerctrl), 0, sc->memmap[ASPEED_DEV_TIMER1]); @@ -346,7 +306,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* ADC */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); @@ -357,7 +317,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]); @@ -371,7 +331,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->spi[i]), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->spi[i]), 0, sc->memmap[ASPEED_DEV_SPI1 + i]); @@ -383,7 +343,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) =20 /* Secure Boot Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->sbc), 0, sc->memmap[ASPEED_DEV_SBC]); @@ -392,7 +352,7 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(&s->sram), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); @@ -407,14 +367,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *d= ev_soc, Error **errp) object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu= ), &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->wdt[i]), 0, wdt_offs= et); } =20 /* GPIO */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { - return; + return false; } aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPIO]); @@ -442,6 +402,58 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->jtag[1]), "aspeed.jtag", sc->memmap[ASPEED_DEV_JTAG1], 0x20); + + return true; +} + +static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + AspeedSoCState *s =3D ASPEED_SOC(dev_soc); + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } + + /* PECI */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->peci), 0, + sc->memmap[ASPEED_DEV_PECI]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_PECI)); + + /* LPC */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->lpc), 0, + sc->memmap[ASPEED_DEV_LPC]); + + /* Connect the LPC IRQ to the GIC. It is otherwise unused. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0, + aspeed_soc_ast1030_get_irq(s, ASPEED_DEV_LPC)); + + /* + * On the AST1030 LPC subdevice IRQs are connected straight to the GIC. + */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_1)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_2)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_3)); + + sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, + qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 6 Nov 2025 16:49:28 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:28 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 07/12] hw/arm/aspeed_ast10x0: Pass SoC name to common init for AST10x0 family reuse Date: Thu, 6 Nov 2025 16:49:16 +0800 Message-ID: <20251106084925.1253704-8-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419062516154100 Content-Type: text/plain; charset="utf-8" Refactor the AST10x0 common initialization to accept a socname parameter. The AST1030 model can be reused by AST1060 since they share most of the same controllers. This approach allows AST1060 to leverage the existing AST1030 initialization flow while keeping separate SoC-specific init functions for components that differ. This prepares the framework for AST1060 support, allowing it to reuse AST1030 device models and initialization flow without code duplication. No functional changes. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast10x0.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 5bbe16af24..c85c21b149 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -107,19 +107,14 @@ static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCS= tate *s, int dev) return qdev_get_gpio_in(DEVICE(&a->armv7m), sc->irqmap[dev]); } =20 -static void aspeed_soc_ast10x0_init(Object *obj) +static void aspeed_soc_ast10x0_init(Object *obj, const char *socname) { Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(obj); AspeedSoCState *s =3D ASPEED_SOC(obj); AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); - char socname[8]; char typename[64]; int i; =20 - if (sscanf(object_get_typename(obj), "%7s", socname) !=3D 1) { - g_assert_not_reached(); - } - object_initialize_child(obj, "armv7m", &a->armv7m, TYPE_ARMV7M); =20 s->sysclk =3D qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0); @@ -184,8 +179,13 @@ static void aspeed_soc_ast10x0_init(Object *obj) static void aspeed_soc_ast1030_init(Object *obj) { AspeedSoCState *s =3D ASPEED_SOC(obj); + char socname[8]; + + if (sscanf(object_get_typename(obj), "%7s", socname) !=3D 1) { + g_assert_not_reached(); + } =20 - aspeed_soc_ast10x0_init(obj); + aspeed_soc_ast10x0_init(obj, socname); object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419067; cv=none; d=zohomail.com; s=zohoarc; b=T3StiUSCbdvDTMFEpZ/KUz53gEQrRW7o6hVxHioOj4N+Z9uvyYz01ULNQ2+YlUfVw9lSgPsBOZEjFzWK+evm0DWcJl6EuaN5Xe5+pRE283SzkCZf+rwFJlr7ll5AlHgc2O3ss1g6xY1KkyGmDiiTqYiYVB4iOc/LW9GgR+Vo4JA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762419067; 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Thu, 06 Nov 2025 03:50:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgt-0003QY-J8; Thu, 06 Nov 2025 03:49:59 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvgs-0005Sg-2o; Thu, 06 Nov 2025 03:49:59 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:28 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:28 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 08/12] hw/arm/aspeed_ast10x0: Add AST1060 SoC support Date: Thu, 6 Nov 2025 16:49:17 +0800 Message-ID: <20251106084925.1253704-9-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419067822158500 Content-Type: text/plain; charset="utf-8" Add initial support for the Aspeed AST1060 SoC. The AST1060 reuses most of the AST1030 peripheral device models, as the two SoCs share nearly the same controllers including WDT, SCU, TIMER, HACE, ADC, I2C, FMC, and SPI. A new common initialization and realization framework (ast10x0_init and ast10x0_realize) is leveraged so AST1060 can instantiate the existing AST1030 models without redefining duplicate device types. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast10x0.c | 61 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index c85c21b149..17f5285d85 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -190,6 +190,25 @@ static void aspeed_soc_ast1030_init(Object *obj) object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI); } =20 +static void aspeed_soc_ast1060_init(Object *obj) +{ + char socname[8] =3D "ast1030"; + + /* + * The AST1060 SoC reuses the AST1030 device models. Since all periphe= ral + * models (e.g. WDT, SCU, TIMER, HACE, ADC, I2C, FMC, SPI) defined for + * AST1030 are compatible with AST1060, we simply reuse the existing + * AST1030 models for AST1060. + * + * To simplify the implementation, AST1060 sets its socname to that of + * AST1030, avoiding the need to create a full set of new + * TYPE_ASPEED_1060_XXX device definitions. This allows the same + * TYPE_ASPEED_1030_WDT and other models to be instantiated for both + * SoCs. + */ + aspeed_soc_ast10x0_init(obj, socname); +} + static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) { AspeedSoCState *s =3D ASPEED_SOC(a); @@ -456,6 +475,15 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); } =20 +static void aspeed_soc_ast1060_realize(DeviceState *dev_soc, Error **errp) +{ + Aspeed10x0SoCState *a =3D ASPEED10X0_SOC(dev_soc); + + if (!aspeed_soc_ast10x0_realize(a, errp)) { + return; + } +} + static void aspeed_soc_ast1030_class_init(ObjectClass *klass, const void *= data) { static const char * const valid_cpu_types[] =3D { @@ -484,6 +512,32 @@ static void aspeed_soc_ast1030_class_init(ObjectClass = *klass, const void *data) sc->num_cpus =3D 1; } =20 +static void aspeed_soc_ast1060_class_init(ObjectClass *klass, const void *= data) +{ + static const char * const valid_cpu_types[] =3D { + ARM_CPU_TYPE_NAME("cortex-m4"), /* TODO cortex-m4f */ + NULL + }; + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSoCClass *sc =3D ASPEED_SOC_CLASS(dc); + + /* Reason: The Aspeed SoC can only be instantiated from a board */ + dc->user_creatable =3D false; + dc->realize =3D aspeed_soc_ast1060_realize; + + sc->valid_cpu_types =3D valid_cpu_types; + sc->silicon_rev =3D AST1060_A2_SILICON_REV; + sc->sram_size =3D 0xc0000; + sc->secsram_size =3D 0x40000; /* 256 * KiB */ + sc->spis_num =3D 2; + sc->wdts_num =3D 4; + sc->uarts_num =3D 1; + sc->uarts_base =3D ASPEED_DEV_UART5; + sc->irqmap =3D aspeed_soc_ast1030_irqmap; + sc->memmap =3D aspeed_soc_ast1030_memmap; + sc->num_cpus =3D 1; +} + static const TypeInfo aspeed_soc_ast10x0_types[] =3D { { .name =3D TYPE_ASPEED10X0_SOC, @@ -495,7 +549,12 @@ static const TypeInfo aspeed_soc_ast10x0_types[] =3D { .parent =3D TYPE_ASPEED10X0_SOC, .instance_init =3D aspeed_soc_ast1030_init, .class_init =3D aspeed_soc_ast1030_class_init, - }, + }, { + .name =3D "ast1060-a2", + .parent =3D TYPE_ASPEED10X0_SOC, + .instance_init =3D aspeed_soc_ast1060_init, + .class_init =3D aspeed_soc_ast1060_class_init, + } }; =20 DEFINE_TYPES(aspeed_soc_ast10x0_types) --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419065; cv=none; d=zohomail.com; s=zohoarc; b=bFN+xRComnurw3+Mfz5C7471xO9u/QZb6O+e71d7tY/SokX/9yw0zjETXm+3T2/NGaoQmeYqc1cgOS1eWh5C7BpFy4JCqTNK8OvH0ORDRZ+4OfcUvR3QdpcIWxkNmq40SobdRvsM47bpqpaf9fWAymRbTOcTZk92HVPnKT4k6QA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762419065; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=x0bGa8O+NoCT6K+Rel6hK3XTt45GVlw4eE9U/m47Z9I=; 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Thu, 06 Nov 2025 03:50:02 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:29 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:29 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 09/12] hw/arm/aspeed_ast10x0_evb: Add AST1060 EVB machine support Date: Thu, 6 Nov 2025 16:49:18 +0800 Message-ID: <20251106084925.1253704-10-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419066566154100 Content-Type: text/plain; charset="utf-8" Add a new machine definition ast1060-evb to support the Aspeed AST1060 evaluation board. The new EVB reuses the same MiniBMC framework used by AST1030, as both SoCs share the same core peripherals and controller designs. The AST1060 EVB machine initializes the ast1060-a2 SoC and sets the FMC and SPI flash models (w25q80bl and w25q02jvm) for simulation. This enables QEMU to boot and emulate firmware images for AST1060-based platforms. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0_evb.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c index 7af2a77865..a01385b543 100644 --- a/hw/arm/aspeed_ast10x0_evb.c +++ b/hw/arm/aspeed_ast10x0_evb.c @@ -96,12 +96,35 @@ static void aspeed_minibmc_machine_ast1030_evb_class_in= it(ObjectClass *oc, aspeed_machine_class_init_cpus_defaults(mc); } =20 +static void aspeed_minibmc_machine_ast1060_evb_class_init(ObjectClass *oc, + const void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Aspeed AST1060 PFR (Cortex-M4)"; + amc->soc_name =3D "ast1060-a2"; + amc->hw_strap1 =3D 0; + amc->hw_strap2 =3D 0; + mc->init =3D aspeed_minibmc_machine_init; + amc->fmc_model =3D "w25q80bl"; + amc->spi_model =3D "w25q02jvm"; + amc->num_cs =3D 2; + amc->macs_mask =3D 0; + aspeed_machine_class_init_cpus_defaults(mc); +} + static const TypeInfo aspeed_ast10x0_evb_types[] =3D { { .name =3D MACHINE_TYPE_NAME("ast1030-evb"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_minibmc_machine_ast1030_evb_class_init, .interfaces =3D arm_machine_interfaces, + }, { + .name =3D MACHINE_TYPE_NAME("ast1060-evb"), + .parent =3D TYPE_ASPEED_MACHINE, + .class_init =3D aspeed_minibmc_machine_ast1060_evb_class_init, + .interfaces =3D arm_machine_interfaces, } }; =20 --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419142; cv=none; d=zohomail.com; s=zohoarc; b=gPlljgCA+bNqIPuAgjlObjmK+7ZKoIAkNMw3ZkzK2whzQqUr5lWWncQx/ciFuCjdgjiFzjvMuSFHTAxxRKxoP/7NvtLFrM2N9qhrxep38Vc8u6CXVjXo0mWZ3evR35vs+HeX/YjzsBMSkdYU1wKK5DB2ald/Pq/KG2wE2TVt0Q4= ARC-Message-Signature: i=1; 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Thu, 06 Nov 2025 03:50:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvh1-0003j9-WB; Thu, 06 Nov 2025 03:50:08 -0500 Received: from mail.aspeedtech.com ([211.20.114.72] helo=TWMBX01.aspeed.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvh0-0005ZE-7P; Thu, 06 Nov 2025 03:50:07 -0500 Received: from TWMBX01.aspeed.com (192.168.0.62) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 6 Nov 2025 16:49:29 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:29 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 10/12] tests/functional/arm/test_aspeed_ast1060: Add functional tests for Aspeed AST1060 SoC Date: Thu, 6 Nov 2025 16:49:19 +0800 Message-ID: <20251106084925.1253704-11-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419146480158500 Content-Type: text/plain; charset="utf-8" Add functional tests for the Aspeed AST1060 SoC and its evaluation board. The new test test_aspeed_ast1060.py validates booting the AST1060 EVB machine using the Zephyr OS and ASPEED PROT application (ast1060_prot_v03.0= 2.tgz) and ensures basic console functionality. Signed-off-by: Jamin Lin --- tests/functional/arm/meson.build | 1 + tests/functional/arm/test_aspeed_ast1060.py | 52 +++++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 tests/functional/arm/test_aspeed_ast1060.py diff --git a/tests/functional/arm/meson.build b/tests/functional/arm/meson.= build index d1ed076a6a..1762a49604 100644 --- a/tests/functional/arm/meson.build +++ b/tests/functional/arm/meson.build @@ -28,6 +28,7 @@ tests_arm_system_quick =3D [ =20 tests_arm_system_thorough =3D [ 'aspeed_ast1030', + 'aspeed_ast1060', 'aspeed_palmetto', 'aspeed_romulus', 'aspeed_witherspoon', diff --git a/tests/functional/arm/test_aspeed_ast1060.py b/tests/functional= /arm/test_aspeed_ast1060.py new file mode 100644 index 0000000000..034efa5342 --- /dev/null +++ b/tests/functional/arm/test_aspeed_ast1060.py @@ -0,0 +1,52 @@ +#!/usr/bin/env python3 +# +# Functional test that boots the ASPEED SoCs with firmware +# +# Copyright (C) 2025 ASPEED Technology Inc +# +# SPDX-License-Identifier: GPL-2.0-or-later + +from aspeed import AspeedTest +from qemu_test import Asset, exec_command_and_wait_for_pattern + + +class AST1060Machine(AspeedTest): + ASSET_ASPEED_AST1060_PROT_3_02 =3D Asset( + ('https://github.com/AspeedTech-BMC' + '/aspeed-zephyr-project/releases/download/v03.02' + '/ast1060_prot_v03.02.tgz'), + 'dd5f1adc935316ddd1906506a02e15567bd7290657b52320f1a225564cc175bd= ') + + def test_arm_ast1060_prot_3_02(self): + self.set_machine('ast1060-evb') + + kernel_name =3D "ast1060_prot/zephyr.bin" + kernel_file =3D self.archive_extract( + self.ASSET_ASPEED_AST1060_PROT_3_02, member=3Dkernel_name) + + self.vm.set_console() + self.vm.add_args('-kernel', kernel_file, '-nographic') + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + exec_command_and_wait_for_pattern(self, "help", + "Available commands") + + def test_arm_ast1060_otp_blockdev_device(self): + self.vm.set_machine("ast1060-evb") + + kernel_name =3D "ast1060_prot/zephyr.bin" + kernel_file =3D self.archive_extract(self.ASSET_ASPEED_AST1060_PRO= T_3_02, + member=3Dkernel_name) + otp_img =3D self.generate_otpmem_image() + + self.vm.set_console() + self.vm.add_args( + "-kernel", kernel_file, + "-blockdev", f"driver=3Dfile,filename=3D{otp_img},node-name=3D= otp", + "-global", "aspeed-otp.drive=3Dotp", + ) + self.vm.launch() + self.wait_for_console_pattern("Booting Zephyr OS") + +if __name__ =3D=3D '__main__': + AspeedTest.main() --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1762419093; cv=none; d=zohomail.com; s=zohoarc; b=kFkiG9ywkLumvtM8DmurjcG//JaXzaptBGAJCPiYUFM4bRhJAoH0OAnlxHkotr2Q3BnsIdHWujFL/Ts+NyxzCN9PGe9v9FLH/ehS6TUvZJ41FAWRtfvMB7N7XkkGuMqxLufxDvv9Gw/BXAGW2nKR7GBvd8Rs05M1l7e40MRK1ZA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1762419093; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=FyRgZfdRY1JYYHf1Cbx6EuUEqLnNxzRVgtfuke8y53I=; b=GeqoHmUE5jruCZA5onZQ+wODVg9xTnz0s7DDGf4TtU0h6OY/YmnpzP4mkF4ip4SA+g8isSqtoQwCZuER+u7Yh7dT+orkyHVd46A85pyY5yoOe5Y0SV87Mj+yIJBNNW9JpfmGseKEp81qYBd3JcJ3VbVKVryhC0qfXf2sCFF3SWw= ARC-Authentication-Results: i=1; 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Thu, 6 Nov 2025 16:49:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 11/12] docs/system/arm/aspeed: Update Aspeed and 2700 family boards list Date: Thu, 6 Nov 2025 16:49:20 +0800 Message-ID: <20251106084925.1253704-12-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419098067158500 Content-Type: text/plain; charset="utf-8" Remove the ast2700-evb entry from the Aspeed family boards list in the documentation. The AST2700 platform now belongs to the new Aspeed 2700 family group, which has its own dedicated documentation section and board definitions. Update the Aspeed 2700 family boards list in the documentation to include the new ast2700fc board entry. Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6317c0e910..a0c05a6f73 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -1,4 +1,4 @@ -Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``ast2700-evb``, `= `bletchley-bmc``, ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2= -bmc``, ``g220a-bmc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-fir= ework-bmc``, ``quanta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonor= apass-bmc``, ``supermicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-b= mc``, ``witherspoon-bmc``, ``yosemitev2-bmc``) +Aspeed family boards (``ast2500-evb``, ``ast2600-evb``, ``bletchley-bmc``,= ``fuji-bmc``, ``gb200nvl-bmc``, ``fby35-bmc``, ``fp5280g2-bmc``, ``g220a-b= mc``, ``palmetto-bmc``, ``qcom-dc-scm-v1-bmc``, ``qcom-firework-bmc``, ``qu= anta-q71l-bmc``, ``rainier-bmc``, ``romulus-bmc``, ``sonorapass-bmc``, ``su= permicrox11-bmc``, ``supermicrox11spi-bmc``, ``tiogapass-bmc``, ``witherspo= on-bmc``, ``yosemitev2-bmc``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of various OpenPOWER systems and @@ -274,7 +274,7 @@ configuration file for OTP memory: done > otpmem.img fi =20 -Aspeed 2700 family boards (``ast2700-evb``) +Aspeed 2700 family boards (``ast2700-evb``, ``ast2700fc``) =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 The QEMU Aspeed machines model BMCs of Aspeed evaluation boards. --=20 2.43.0 From nobody Fri Nov 14 15:22:00 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 6 Nov 2025 16:49:30 +0800 Received: from mail.aspeedtech.com (192.168.10.10) by TWMBX01.aspeed.com (192.168.0.62) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Thu, 6 Nov 2025 16:49:30 +0800 To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Steven Lee , Troy Lee , Andrew Jeffery , "Joel Stanley" , Alistair Francis , "Kevin Wolf" , Hanna Reitz , "open list:ASPEED BMCs" , "open list:All patches CC here" , "open list:Block layer core" CC: , , Subject: [PATCH v1 12/12] docs/system/arm/aspeed: Update Aspeed MiniBMC section to include AST1060 PFR processor Date: Thu, 6 Nov 2025 16:49:21 +0800 Message-ID: <20251106084925.1253704-13-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> References: <20251106084925.1253704-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.72; envelope-from=jamin_lin@aspeedtech.com; helo=TWMBX01.aspeed.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_FAIL=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jamin Lin From: Jamin Lin via Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762419067807158500 Content-Type: text/plain; charset="utf-8" Added details describing AST1060 as a PFR processor board alongside AST1030 MiniBMC, and extended the list of missing devices to include SMBus Filter and QSPI Monitor controllers. Signed-off-by: Jamin Lin --- docs/system/arm/aspeed.rst | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index a0c05a6f73..ffa5f4b372 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -448,23 +448,25 @@ Use ``tio`` or another terminal emulator to connect t= o the consoles: $ tio /dev/pts/57 =20 =20 -Aspeed minibmc family boards (``ast1030-evb``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Aspeed minibmc and PFR processor family boards (``ast1030-evb``, ``ast1060= -evb``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D =20 -The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation -boards. They are based on different releases of the -Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). +The QEMU Aspeed machines model mini BMCs and PFR processors of various Asp= eed +evaluation boards. They are based on different releases of the +Aspeed SoC : the AST1030 (MiniBMC) and AST1060 (PFR Processor), both integ= rating +an ARM Cortex M4F CPU (200MHz). =20 The SoC comes with SRAM, SPI, I2C, etc. =20 -AST1030 SoC based machines : +AST10x0 SoC based machines : =20 -- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) +- ``ast1030-evb`` Aspeed AST1030 MiniBMC Evaluation board (Cortex= -M4F) +- ``ast1060-evb`` Aspeed AST1060 PFR Processor Evaluation board (Cortex= -M4F) =20 Supported devices ----------------- =20 - * SMP (for the AST1030 Cortex-M4F) + * SMP (for the Cortex-M4F) * Interrupt Controller (VIC) * Timer Controller * I2C Controller @@ -492,6 +494,8 @@ Missing devices * Virtual UART * eSPI Controller * I3C Controller + * SMBus Filter Controller + * QSPI Monitor Controller =20 Boot options ------------ @@ -502,9 +506,11 @@ ASPEED GitHub release repository : =20 https://github.com/AspeedTech-BMC/zephyr/releases =20 + https://github.com/AspeedTech-BMC/aspeed-zephyr-project/releases + To boot a kernel directly from a Zephyr build tree: =20 .. code-block:: bash =20 $ qemu-system-arm -M ast1030-evb -nographic \ - -kernel zephyr.elf + -kernel zephyr.bin --=20 2.43.0