From nobody Fri Nov 14 15:22:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762418512758196.75378734382048; Thu, 6 Nov 2025 00:41:52 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvYC-0007T9-RD; Thu, 06 Nov 2025 03:41:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvY6-0007SC-T0 for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:54 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvY4-00082H-O7 for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:54 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cx778NXwxpUJ8fAA--.1194S3; Thu, 06 Nov 2025 16:40:45 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJBxpeQMXwxpVnIpAQ--.58291S3; Thu, 06 Nov 2025 16:40:44 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 1/3] target/loongarch: Add detailed information with CPU Product ID Date: Thu, 6 Nov 2025 16:40:41 +0800 Message-Id: <20251106084043.2453749-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251106084043.2453749-1-maobibo@loongson.cn> References: <20251106084043.2453749-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJBxpeQMXwxpVnIpAQ--.58291S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762418515443158500 Content-Type: text/plain; charset="utf-8" CPUCFG0 is LoongArch CPU Product ID, it is a combination of Vendor ID, Series ID and Product ID, here is the layout: +-------------+----------------+------------+----------------+ | Reserved | Vendor ID | Series ID | Product ID | +-------------+----------------+------------+----------------+ 31 24 23 16 15 12 11 0 Here adds detailed information with CPUCFG0, it is convenient to add such information with host or LA664 CPU type in future. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 12 ++++++++++-- target/loongarch/cpu.h | 10 +++++++++- 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index d74c3c3766..68ae3aff97 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -278,8 +278,12 @@ static void loongarch_la464_initfn(Object *obj) } =20 cpu->dtb_compatible =3D "loongarch,Loongson-3A5000"; - env->cpucfg[0] =3D 0x14c010; /* PRID */ + data =3D FIELD_DP32(data, CPUCFG0, PRID, 0x10); + data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA464); + data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); + env->cpucfg[0] =3D data; =20 + data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 2); data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); @@ -385,8 +389,12 @@ static void loongarch_la132_initfn(Object *obj) } =20 cpu->dtb_compatible =3D "loongarch,Loongson-1C103"; - env->cpucfg[0] =3D 0x148042; /* PRID */ + data =3D FIELD_DP32(data, CPUCFG0, PRID, 0x42); + data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA132); + data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); + env->cpucfg[0] =3D data; =20 + data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ data =3D FIELD_DP32(data, CPUCFG1, PGMMU, 1); data =3D FIELD_DP32(data, CPUCFG1, IOCSR, 1); diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 1a14469b3b..c00ad67457 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -97,7 +97,15 @@ FIELD(FCSR0, CAUSE, 24, 5) #define EXCCODE_DBP EXCODE(26, 0) /* Reserved subcode use= d for debug */ =20 /* cpucfg[0] bits */ -FIELD(CPUCFG0, PRID, 0, 32) +FIELD(CPUCFG0, PRID, 0, 12) +FIELD(CPUCFG0, SERID, 12, 4) +FIELD(CPUCFG0, VENID, 16, 8) +#define PRID_SERIES_LA132 0x8 /* Loongson 32bit */ +#define PRID_SERIES_LA264 0xa /* Loongson 64bit, 2-issue */ +#define PRID_SERIES_LA364 0xb /* Loongson 64bit, 3-issue */ +#define PRID_SERIES_LA464 0xc /* Loongson 64bit, 4-issue */ +#define PRID_SERIES_LA664 0xd /* Loongson 64bit, 6-issue */ +#define PRID_VENDOR_LOONGSON 0x14 =20 /* cpucfg[1] bits */ FIELD(CPUCFG1, ARCH, 0, 2) base-commit: a8e63c013016f9ff981689189c5b063551d04559 --=20 2.39.3 From nobody Fri Nov 14 15:22:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762418510393915.871817848531; Thu, 6 Nov 2025 00:41:50 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvYF-0007Tm-Oy; Thu, 06 Nov 2025 03:41:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvY7-0007SO-RO for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:56 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvY5-00082f-4J for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:55 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Cxrr8PXwxpVJ8fAA--.1721S3; Thu, 06 Nov 2025 16:40:47 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+QPXwxpWXIpAQ--.58753S2; Thu, 06 Nov 2025 16:40:47 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 2/3] target/loongarch: Add generic CPU model information Date: Thu, 6 Nov 2025 16:40:42 +0800 Message-Id: <20251106084043.2453749-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251106084043.2453749-1-maobibo@loongson.cn> References: <20251106084043.2453749-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+QPXwxpWXIpAQ--.58753S2 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762418515297158500 Content-Type: text/plain; charset="utf-8" On LoongArch system, CPU model name comes from IOCSR register LOONGARCH_IOCSR_VENDOR and LOONGARCH_IOCSR_CPUNAME. Its value can be initialized when CPU is created. Signed-off-by: Bibo Mao --- hw/loongarch/virt.c | 6 ++++-- target/loongarch/cpu.c | 4 ++++ target/loongarch/cpu.h | 6 ++++++ 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index 49434ad182..3ae723239f 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -635,7 +635,9 @@ static MemTxResult virt_iocsr_misc_read(void *opaque, h= waddr addr, LoongArchVirtMachineState *lvms =3D LOONGARCH_VIRT_MACHINE(opaque); uint64_t ret =3D 0; int features; + CPULoongArchState *env; =20 + env =3D &LOONGARCH_CPU(first_cpu)->env; switch (addr) { case VERSION_REG: ret =3D 0x11ULL; @@ -650,10 +652,10 @@ static MemTxResult virt_iocsr_misc_read(void *opaque,= hwaddr addr, } break; case VENDOR_REG: - ret =3D 0x6e6f73676e6f6f4cULL; /* "Loongson" */ + ret =3D env->vendor_id; break; case CPUNAME_REG: - ret =3D 0x303030354133ULL; /* "3A5000" */ + ret =3D env->cpu_id; break; case MISC_FUNC_REG: if (kvm_irqchip_in_kernel()) { diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 68ae3aff97..8b8723a343 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -282,6 +282,8 @@ static void loongarch_la464_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA464); data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); env->cpucfg[0] =3D data; + memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8); + memccpy((void *)&env->cpu_id, CPU_MODEL_3A5000, 0, 8); =20 data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 2); @@ -393,6 +395,8 @@ static void loongarch_la132_initfn(Object *obj) data =3D FIELD_DP32(data, CPUCFG0, SERID, PRID_SERIES_LA132); data =3D FIELD_DP32(data, CPUCFG0, VENID, PRID_VENDOR_LOONGSON); env->cpucfg[0] =3D data; + memccpy((void *)&env->vendor_id, CPU_VENDOR_LOONGSON, 0, 8); + memccpy((void *)&env->cpu_id, CPU_MODEL_1C101, 0, 8); =20 data =3D 0; data =3D FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index c00ad67457..6cda47ee96 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -301,6 +301,10 @@ typedef struct LoongArchBT { uint32_t ftop; } lbt_t; =20 +#define CPU_VENDOR_LOONGSON "Loongson" +#define CPU_MODEL_3A5000 "3A5000" +#define CPU_MODEL_1C101 "1C101" + typedef struct CPUArchState { uint64_t gpr[32]; uint64_t pc; @@ -312,6 +316,8 @@ typedef struct CPUArchState { =20 uint32_t cpucfg[21]; uint32_t pv_features; + uint64_t vendor_id; + uint64_t cpu_id; =20 /* LoongArch CSRs */ uint64_t CSR_CRMD; --=20 2.39.3 From nobody Fri Nov 14 15:22:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1762418507897510.40206820298295; Thu, 6 Nov 2025 00:41:47 -0800 (PST) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvYF-0007Tl-OD; Thu, 06 Nov 2025 03:41:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1vGvY7-0007SP-Vj for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:56 -0500 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1vGvY4-00082k-QH for qemu-devel@nongnu.org; Thu, 06 Nov 2025 03:40:55 -0500 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxxtAQXwxpVp8fAA--.1879S3; Thu, 06 Nov 2025 16:40:48 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxM+QPXwxpWXIpAQ--.58753S3; Thu, 06 Nov 2025 16:40:47 +0800 (CST) From: Bibo Mao To: Song Gao Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH 3/3] target/loongarch: Add host CPU model in kvm mode Date: Thu, 6 Nov 2025 16:40:43 +0800 Message-Id: <20251106084043.2453749-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20251106084043.2453749-1-maobibo@loongson.cn> References: <20251106084043.2453749-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxM+QPXwxpWXIpAQ--.58753S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1762418515502154100 Content-Type: text/plain; charset="utf-8" Host CPU model is basically the same with max CPU model, except Product ID and CPU model name. With host CPU model, Product ID comes from cpucfg0 and CPU model comes from /proc/cpuinfo. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 94 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 8b8723a343..c7f52adeb9 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -429,6 +429,97 @@ static void loongarch_max_initfn(Object *obj) } } =20 +#if defined(CONFIG_KVM) +static int read_cpuinfo(const char *field, char *value, int len) +{ + FILE *f; + int ret =3D -1; + int field_len =3D strlen(field); + char line[512]; + + f =3D fopen("/proc/cpuinfo", "r"); + if (!f) { + return -1; + } + + do { + if (!fgets(line, sizeof(line), f)) { + break; + } + if (!strncmp(line, field, field_len)) { + strncpy(value, line, len); + ret =3D 0; + break; + } + } while (*line); + + fclose(f); + + return ret; +} + +static uint64_t get_host_cpu_model(void) +{ + char line[512]; + char *ns; + static uint64_t cpuid; + + if (cpuid) { + return cpuid; + } + + if (read_cpuinfo("Model Name", line, sizeof(line))) { + return 0; + } + + ns =3D strchr(line, ':'); + if (!ns) { + return 0; + } + + ns =3D strstr(ns, "Loongson-"); + if (!ns) { + return 0; + } + + ns +=3D strlen("Loongson-"); + memccpy((void *)&cpuid, ns, 0, 8); + return cpuid; +} + +static uint32_t get_host_cpucfg(int number) +{ + unsigned int data =3D 0; + +#ifdef __loongarch__ + asm volatile("cpucfg %[val], %[reg]" + : [val] "=3Dr" (data) + : [reg] "r" (number) + : "memory"); +#endif + + return data; +} + +static void loongarch_host_initfn(Object *obj) +{ + uint32_t data; + uint64_t cpuid; + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + + loongarch_max_initfn(obj); + data =3D get_host_cpucfg(0); + if (data) { + cpu->env.cpucfg[0] =3D data; + } + + cpuid =3D get_host_cpu_model(); + if (cpuid) { + cpu->env.cpu_id =3D cpuid; + } +} +#endif + static void loongarch_cpu_reset_hold(Object *obj, ResetType type) { uint8_t tlb_ps; @@ -780,6 +871,9 @@ static const TypeInfo loongarch_cpu_type_infos[] =3D { DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), DEFINE_LOONGARCH_CPU_TYPE(64, "max", loongarch_max_initfn), +#if defined(CONFIG_KVM) + DEFINE_LOONGARCH_CPU_TYPE(64, "host", loongarch_host_initfn), +#endif }; =20 DEFINE_TYPES(loongarch_cpu_type_infos) --=20 2.39.3